llvm.org GIT mirror llvm / e4b2165
[PowerPC] Fix FrameIndex handling in SelectAddressRegImm The PPCTargetLowering::SelectAddressRegImm routine needs to handle FrameIndex nodes in a special manner, by tranlating them into a TargetFrameIndex node. This was done in most cases, but seems to have been neglected in one path: when the input tree has an OR of the FrameIndex with an immediate. This can happen if the FrameIndex can be proven to be sufficiently aligned that an OR of that immediate is equivalent to an ADD. The missing handling of FrameIndex in that case caused the SelectionDAG instruction selection to miss opportunities to merge the OR back into the FrameIndex node, leading to superfluous addi/ori instructions in the final assembler output. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213482 91177308-0d34-0410-b5e6-96231b3b80d8 Ulrich Weigand 5 years ago
4 changed file(s) with 18 addition(s) and 20 deletion(s). Raw diff Collapse all Expand all
13301330 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
13311331 // If all of the bits are known zero on the LHS or RHS, the add won't
13321332 // carry.
1333 Base = N.getOperand(0);
1333 if (FrameIndexSDNode *FI =
1334 dyn_cast(N.getOperand(0))) {
1335 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1336 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1337 } else {
1338 Base = N.getOperand(0);
1339 }
13341340 Disp = DAG.getTargetConstant(imm, N.getValueType());
13351341 return true;
13361342 }
6161 }
6262
6363 ; CHECK-LABEL: func2:
64 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
65 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
64 ; CHECK: ld [[REG2:[0-9]+]], 72(1)
6665 ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
6766 ; CHECK-DAG: std [[REG2]], -[[OFFSET1:[0-9]+]]
6867 ; CHECK-DAG: std 4, -[[OFFSET2:[0-9]+]]
8180 ; DARWIN32: lwz r3, -[[OFFSET2]]
8281
8382 ; DARWIN64: _func2:
84 ; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64
85 ; DARWIN64: ld r[[REG2:[0-9]+]], 8(r[[REG1]])
83 ; DARWIN64: ld r[[REG2:[0-9]+]], 72(r1)
8684 ; DARWIN64: mr
8785 ; DARWIN64: mr r[[REG3:[0-9]+]], r[[REGA:[0-9]+]]
8886 ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REGA]], r[[REG2]]
107105 }
108106
109107 ; CHECK-LABEL: func3:
110 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
111 ; CHECK: addi [[REG2:[0-9]+]], 1, 48
112 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
113 ; CHECK: ld [[REG4:[0-9]+]], 8([[REG2]])
108 ; CHECK: ld [[REG3:[0-9]+]], 72(1)
109 ; CHECK: ld [[REG4:[0-9]+]], 56(1)
114110 ; CHECK: cmpld {{[0-9]+}}, [[REG4]], [[REG3]]
115111 ; CHECK: std [[REG3]], -[[OFFSET1:[0-9]+]](1)
116112 ; CHECK: std [[REG4]], -[[OFFSET2:[0-9]+]](1)
129125 ; DARWIN32: lwz r3, -[[OFFSET1]]
130126
131127 ; DARWIN64: _func3:
132 ; DARWIN64: addi r[[REG1:[0-9]+]], r1, 64
133 ; DARWIN64: addi r[[REG2:[0-9]+]], r1, 48
134 ; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]])
135 ; DARWIN64: ld r[[REG4:[0-9]+]], 8(r[[REG2]])
128 ; DARWIN64: ld r[[REG3:[0-9]+]], 72(r1)
129 ; DARWIN64: ld r[[REG4:[0-9]+]], 56(r1)
136130 ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG4]], r[[REG3]]
137131 ; DARWIN64: std r[[REG3]], -[[OFFSET1:[0-9]+]]
138132 ; DARWIN64: std r[[REG4]], -[[OFFSET2:[0-9]+]]
156150 }
157151
158152 ; CHECK-LABEL: func4:
159 ; CHECK: addi [[REG1:[0-9]+]], 1, 128
153 ; CHECK: ld [[REG3:[0-9]+]], 136(1)
160154 ; CHECK: ld [[REG2:[0-9]+]], 120(1)
161 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
162155 ; CHECK: cmpld {{[0-9]+}}, [[REG2]], [[REG3]]
156 ; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
163157 ; CHECK: std [[REG2]], -[[OFFSET1:[0-9]+]](1)
164 ; CHECK: std [[REG3]], -[[OFFSET2:[0-9]+]](1)
165158 ; CHECK: ld 3, -[[OFFSET1]](1)
166159 ; CHECK: ld 3, -[[OFFSET2]](1)
167160
177170 ; DARWIN32: lwz r[[REG1]], -[[OFFSET2]]
178171
179172 ; DARWIN64: _func4:
180 ; DARWIN64: addi r[[REG1:[0-9]+]], r1, 128
181173 ; DARWIN64: ld r[[REG2:[0-9]+]], 120(r1)
182 ; DARWIN64: ld r[[REG3:[0-9]+]], 8(r[[REG1]])
174 ; DARWIN64: ld r[[REG3:[0-9]+]], 136(r1)
183175 ; DARWIN64: mr r[[REG4:[0-9]+]], r[[REG2]]
184176 ; DARWIN64: cmpld cr{{[0-9]+}}, r[[REG2]], r[[REG3]]
185177 ; DARWIN64: std r[[REG4]], -[[OFFSET1:[0-9]+]]
2525 ; CHECK-LABEL: foo:
2626 ; CHECK: lfd 3
2727 ; CHECK: lfd 4
28 ; CHECK: lfd 1
2829 ; CHECK: lfd 2
29 ; CHECK: lfd 1
3030
3131 define { float, float } @oof() nounwind {
3232 entry:
633633 ; CHECK-DAG: addi [[R1:[0-9]+]], 3, 3
634634 ; CHECK-DAG: addi [[R2:[0-9]+]], 1, -16
635635 ; CHECK-DAG: addi [[R3:[0-9]+]], 3, 2
636 ; CHECK: std [[R1]], 8([[R2]])
636 ; CHECK: std [[R1]], -8(1)
637637 ; CHECK: std [[R3]], -16(1)
638638 ; CHECK: lxvd2x 34, 0, [[R2]]
639639 ; CHECK-NOT: stxvd2x