llvm.org GIT mirror llvm / e4a40f7
Remove the need to cache the subtarget in the PowerPC TargetRegisterInfo classes. Replace it with a cache to the TargetMachine and use that where applicable at the moment. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232002 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
3 changed file(s) with 68 addition(s) and 55 deletion(s). Raw diff Collapse all Expand all
6060
6161 PPCInstrInfo::PPCInstrInfo(PPCSubtarget &STI)
6262 : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
63 Subtarget(STI), RI(STI) {}
63 Subtarget(STI), RI(STI.getTargetMachine()) {}
6464
6565 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
6666 /// this target when scheduling the DAG.
1717 #include "PPCInstrBuilder.h"
1818 #include "PPCMachineFunctionInfo.h"
1919 #include "PPCSubtarget.h"
20 #include "PPCTargetMachine.h"
2021 #include "llvm/ADT/BitVector.h"
2122 #include "llvm/ADT/STLExtras.h"
2223 #include "llvm/CodeGen/MachineFrameInfo.h"
5556 AlwaysBasePointer("ppc-always-use-base-pointer", cl::Hidden, cl::init(false),
5657 cl::desc("Force the use of a base pointer in every function"));
5758
58 PPCRegisterInfo::PPCRegisterInfo(const PPCSubtarget &ST)
59 : PPCGenRegisterInfo(ST.isPPC64() ? PPC::LR8 : PPC::LR,
60 ST.isPPC64() ? 0 : 1,
61 ST.isPPC64() ? 0 : 1),
62 Subtarget(ST) {
59 PPCRegisterInfo::PPCRegisterInfo(const PPCTargetMachine &TM)
60 : PPCGenRegisterInfo(TM.isPPC64() ? PPC::LR8 : PPC::LR,
61 TM.isPPC64() ? 0 : 1,
62 TM.isPPC64() ? 0 : 1),
63 TM(TM) {
6364 ImmToIdxMap[PPC::LD] = PPC::LDX; ImmToIdxMap[PPC::STD] = PPC::STDX;
6465 ImmToIdxMap[PPC::LBZ] = PPC::LBZX; ImmToIdxMap[PPC::STB] = PPC::STBX;
6566 ImmToIdxMap[PPC::LHZ] = PPC::LHZX; ImmToIdxMap[PPC::LHA] = PPC::LHAX;
8687 // Note that PPCInstrInfo::FoldImmediate also directly uses this Kind value
8788 // when it checks for ZERO folding.
8889 if (Kind == 1) {
89 if (Subtarget.isPPC64())
90 if (TM.isPPC64())
9091 return &PPC::G8RC_NOX0RegClass;
9192 return &PPC::GPRC_NOR0RegClass;
9293 }
9394
94 if (Subtarget.isPPC64())
95 if (TM.isPPC64())
9596 return &PPC::G8RCRegClass;
9697 return &PPC::GPRCRegClass;
9798 }
9899
99100 const MCPhysReg*
100101 PPCRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
102 const PPCSubtarget &Subtarget = MF->getSubtarget();
101103 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg) {
102104 if (Subtarget.hasVSX())
103105 return CSR_64_AllRegs_VSX_SaveList;
107109 }
108110
109111 if (Subtarget.isDarwinABI())
110 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
111 CSR_Darwin64_Altivec_SaveList :
112 CSR_Darwin64_SaveList) :
113 (Subtarget.hasAltivec() ?
114 CSR_Darwin32_Altivec_SaveList :
115 CSR_Darwin32_SaveList);
112 return TM.isPPC64()
113 ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_SaveList
114 : CSR_Darwin64_SaveList)
115 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_SaveList
116 : CSR_Darwin32_SaveList);
116117
117118 // On PPC64, we might need to save r2 (but only if it is not reserved).
118119 bool SaveR2 = MF->getRegInfo().isAllocatable(PPC::X2);
119120
120 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
121 (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList :
122 CSR_SVR464_Altivec_SaveList) :
123 (SaveR2 ? CSR_SVR464_R2_SaveList :
124 CSR_SVR464_SaveList)) :
125 (Subtarget.hasAltivec() ?
126 CSR_SVR432_Altivec_SaveList :
127 CSR_SVR432_SaveList);
121 return TM.isPPC64()
122 ? (Subtarget.hasAltivec()
123 ? (SaveR2 ? CSR_SVR464_R2_Altivec_SaveList
124 : CSR_SVR464_Altivec_SaveList)
125 : (SaveR2 ? CSR_SVR464_R2_SaveList : CSR_SVR464_SaveList))
126 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_SaveList
127 : CSR_SVR432_SaveList);
128128 }
129129
130130 const uint32_t *
131131 PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
132132 CallingConv::ID CC) const {
133 const PPCSubtarget &Subtarget = MF.getSubtarget();
133134 if (CC == CallingConv::AnyReg) {
134135 if (Subtarget.hasVSX())
135136 return CSR_64_AllRegs_VSX_RegMask;
139140 }
140141
141142 if (Subtarget.isDarwinABI())
142 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
143 CSR_Darwin64_Altivec_RegMask :
144 CSR_Darwin64_RegMask) :
145 (Subtarget.hasAltivec() ?
146 CSR_Darwin32_Altivec_RegMask :
147 CSR_Darwin32_RegMask);
148
149 return Subtarget.isPPC64() ? (Subtarget.hasAltivec() ?
150 CSR_SVR464_Altivec_RegMask :
151 CSR_SVR464_RegMask) :
152 (Subtarget.hasAltivec() ?
153 CSR_SVR432_Altivec_RegMask :
154 CSR_SVR432_RegMask);
143 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_Darwin64_Altivec_RegMask
144 : CSR_Darwin64_RegMask)
145 : (Subtarget.hasAltivec() ? CSR_Darwin32_Altivec_RegMask
146 : CSR_Darwin32_RegMask);
147
148 return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask
149 : CSR_SVR464_RegMask)
150 : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask
151 : CSR_SVR432_RegMask);
155152 }
156153
157154 const uint32_t*
166163
167164 BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
168165 BitVector Reserved(getNumRegs());
166 const PPCSubtarget &Subtarget = MF.getSubtarget();
169167 const PPCFrameLowering *PPCFI =
170168 static_cast(Subtarget.getFrameLowering());
171169
204202 }
205203
206204 // On PPC64, r13 is the thread pointer. Never allocate this register.
207 if (Subtarget.isPPC64()) {
205 if (TM.isPPC64()) {
208206 Reserved.set(PPC::R13);
209207
210208 Reserved.set(PPC::X1);
235233 Reserved.set(PPC::R31);
236234
237235 if (hasBasePointer(MF)) {
238 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
239 MF.getTarget().getRelocationModel() == Reloc::PIC_)
236 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
237 TM.getRelocationModel() == Reloc::PIC_)
240238 Reserved.set(PPC::R29);
241239 else
242240 Reserved.set(PPC::R30);
243241 }
244242
245 if (Subtarget.isSVR4ABI() && !Subtarget.isPPC64() &&
246 MF.getTarget().getRelocationModel() == Reloc::PIC_)
243 if (Subtarget.isSVR4ABI() && !TM.isPPC64() &&
244 TM.getRelocationModel() == Reloc::PIC_)
247245 Reserved.set(PPC::R30);
248246
249247 // Reserve Altivec registers when Altivec is unavailable.
257255
258256 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
259257 MachineFunction &MF) const {
258 const PPCSubtarget &Subtarget = MF.getSubtarget();
260259 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
261260 const unsigned DefaultSafety = 1;
262261
291290 const TargetRegisterClass *
292291 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
293292 const MachineFunction &MF) const {
293 const PPCSubtarget &Subtarget = MF.getSubtarget();
294294 if (Subtarget.hasVSX()) {
295295 // With VSX, we can inflate various sub-register classes to the full VSX
296296 // register set.
324324 MachineFunction &MF = *MBB.getParent();
325325 // Get the frame info.
326326 MachineFrameInfo *MFI = MF.getFrameInfo();
327 const PPCSubtarget &Subtarget = MF.getSubtarget();
327328 // Get the instruction info.
328329 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
329330 // Determine whether 64-bit pointers are used.
330 bool LP64 = Subtarget.isPPC64();
331 bool LP64 = TM.isPPC64();
331332 DebugLoc dl = MI.getDebugLoc();
332333
333334 // Get the maximum call stack size.
441442 // Get the instruction's basic block.
442443 MachineBasicBlock &MBB = *MI.getParent();
443444 MachineFunction &MF = *MBB.getParent();
445 const PPCSubtarget &Subtarget = MF.getSubtarget();
444446 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
445447 DebugLoc dl = MI.getDebugLoc();
446448
447 bool LP64 = Subtarget.isPPC64();
449 bool LP64 = TM.isPPC64();
448450 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
449451 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
450452
485487 // Get the instruction's basic block.
486488 MachineBasicBlock &MBB = *MI.getParent();
487489 MachineFunction &MF = *MBB.getParent();
490 const PPCSubtarget &Subtarget = MF.getSubtarget();
488491 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
489492 DebugLoc dl = MI.getDebugLoc();
490493
491 bool LP64 = Subtarget.isPPC64();
494 bool LP64 = TM.isPPC64();
492495 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
493496 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
494497
558561 // Get the instruction's basic block.
559562 MachineBasicBlock &MBB = *MI.getParent();
560563 MachineFunction &MF = *MBB.getParent();
564 const PPCSubtarget &Subtarget = MF.getSubtarget();
561565 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
562566 DebugLoc dl = MI.getDebugLoc();
563567
564 bool LP64 = Subtarget.isPPC64();
568 bool LP64 = TM.isPPC64();
565569 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
566570 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
567571
601605 // Get the instruction's basic block.
602606 MachineBasicBlock &MBB = *MI.getParent();
603607 MachineFunction &MF = *MBB.getParent();
608 const PPCSubtarget &Subtarget = MF.getSubtarget();
604609 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
605610 DebugLoc dl = MI.getDebugLoc();
606611
607 bool LP64 = Subtarget.isPPC64();
612 bool LP64 = TM.isPPC64();
608613 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
609614 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
610615
648653 // Get the instruction's basic block.
649654 MachineBasicBlock &MBB = *MI.getParent();
650655 MachineFunction &MF = *MBB.getParent();
656 const PPCSubtarget &Subtarget = MF.getSubtarget();
651657 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
652658 DebugLoc dl = MI.getDebugLoc();
653659
673679 // Get the instruction's basic block.
674680 MachineBasicBlock &MBB = *MI.getParent();
675681 MachineFunction &MF = *MBB.getParent();
682 const PPCSubtarget &Subtarget = MF.getSubtarget();
676683 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
677684 DebugLoc dl = MI.getDebugLoc();
678685
695702 bool
696703 PPCRegisterInfo::hasReservedSpillSlot(const MachineFunction &MF,
697704 unsigned Reg, int &FrameIdx) const {
698
705 const PPCSubtarget &Subtarget = MF.getSubtarget();
699706 // For the nonvolatile condition registers (CR2, CR3, CR4) in an SVR4
700707 // ABI, return true to prevent allocating an additional frame slot.
701708 // For 64-bit, the CR save area is at SP+8; the value of FrameIdx = 0
702709 // is arbitrary and will be subsequently ignored. For 32-bit, we have
703710 // previously created the stack slot if needed, so return its FrameIdx.
704711 if (Subtarget.isSVR4ABI() && PPC::CR2 <= Reg && Reg <= PPC::CR4) {
705 if (Subtarget.isPPC64())
712 if (TM.isPPC64())
706713 FrameIdx = 0;
707714 else {
708715 const PPCFunctionInfo *FI = MF.getInfo();
755762 MachineBasicBlock &MBB = *MI.getParent();
756763 // Get the basic block's function.
757764 MachineFunction &MF = *MBB.getParent();
765 const PPCSubtarget &Subtarget = MF.getSubtarget();
758766 // Get the instruction info.
759767 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
760768 // Get the frame info.
845853 // The offset doesn't fit into a single register, scavenge one to build the
846854 // offset in.
847855
848 bool is64Bit = Subtarget.isPPC64();
856 bool is64Bit = TM.isPPC64();
849857 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
850858 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
851859 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
883891 }
884892
885893 unsigned PPCRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
894 const PPCSubtarget &Subtarget = MF.getSubtarget();
886895 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
887896
888 if (!Subtarget.isPPC64())
897 if (!TM.isPPC64())
889898 return TFI->hasFP(MF) ? PPC::R31 : PPC::R1;
890899 else
891900 return TFI->hasFP(MF) ? PPC::X31 : PPC::X1;
892901 }
893902
894903 unsigned PPCRegisterInfo::getBaseRegister(const MachineFunction &MF) const {
904 const PPCSubtarget &Subtarget = MF.getSubtarget();
895905 if (!hasBasePointer(MF))
896906 return getFrameRegister(MF);
897907
898 if (Subtarget.isPPC64())
908 if (TM.isPPC64())
899909 return PPC::X30;
900910
901911 if (Subtarget.isSVR4ABI() &&
902 MF.getTarget().getRelocationModel() == Reloc::PIC_)
912 TM.getRelocationModel() == Reloc::PIC_)
903913 return PPC::R29;
904914
905915 return PPC::R30;
925935 }
926936
927937 bool PPCRegisterInfo::needsStackRealignment(const MachineFunction &MF) const {
938 const PPCSubtarget &Subtarget = MF.getSubtarget();
928939 const MachineFrameInfo *MFI = MF.getFrameInfo();
929940 const Function *F = MF.getFunction();
930941 unsigned StackAlign = Subtarget.getFrameLowering()->getStackAlignment();
962973
963974 MachineBasicBlock &MBB = *MI->getParent();
964975 MachineFunction &MF = *MBB.getParent();
965
976 const PPCSubtarget &Subtarget = MF.getSubtarget();
966977 const PPCFrameLowering *PPCFI =
967978 static_cast(Subtarget.getFrameLowering());
968979 unsigned StackEst =
9901001 materializeFrameBaseRegister(MachineBasicBlock *MBB,
9911002 unsigned BaseReg, int FrameIdx,
9921003 int64_t Offset) const {
993 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
1004 unsigned ADDriOpc = TM.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
9941005
9951006 MachineBasicBlock::iterator Ins = MBB->begin();
9961007 DebugLoc DL; // Defaults to "unknown"
9981009 DL = Ins->getDebugLoc();
9991010
10001011 const MachineFunction &MF = *MBB->getParent();
1012 const PPCSubtarget &Subtarget = MF.getSubtarget();
10011013 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
10021014 const MCInstrDesc &MCID = TII.get(ADDriOpc);
10031015 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
10231035
10241036 MachineBasicBlock &MBB = *MI.getParent();
10251037 MachineFunction &MF = *MBB.getParent();
1038 const PPCSubtarget &Subtarget = MF.getSubtarget();
10261039 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
10271040 const MCInstrDesc &MCID = MI.getDesc();
10281041 MachineRegisterInfo &MRI = MF.getRegInfo();
2727
2828 class PPCRegisterInfo : public PPCGenRegisterInfo {
2929 DenseMap ImmToIdxMap;
30 const PPCSubtarget &Subtarget;
30 const PPCTargetMachine &TM;
3131 public:
32 PPCRegisterInfo(const PPCSubtarget &SubTarget);
32 PPCRegisterInfo(const PPCTargetMachine &TM);
3333
3434 /// getPointerRegClass - Return the register class to use to hold pointers.
3535 /// This is used for addressing modes.