llvm.org GIT mirror llvm / e4345c9
Revert "- Implement asm parsing support for LDRT, LDRBT, STRT, STRBT and" This revision introduced a dependency cycle, as nlewycky mentioned by email. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128597 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Beaumont-Gay 9 years ago
8 changed file(s) with 68 addition(s) and 321 deletion(s). Raw diff Collapse all Expand all
199199 }
200200
201201 namespace ARMII {
202
203 /// ARM Addressing Modes
204 enum AddrMode {
205 AddrModeNone = 0,
206 AddrMode1 = 1,
207 AddrMode2 = 2,
208 AddrMode3 = 3,
209 AddrMode4 = 4,
210 AddrMode5 = 5,
211 AddrMode6 = 6,
212 AddrModeT1_1 = 7,
213 AddrModeT1_2 = 8,
214 AddrModeT1_4 = 9,
215 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
216 AddrModeT2_i12 = 11,
217 AddrModeT2_i8 = 12,
218 AddrModeT2_so = 13,
219 AddrModeT2_pc = 14, // +/- i12 for pc relative data
220 AddrModeT2_i8s4 = 15, // i8 * 4
221 AddrMode_i12 = 16
222 };
223
224 inline static const char *AddrModeToString(AddrMode addrmode) {
225 switch (addrmode) {
226 default: llvm_unreachable("Unknown memory operation");
227 case AddrModeNone: return "AddrModeNone";
228 case AddrMode1: return "AddrMode1";
229 case AddrMode2: return "AddrMode2";
230 case AddrMode3: return "AddrMode3";
231 case AddrMode4: return "AddrMode4";
232 case AddrMode5: return "AddrMode5";
233 case AddrMode6: return "AddrMode6";
234 case AddrModeT1_1: return "AddrModeT1_1";
235 case AddrModeT1_2: return "AddrModeT1_2";
236 case AddrModeT1_4: return "AddrModeT1_4";
237 case AddrModeT1_s: return "AddrModeT1_s";
238 case AddrModeT2_i12: return "AddrModeT2_i12";
239 case AddrModeT2_i8: return "AddrModeT2_i8";
240 case AddrModeT2_so: return "AddrModeT2_so";
241 case AddrModeT2_pc: return "AddrModeT2_pc";
242 case AddrModeT2_i8s4: return "AddrModeT2_i8s4";
243 case AddrMode_i12: return "AddrMode_i12";
244 }
245 }
246
247202 /// Target Operand Flag enum.
248203 enum TOF {
249204 //===------------------------------------------------------------------===//
3333
3434 //===------------------------------------------------------------------===//
3535 // This four-bit field describes the addressing mode used.
36 AddrModeMask = 0x1f, // The AddrMode enums are declared in ARMBaseInfo.h
36
37 AddrModeMask = 0x1f,
38 AddrModeNone = 0,
39 AddrMode1 = 1,
40 AddrMode2 = 2,
41 AddrMode3 = 3,
42 AddrMode4 = 4,
43 AddrMode5 = 5,
44 AddrMode6 = 6,
45 AddrModeT1_1 = 7,
46 AddrModeT1_2 = 8,
47 AddrModeT1_4 = 9,
48 AddrModeT1_s = 10, // i8 * 4 for pc and sp relative data
49 AddrModeT2_i12 = 11,
50 AddrModeT2_i8 = 12,
51 AddrModeT2_so = 13,
52 AddrModeT2_pc = 14, // +/- i12 for pc relative data
53 AddrModeT2_i8s4 = 15, // i8 * 4
54 AddrMode_i12 = 16,
3755
3856 // Size* - Flags to keep track of the size of an instruction.
3957 SizeShift = 5,
514514 : AI2ldstidx<0, isByte, isPre, oops, iops, im, f, itin, opc, asm, cstr,
515515 pattern> {
516516 // AM2 store w/ two operands: (GPR, am2offset)
517 // {17-14} Rn
518517 // {13} 1 == Rm, 0 == imm12
519518 // {12} isAdd
520519 // {11-0} imm12/Rm
521 bits<18> addr;
522 let Inst{25} = addr{13};
523 let Inst{23} = addr{12};
524 let Inst{19-16} = addr{17-14};
525 let Inst{11-0} = addr{11-0};
520 bits<14> offset;
521 bits<4> Rn;
522 let Inst{25} = offset{13};
523 let Inst{23} = offset{12};
524 let Inst{19-16} = Rn;
525 let Inst{11-0} = offset{11-0};
526526 }
527527
528528 // addrmode3 instructions
497497 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
498498 }
499499
500 def MemMode2AsmOperand : AsmOperandClass {
501 let Name = "MemMode2";
502 let SuperClasses = [];
503 let ParserMethod = "tryParseMemMode2Operand";
504 }
505
506500 // addrmode2 := reg +/- imm12
507501 // := reg +/- reg shop imm
508502 //
510504 ComplexPattern {
511505 let EncoderMethod = "getAddrMode2OpValue";
512506 let PrintMethod = "printAddrMode2Operand";
513 let ParserMatchClass = MemMode2AsmOperand;
514507 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
515508 }
516509
16621655 let Inst{23} = addr{12};
16631656 let Inst{19-16} = addr{17-14};
16641657 let Inst{11-0} = addr{11-0};
1665 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
16661658 }
16671659 def _POST : AI2ldstidx<1, isByte, 0, (outs GPR:$Rt, GPR:$Rn_wb),
16681660 (ins GPR:$Rn, am2offset:$offset),
17211713
17221714 // LDRT, LDRBT, LDRSBT, LDRHT, LDRSHT are for disassembly only.
17231715 let mayLoad = 1, neverHasSideEffects = 1 in {
1724 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$Rt, GPR:$base_wb),
1725 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_ru,
1726 "ldrt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1727 // {17-14} Rn
1728 // {13} 1 == Rm, 0 == imm12
1729 // {12} isAdd
1730 // {11-0} imm12/Rm
1731 bits<18> addr;
1732 let Inst{25} = addr{13};
1733 let Inst{23} = addr{12};
1716 def LDRT : AI2ldstidx<1, 0, 0, (outs GPR:$dst, GPR:$base_wb),
1717 (ins GPR:$base, am2offset:$offset), IndexModePost,
1718 LdFrm, IIC_iLoad_ru,
1719 "ldrt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
17341720 let Inst{21} = 1; // overwrite
1735 let Inst{19-16} = addr{17-14};
1736 let Inst{11-0} = addr{11-0};
1737 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
1738 }
1739 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$Rt, GPR:$base_wb),
1740 (ins addrmode2:$addr), IndexModePost, LdFrm, IIC_iLoad_bh_ru,
1741 "ldrbt", "\t$Rt, $addr", "$addr.base = $base_wb", []> {
1742 // {17-14} Rn
1743 // {13} 1 == Rm, 0 == imm12
1744 // {12} isAdd
1745 // {11-0} imm12/Rm
1746 bits<18> addr;
1747 let Inst{25} = addr{13};
1748 let Inst{23} = addr{12};
1721 }
1722 def LDRBT : AI2ldstidx<1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
1723 (ins GPR:$base, am2offset:$offset), IndexModePost,
1724 LdFrm, IIC_iLoad_bh_ru,
1725 "ldrbt", "\t$dst, [$base], $offset", "$base = $base_wb", []> {
17491726 let Inst{21} = 1; // overwrite
1750 let Inst{19-16} = addr{17-14};
1751 let Inst{11-0} = addr{11-0};
1752 let AsmMatchConverter = "CvtLdWriteBackRegAddrMode2";
17531727 }
17541728 def LDRSBT : AI3ldstidx<0b1101, 1, 1, 0, (outs GPR:$dst, GPR:$base_wb),
17551729 (ins GPR:$base, am3offset:$offset), IndexModePost,
18431817
18441818 // STRT, STRBT, and STRHT are for disassembly only.
18451819
1846 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1820 def STRT : AI2stridx<0, 0, (outs GPR:$Rn_wb),
1821 (ins GPR:$Rt, GPR:$Rn,am2offset:$offset),
18471822 IndexModePost, StFrm, IIC_iStore_ru,
1848 "strt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1823 "strt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
18491824 [/* For disassembly only; pattern left blank */]> {
18501825 let Inst{21} = 1; // overwrite
1851 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
1852 }
1853
1854 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb), (ins GPR:$Rt, addrmode2:$addr),
1826 }
1827
1828 def STRBT : AI2stridx<1, 0, (outs GPR:$Rn_wb),
1829 (ins GPR:$Rt, GPR:$Rn, am2offset:$offset),
18551830 IndexModePost, StFrm, IIC_iStore_bh_ru,
1856 "strbt", "\t$Rt, $addr", "$addr.base = $Rn_wb",
1831 "strbt", "\t$Rt, [$Rn], $offset", "$Rn = $Rn_wb",
18571832 [/* For disassembly only; pattern left blank */]> {
18581833 let Inst{21} = 1; // overwrite
1859 let AsmMatchConverter = "CvtStWriteBackRegAddrMode2";
18601834 }
18611835
18621836 def STRHT: AI3sthpo<(outs GPR:$base_wb),
34163390 let Inst{23-20} = opc1;
34173391 }
34183392
3419 class ACI
3420 IndexMode im = IndexModeNone>
3421 : I
3393 class ACI
3394 : I
34223395 opc, asm, "", [/* For disassembly only; pattern left blank */]> {
34233396 let Inst{27-25} = 0b110;
34243397 }
34373410
34383411 def _PRE : ACI<(outs),
34393412 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3440 opc, "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3413 opc, "\tp$cop, cr$CRd, $addr!"> {
34413414 let Inst{31-28} = op31_28;
34423415 let Inst{24} = 1; // P = 1
34433416 let Inst{21} = 1; // W = 1
34783451
34793452 def L_PRE : ACI<(outs),
34803453 (ins nohash_imm:$cop, nohash_imm:$CRd, addrmode2:$addr),
3481 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!", IndexModePre> {
3454 !strconcat(opc, "l"), "\tp$cop, cr$CRd, $addr!"> {
34823455 let Inst{31-28} = op31_28;
34833456 let Inst{24} = 1; // P = 1
34843457 let Inst{21} = 1; // W = 1
4747 bool TryParseRegisterWithWriteBack(SmallVectorImpl &);
4848 bool TryParseShiftRegister(SmallVectorImpl &);
4949 bool ParseRegisterList(SmallVectorImpl &);
50 bool ParseMemory(SmallVectorImpl &,
51 ARMII::AddrMode AddrMode);
50 bool ParseMemory(SmallVectorImpl &);
5251 bool ParseOperand(SmallVectorImpl &, StringRef Mnemonic);
5352 bool ParsePrefix(ARMMCExpr::VariantKind &RefKind);
5453 const MCExpr *ApplyPrefixToExpr(const MCExpr *E,
9594 SmallVectorImpl&);
9695 OperandMatchResultTy tryParseMSRMaskOperand(
9796 SmallVectorImpl&);
98 OperandMatchResultTy tryParseMemMode2Operand(
99 SmallVectorImpl&);
100
101 // Asm Match Converter Methods
102 bool CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
103 const SmallVectorImpl &);
104 bool CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
105 const SmallVectorImpl &);
10697
10798 public:
10899 ARMAsmParser(const Target &T, MCAsmParser &_Parser, TargetMachine &_TM)
180171
181172 /// Combined record for all forms of ARM address expressions.
182173 struct {
183 ARMII::AddrMode AddrMode;
184174 unsigned BaseRegNum;
185175 union {
186176 unsigned RegNum; ///< Offset register num, when OffsetIsReg.
302292
303293 /// @name Memory Operand Accessors
304294 /// @{
305 ARMII::AddrMode getMemAddrMode() const {
306 return Mem.AddrMode;
307 }
295
308296 unsigned getMemBaseRegNum() const {
309297 return Mem.BaseRegNum;
310298 }
349337 bool isMemBarrierOpt() const { return Kind == MemBarrierOpt; }
350338 bool isMemory() const { return Kind == Memory; }
351339 bool isShifter() const { return Kind == Shifter; }
352 bool isMemMode2() const {
353 if (getMemAddrMode() != ARMII::AddrMode2)
354 return false;
355
356 if (getMemOffsetIsReg())
357 return true;
358
359 if (getMemNegative() &&
360 !(getMemPostindexed() || getMemPreindexed()))
361 return false;
362
363 const MCConstantExpr *CE = dyn_cast(getMemOffset());
364 if (!CE) return false;
365 int64_t Value = CE->getValue();
366
367 // The offset must be in the range 0-4095 (imm12).
368 if (Value > 4095 || Value < -4095)
369 return false;
370
371 return true;
372 }
373340 bool isMemMode5() const {
374341 if (!isMemory() || getMemOffsetIsReg() || getMemWriteback() ||
375342 getMemNegative())
495462 (void)CE;
496463 assert((CE || CE->getValue() == 0) &&
497464 "No offset operand support in mode 7");
498 }
499
500 void addMemMode2Operands(MCInst &Inst, unsigned N) const {
501 assert(isMemMode2() && "Invalid mode or number of operands!");
502 Inst.addOperand(MCOperand::CreateReg(getMemBaseRegNum()));
503
504 if (getMemOffsetIsReg()) {
505 Inst.addOperand(MCOperand::CreateReg(getMemOffsetRegNum()));
506
507 ARM_AM::AddrOpc AMOpc = getMemNegative() ? ARM_AM::sub : ARM_AM::add;
508 ARM_AM::ShiftOpc ShOpc = ARM_AM::no_shift;
509 int64_t ShiftAmount = 0;
510
511 if (getMemOffsetRegShifted()) {
512 ShOpc = getMemShiftType();
513 const MCConstantExpr *CE =
514 dyn_cast(getMemShiftAmount());
515 ShiftAmount = CE->getValue();
516 }
517
518 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(AMOpc, ShiftAmount,
519 ShOpc)));
520 return;
521 }
522
523 // Create a operand placeholder to always yield the same number of operands.
524 Inst.addOperand(MCOperand::CreateReg(0));
525
526 // FIXME: #-0 is encoded differently than #0. Does the parser preserve
527 // the difference?
528 const MCConstantExpr *CE = dyn_cast(getMemOffset());
529 assert(CE && "Non-constant mode 2 offset operand!");
530 int64_t Offset = CE->getValue();
531
532 if (Offset >= 0)
533 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::add,
534 Offset, ARM_AM::no_shift)));
535 else
536 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM2Opc(ARM_AM::sub,
537 -Offset, ARM_AM::no_shift)));
538465 }
539466
540467 void addMemMode5Operands(MCInst &Inst, unsigned N) const {
671598 return Op;
672599 }
673600
674 static ARMOperand *CreateMem(ARMII::AddrMode AddrMode, unsigned BaseRegNum,
675 bool OffsetIsReg, const MCExpr *Offset,
676 int OffsetRegNum, bool OffsetRegShifted,
601 static ARMOperand *CreateMem(unsigned BaseRegNum, bool OffsetIsReg,
602 const MCExpr *Offset, int OffsetRegNum,
603 bool OffsetRegShifted,
677604 enum ARM_AM::ShiftOpc ShiftType,
678605 const MCExpr *ShiftAmount, bool Preindexed,
679606 bool Postindexed, bool Negative, bool Writeback,
690617 "Cannot have expression offset and register offset!");
691618
692619 ARMOperand *Op = new ARMOperand(Memory);
693 Op->Mem.AddrMode = AddrMode;
694620 Op->Mem.BaseRegNum = BaseRegNum;
695621 Op->Mem.OffsetIsReg = OffsetIsReg;
696622 if (OffsetIsReg)
762688 break;
763689 case Memory:
764690 OS << "
765 << "am:" << ARMII::AddrModeToString(getMemAddrMode())
766 << " base:" << getMemBaseRegNum();
691 << "base:" << getMemBaseRegNum();
767692 if (getMemOffsetIsReg()) {
768693 OS << " offset:
769694 if (getMemOffsetRegShifted()) {
12061131 return MatchOperand_Success;
12071132 }
12081133
1209 /// tryParseMemMode2Operand - Try to parse memory addressing mode 2 operand.
1210 ARMAsmParser::OperandMatchResultTy ARMAsmParser::
1211 tryParseMemMode2Operand(SmallVectorImpl &Operands) {
1212 SMLoc S = Parser.getTok().getLoc();
1213 const AsmToken &Tok = Parser.getTok();
1214 assert(Tok.is(AsmToken::LBrac) && "Token is not a \"[\"");
1215
1216 if (ParseMemory(Operands, ARMII::AddrMode2))
1217 return MatchOperand_NoMatch;
1218
1219 return MatchOperand_Success;
1220 }
1221
1222 /// CvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1223 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1224 /// when they refer multiple MIOperands inside a single one.
1225 bool ARMAsmParser::
1226 CvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1227 const SmallVectorImpl &Operands) {
1228 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1229
1230 // Create a writeback register dummy placeholder.
1231 Inst.addOperand(MCOperand::CreateImm(0));
1232
1233 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1234 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1235 return true;
1236 }
1237
1238 /// CvtStWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
1239 /// Needed here because the Asm Gen Matcher can't handle properly tied operands
1240 /// when they refer multiple MIOperands inside a single one.
1241 bool ARMAsmParser::
1242 CvtStWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
1243 const SmallVectorImpl &Operands) {
1244 // Create a writeback register dummy placeholder.
1245 Inst.addOperand(MCOperand::CreateImm(0));
1246 ((ARMOperand*)Operands[2])->addRegOperands(Inst, 1);
1247 ((ARMOperand*)Operands[3])->addMemMode2Operands(Inst, 3);
1248 ((ARMOperand*)Operands[1])->addCondCodeOperands(Inst, 2);
1249 return true;
1250 }
1251
12521134 /// Parse an ARM memory expression, return false if successful else return true
12531135 /// or an error. The first token must be a '[' when called.
12541136 ///
12551137 /// TODO Only preindexing and postindexing addressing are started, unindexed
12561138 /// with option, etc are still to do.
12571139 bool ARMAsmParser::
1258 ParseMemory(SmallVectorImpl &Operands,
1259 ARMII::AddrMode AddrMode = ARMII::AddrModeNone) {
1140 ParseMemory(SmallVectorImpl &Operands) {
12601141 SMLoc S, E;
12611142 assert(Parser.getTok().is(AsmToken::LBrac) &&
12621143 "Token is not a Left Bracket");
13491230 Offset = MCConstantExpr::Create(0, getContext());
13501231 }
13511232
1352 Operands.push_back(ARMOperand::CreateMem(AddrMode, BaseRegNum, OffsetIsReg,
1353 Offset, OffsetRegNum, OffsetRegShifted,
1354 ShiftType, ShiftAmount, Preindexed,
1355 Postindexed, Negative, Writeback, S, E));
1233 Operands.push_back(ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset,
1234 OffsetRegNum, OffsetRegShifted,
1235 ShiftType, ShiftAmount, Preindexed,
1236 Postindexed, Negative, Writeback,
1237 S, E));
13561238 if (WBOp)
13571239 Operands.push_back(WBOp);
13581240
1313 #define DEBUG_TYPE "asm-printer"
1414 #include "ARMBaseInfo.h"
1515 #include "ARMInstPrinter.h"
16 #include "ARMInstrInfo.h"
1716 #include "ARMAddressingModes.h"
1817 #include "llvm/MC/MCInst.h"
1918 #include "llvm/MC/MCAsmInfo.h"
181180 }
182181 }
183182
184 void ARMInstPrinter::printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
185 raw_ostream &O) {
183
184 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
185 raw_ostream &O) {
186186 const MCOperand &MO1 = MI->getOperand(Op);
187187 const MCOperand &MO2 = MI->getOperand(Op+1);
188188 const MCOperand &MO3 = MI->getOperand(Op+2);
189
190 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
191 printOperand(MI, Op, O);
192 return;
193 }
189194
190195 O << "[" << getRegisterName(MO1.getReg());
191196
207212 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
208213 << " #" << ShImm;
209214 O << "]";
210 }
211
212 void ARMInstPrinter::printAM2PostIndexOp(const MCInst *MI, unsigned Op,
213 raw_ostream &O) {
214 const MCOperand &MO1 = MI->getOperand(Op);
215 const MCOperand &MO2 = MI->getOperand(Op+1);
216 const MCOperand &MO3 = MI->getOperand(Op+2);
217
218 O << "[" << getRegisterName(MO1.getReg()) << "], ";
219
220 if (!MO2.getReg()) {
221 unsigned ImmOffs = ARM_AM::getAM2Offset(MO3.getImm());
222 O << '#'
223 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
224 << ImmOffs;
225 return;
226 }
227
228 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
229 << getRegisterName(MO2.getReg());
230
231 if (unsigned ShImm = ARM_AM::getAM2Offset(MO3.getImm()))
232 O << ", "
233 << ARM_AM::getShiftOpcStr(ARM_AM::getAM2ShiftOpc(MO3.getImm()))
234 << " #" << ShImm;
235 }
236
237 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
238 raw_ostream &O) {
239 const MCOperand &MO1 = MI->getOperand(Op);
240
241 if (!MO1.isReg()) { // FIXME: This is for CP entries, but isn't right.
242 printOperand(MI, Op, O);
243 return;
244 }
245
246 unsigned Opcode = MI->getOpcode();
247 const TargetInstrDesc &Desc = TM.getInstrInfo()->get(Opcode);
248 uint64_t TSFlags = Desc.TSFlags;
249 unsigned IdxMode = (TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift;
250
251 if (IdxMode == ARMII::IndexModePost) {
252 printAM2PostIndexOp(MI, Op, O);
253 return;
254 }
255 printAM2PreOrOffsetIndexOp(MI, Op, O);
256215 }
257216
258217 void ARMInstPrinter::printAddrMode2OffsetOperand(const MCInst *MI,
2121 class TargetMachine;
2222
2323 class ARMInstPrinter : public MCInstPrinter {
24 private:
25 TargetMachine &TM;
2624 public:
27 ARMInstPrinter(TargetMachine &_TM, const MCAsmInfo &MAI)
28 : MCInstPrinter(MAI), TM(_TM) {}
25 ARMInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
26 : MCInstPrinter(MAI) {}
2927
3028 virtual void printInst(const MCInst *MI, raw_ostream &O);
3129 virtual StringRef getOpcodeName(unsigned Opcode) const;
4341 void printSOImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
4442
4543 void printSORegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46
4744 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
48 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
49 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
50 raw_ostream &O);
5145 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
5246 raw_ostream &O);
5347 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
+0
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test/MC/ARM/arm_addrmode2.s less more
None @ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s | FileCheck %s
1
2 @ Post-indexed
3 @ CHECK: ldrt r1, [r0], r2 @ encoding: [0x02,0x10,0xb0,0xe6]
4 @ CHECK: ldrt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xb0,0xe6]
5 @ CHECK: ldrt r1, [r0], #4 @ encoding: [0x04,0x10,0xb0,0xe4]
6 @ CHECK: ldrbt r1, [r0], r2 @ encoding: [0x02,0x10,0xf0,0xe6]
7 @ CHECK: ldrbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xf0,0xe6]
8 @ CHECK: ldrbt r1, [r0], #4 @ encoding: [0x04,0x10,0xf0,0xe4]
9 @ CHECK: strt r1, [r0], r2 @ encoding: [0x02,0x10,0xa0,0xe6]
10 @ CHECK: strt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xa0,0xe6]
11 @ CHECK: strt r1, [r0], #4 @ encoding: [0x04,0x10,0xa0,0xe4]
12 @ CHECK: strbt r1, [r0], r2 @ encoding: [0x02,0x10,0xe0,0xe6]
13 @ CHECK: strbt r1, [r0], r2, lsr #3 @ encoding: [0xa2,0x11,0xe0,0xe6]
14 @ CHECK: strbt r1, [r0], #4 @ encoding: [0x04,0x10,0xe0,0xe4]
15 ldrt r1, [r0], r2
16 ldrt r1, [r0], r2, lsr #3
17 ldrt r1, [r0], #4
18 ldrbt r1, [r0], r2
19 ldrbt r1, [r0], r2, lsr #3
20 ldrbt r1, [r0], #4
21 strt r1, [r0], r2
22 strt r1, [r0], r2, lsr #3
23 strt r1, [r0], #4
24 strbt r1, [r0], r2
25 strbt r1, [r0], r2, lsr #3
26 strbt r1, [r0], #4
27
28 @ Pre-indexed
29 @ CHECK: ldr r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xb0,0xe7]
30 @ CHECK: ldrb r1, [r0, r2, lsr #3]! @ encoding: [0xa2,0x11,0xf0,0xe7]
31 ldr r1, [r0, r2, lsr #3]!
32 ldrb r1, [r0, r2, lsr #3]!
33