llvm.org GIT mirror llvm / e3a9b4c
Fix a bunch more layering of CodeGen headers that are in Target All these headers already depend on CodeGen headers so moving them into CodeGen fixes the layering (since CodeGen depends on Target, not the other way around). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318490 91177308-0d34-0410-b5e6-96231b3b80d8 David Blaikie 1 year, 11 months ago
418 changed file(s) with 6556 addition(s) and 6560 deletion(s). Raw diff Collapse all Expand all
2626 #include "llvm/Analysis/TargetTransformInfoImpl.h"
2727 #include "llvm/CodeGen/ISDOpcodes.h"
2828 #include "llvm/CodeGen/MachineValueType.h"
29 #include "llvm/CodeGen/TargetLowering.h"
30 #include "llvm/CodeGen/TargetSubtargetInfo.h"
2931 #include "llvm/CodeGen/ValueTypes.h"
3032 #include "llvm/IR/BasicBlock.h"
3133 #include "llvm/IR/CallSite.h"
4547 #include "llvm/Support/CommandLine.h"
4648 #include "llvm/Support/ErrorHandling.h"
4749 #include "llvm/Support/MathExtras.h"
48 #include "llvm/Target/TargetLowering.h"
49 #include "llvm/Target/TargetSubtargetInfo.h"
5050 #include
5151 #include
5252 #include
1717 #include "llvm/ADT/SmallVector.h"
1818 #include "llvm/CodeGen/MachineFrameInfo.h"
1919 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/TargetCallingConv.h"
2021 #include "llvm/IR/CallingConv.h"
2122 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Target/TargetCallingConv.h"
2323
2424 namespace llvm {
2525
0 //===-- CostTable.h - Instruction Cost Table handling -----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// \brief Cost tables and simple lookup functions
11 ///
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_CODEGEN_COSTTABLE_H_
15 #define LLVM_CODEGEN_COSTTABLE_H_
16
17 #include "llvm/ADT/ArrayRef.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineValueType.h"
20
21 namespace llvm {
22
23 /// Cost Table Entry
24 struct CostTblEntry {
25 int ISD;
26 MVT::SimpleValueType Type;
27 unsigned Cost;
28 };
29
30 /// Find in cost table, TypeTy must be comparable to CompareTy by ==
31 inline const CostTblEntry *CostTableLookup(ArrayRef Tbl,
32 int ISD, MVT Ty) {
33 auto I = find_if(Tbl, [=](const CostTblEntry &Entry) {
34 return ISD == Entry.ISD && Ty == Entry.Type;
35 });
36 if (I != Tbl.end())
37 return I;
38
39 // Could not find an entry.
40 return nullptr;
41 }
42
43 /// Type Conversion Cost Table
44 struct TypeConversionCostTblEntry {
45 int ISD;
46 MVT::SimpleValueType Dst;
47 MVT::SimpleValueType Src;
48 unsigned Cost;
49 };
50
51 /// Find in type conversion cost table, TypeTy must be comparable to CompareTy
52 /// by ==
53 inline const TypeConversionCostTblEntry *
54 ConvertCostTableLookup(ArrayRef Tbl,
55 int ISD, MVT Dst, MVT Src) {
56 auto I = find_if(Tbl, [=](const TypeConversionCostTblEntry &Entry) {
57 return ISD == Entry.ISD && Src == Entry.Src && Dst == Entry.Dst;
58 });
59 if (I != Tbl.end())
60 return I;
61
62 // Could not find an entry.
63 return nullptr;
64 }
65
66 } // namespace llvm
67
68 #endif /* LLVM_CODEGEN_COSTTABLE_H_ */
1919 #include "llvm/ADT/StringRef.h"
2020 #include "llvm/CodeGen/MachineBasicBlock.h"
2121 #include "llvm/CodeGen/MachineValueType.h"
22 #include "llvm/CodeGen/TargetLowering.h"
2223 #include "llvm/IR/Attributes.h"
2324 #include "llvm/IR/CallSite.h"
2425 #include "llvm/IR/CallingConv.h"
2627 #include "llvm/IR/DerivedTypes.h"
2728 #include "llvm/IR/InstrTypes.h"
2829 #include "llvm/IR/IntrinsicInst.h"
29 #include "llvm/Target/TargetLowering.h"
3030 #include
3131 #include
3232 #include
2222 #include "llvm/ADT/SmallVector.h"
2323 #include "llvm/CodeGen/ISDOpcodes.h"
2424 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/TargetRegisterInfo.h"
2526 #include "llvm/IR/Instructions.h"
2627 #include "llvm/IR/Type.h"
2728 #include "llvm/IR/Value.h"
2829 #include "llvm/Support/KnownBits.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
3030 #include
3131 #include
3232 #include
1717 #include "llvm/ADT/ArrayRef.h"
1818 #include "llvm/CodeGen/CallingConvLower.h"
1919 #include "llvm/CodeGen/MachineValueType.h"
20 #include "llvm/CodeGen/TargetCallingConv.h"
2021 #include "llvm/IR/CallSite.h"
2122 #include "llvm/IR/CallingConv.h"
2223 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Target/TargetCallingConv.h"
2424 #include
2525 #include
2626
2222 #include "llvm/CodeGen/MachineOperand.h"
2323 #include "llvm/CodeGen/MachineRegisterInfo.h"
2424 #include "llvm/CodeGen/TargetInstrInfo.h"
25 #include "llvm/CodeGen/TargetOpcodes.h"
26 #include "llvm/CodeGen/TargetRegisterInfo.h"
2527 #include "llvm/IR/Constants.h"
2628 #include "llvm/Support/Debug.h"
2729 #include "llvm/Support/ErrorHandling.h"
2830 #include "llvm/Support/raw_ostream.h"
29 #include "llvm/Target/TargetOpcodes.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
3131 #include
3232 #include
3333 #include
1919 #include "llvm/ADT/Optional.h"
2020 #include "llvm/ADT/STLExtras.h"
2121 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/TargetOpcodes.h"
2223 #include "llvm/Support/LowLevelTypeImpl.h"
23 #include "llvm/Target/TargetOpcodes.h"
24 #include
2425 #include
25 #include
2626 #include
27 #include
2728 #include
28 #include
2929
3030 namespace llvm {
3131
2727 #include "llvm/CodeGen/MachineBasicBlock.h"
2828 #include "llvm/CodeGen/MachineFunctionPass.h"
2929 #include "llvm/CodeGen/SlotIndexes.h"
30 #include "llvm/CodeGen/TargetRegisterInfo.h"
3031 #include "llvm/MC/LaneBitmask.h"
3132 #include "llvm/Support/CommandLine.h"
3233 #include "llvm/Support/Compiler.h"
3334 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Target/TargetRegisterInfo.h"
3535 #include
3636 #include
3737 #include
3131
3232 #include "llvm/ADT/SparseSet.h"
3333 #include "llvm/CodeGen/MachineBasicBlock.h"
34 #include "llvm/CodeGen/TargetRegisterInfo.h"
3435 #include "llvm/MC/MCRegisterInfo.h"
35 #include "llvm/Target/TargetRegisterInfo.h"
3636 #include
3737 #include
3838
2828 #include "llvm/CodeGen/MachineFunction.h"
2929 #include "llvm/CodeGen/MachineRegisterInfo.h"
3030 #include "llvm/CodeGen/SlotIndexes.h"
31 #include "llvm/Target/TargetSubtargetInfo.h"
31 #include "llvm/CodeGen/TargetSubtargetInfo.h"
3232 #include
3333
3434 namespace llvm {
1515 #define LLVM_CODEGEN_LIVEREGUNITS_H
1616
1717 #include "llvm/ADT/BitVector.h"
18 #include "llvm/CodeGen/TargetRegisterInfo.h"
1819 #include "llvm/MC/LaneBitmask.h"
1920 #include "llvm/MC/MCRegisterInfo.h"
20 #include "llvm/Target/TargetRegisterInfo.h"
2121 #include
2222
2323 namespace llvm {
3535 #include "llvm/ADT/SparseBitVector.h"
3636 #include "llvm/CodeGen/MachineFunctionPass.h"
3737 #include "llvm/CodeGen/MachineInstr.h"
38 #include "llvm/Target/TargetRegisterInfo.h"
38 #include "llvm/CodeGen/TargetRegisterInfo.h"
3939
4040 namespace llvm {
4141
2121 #include "llvm/ADT/iterator_range.h"
2222 #include "llvm/Analysis/AliasAnalysis.h"
2323 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/TargetOpcodes.h"
2425 #include "llvm/IR/DebugLoc.h"
2526 #include "llvm/IR/InlineAsm.h"
2627 #include "llvm/MC/MCInstrDesc.h"
2728 #include "llvm/Support/ArrayRecycler.h"
28 #include "llvm/Target/TargetOpcodes.h"
2929 #include
3030 #include
3131 #include
2626 #include "llvm/CodeGen/MachineFunction.h"
2727 #include "llvm/CodeGen/MachineInstrBundle.h"
2828 #include "llvm/CodeGen/MachineOperand.h"
29 #include "llvm/CodeGen/TargetRegisterInfo.h"
30 #include "llvm/CodeGen/TargetSubtargetInfo.h"
2931 #include "llvm/MC/LaneBitmask.h"
30 #include "llvm/Target/TargetRegisterInfo.h"
31 #include "llvm/Target/TargetSubtargetInfo.h"
3232 #include
3333 #include
3434 #include
1919 #include "llvm/ADT/ArrayRef.h"
2020 #include "llvm/ADT/BitVector.h"
2121 #include "llvm/ADT/SmallVector.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
2223 #include "llvm/MC/MCRegisterInfo.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
2424 #include
2525 #include
2626 #include
1919 #include "llvm/ADT/SparseSet.h"
2020 #include "llvm/CodeGen/MachineBasicBlock.h"
2121 #include "llvm/CodeGen/SlotIndexes.h"
22 #include "llvm/CodeGen/TargetRegisterInfo.h"
2223 #include "llvm/MC/LaneBitmask.h"
23 #include "llvm/Target/TargetRegisterInfo.h"
2424 #include
2525 #include
2626 #include
2020 #include "llvm/CodeGen/ScheduleDAG.h"
2121 #include "llvm/CodeGen/SelectionDAGISel.h"
2222 #include "llvm/CodeGen/TargetInstrInfo.h"
23 #include "llvm/CodeGen/TargetRegisterInfo.h"
2324 #include "llvm/MC/MCInstrItineraries.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
2525
2626 namespace llvm {
2727 class ResourcePriorityQueue;
2121 #include "llvm/ADT/SmallVector.h"
2222 #include "llvm/ADT/iterator.h"
2323 #include "llvm/CodeGen/MachineInstr.h"
24 #include "llvm/CodeGen/TargetLowering.h"
2425 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Target/TargetLowering.h"
2626 #include
2727 #include
2828 #include
2323 #include "llvm/CodeGen/LivePhysRegs.h"
2424 #include "llvm/CodeGen/MachineBasicBlock.h"
2525 #include "llvm/CodeGen/ScheduleDAG.h"
26 #include "llvm/CodeGen/TargetRegisterInfo.h"
2627 #include "llvm/CodeGen/TargetSchedule.h"
2728 #include "llvm/MC/LaneBitmask.h"
28 #include "llvm/Target/TargetRegisterInfo.h"
2929 #include
3030 #include
3131 #include
1616
1717 #include "llvm/CodeGen/MachineFunctionPass.h"
1818 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/CodeGen/TargetSubtargetInfo.h"
1920 #include "llvm/IR/BasicBlock.h"
2021 #include "llvm/Pass.h"
21 #include "llvm/Target/TargetSubtargetInfo.h"
2222 #include
2323
2424 namespace llvm {
2121 #include "llvm/ADT/SmallVector.h"
2222 #include "llvm/CodeGen/RegisterScavenging.h"
2323 #include "llvm/CodeGen/TargetInstrInfo.h"
24 #include "llvm/CodeGen/TargetSubtargetInfo.h"
2425 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Target/TargetSubtargetInfo.h"
2626 #include
2727 #include
2828
0 //===-- llvm/CodeGen/TargetCallingConv.h - Calling Convention ---*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines types for working with calling-convention information.
10 //
11 //===----------------------------------------------------------------------===//
12
13 #ifndef LLVM_CODEGEN_TARGETCALLINGCONV_H
14 #define LLVM_CODEGEN_TARGETCALLINGCONV_H
15
16 #include "llvm/CodeGen/MachineValueType.h"
17 #include "llvm/CodeGen/ValueTypes.h"
18 #include "llvm/Support/MathExtras.h"
19 #include
20 #include
21 #include
22
23 namespace llvm {
24 namespace ISD {
25
26 struct ArgFlagsTy {
27 private:
28 unsigned IsZExt : 1; ///< Zero extended
29 unsigned IsSExt : 1; ///< Sign extended
30 unsigned IsInReg : 1; ///< Passed in register
31 unsigned IsSRet : 1; ///< Hidden struct-ret ptr
32 unsigned IsByVal : 1; ///< Struct passed by value
33 unsigned IsNest : 1; ///< Nested fn static chain
34 unsigned IsReturned : 1; ///< Always returned
35 unsigned IsSplit : 1;
36 unsigned IsInAlloca : 1; ///< Passed with inalloca
37 unsigned IsSplitEnd : 1; ///< Last part of a split
38 unsigned IsSwiftSelf : 1; ///< Swift self parameter
39 unsigned IsSwiftError : 1; ///< Swift error parameter
40 unsigned IsHva : 1; ///< HVA field for
41 unsigned IsHvaStart : 1; ///< HVA structure start
42 unsigned IsSecArgPass : 1; ///< Second argument
43 unsigned ByValAlign : 4; ///< Log 2 of byval alignment
44 unsigned OrigAlign : 5; ///< Log 2 of original alignment
45 unsigned IsInConsecutiveRegsLast : 1;
46 unsigned IsInConsecutiveRegs : 1;
47 unsigned IsCopyElisionCandidate : 1; ///< Argument copy elision candidate
48
49 unsigned ByValSize; ///< Byval struct size
50
51 public:
52 ArgFlagsTy()
53 : IsZExt(0), IsSExt(0), IsInReg(0), IsSRet(0), IsByVal(0), IsNest(0),
54 IsReturned(0), IsSplit(0), IsInAlloca(0), IsSplitEnd(0),
55 IsSwiftSelf(0), IsSwiftError(0), IsHva(0), IsHvaStart(0),
56 IsSecArgPass(0), ByValAlign(0), OrigAlign(0),
57 IsInConsecutiveRegsLast(0), IsInConsecutiveRegs(0),
58 IsCopyElisionCandidate(0), ByValSize(0) {
59 static_assert(sizeof(*this) == 2 * sizeof(unsigned), "flags are too big");
60 }
61
62 bool isZExt() const { return IsZExt; }
63 void setZExt() { IsZExt = 1; }
64
65 bool isSExt() const { return IsSExt; }
66 void setSExt() { IsSExt = 1; }
67
68 bool isInReg() const { return IsInReg; }
69 void setInReg() { IsInReg = 1; }
70
71 bool isSRet() const { return IsSRet; }
72 void setSRet() { IsSRet = 1; }
73
74 bool isByVal() const { return IsByVal; }
75 void setByVal() { IsByVal = 1; }
76
77 bool isInAlloca() const { return IsInAlloca; }
78 void setInAlloca() { IsInAlloca = 1; }
79
80 bool isSwiftSelf() const { return IsSwiftSelf; }
81 void setSwiftSelf() { IsSwiftSelf = 1; }
82
83 bool isSwiftError() const { return IsSwiftError; }
84 void setSwiftError() { IsSwiftError = 1; }
85
86 bool isHva() const { return IsHva; }
87 void setHva() { IsHva = 1; }
88
89 bool isHvaStart() const { return IsHvaStart; }
90 void setHvaStart() { IsHvaStart = 1; }
91
92 bool isSecArgPass() const { return IsSecArgPass; }
93 void setSecArgPass() { IsSecArgPass = 1; }
94
95 bool isNest() const { return IsNest; }
96 void setNest() { IsNest = 1; }
97
98 bool isReturned() const { return IsReturned; }
99 void setReturned() { IsReturned = 1; }
100
101 bool isInConsecutiveRegs() const { return IsInConsecutiveRegs; }
102 void setInConsecutiveRegs() { IsInConsecutiveRegs = 1; }
103
104 bool isInConsecutiveRegsLast() const { return IsInConsecutiveRegsLast; }
105 void setInConsecutiveRegsLast() { IsInConsecutiveRegsLast = 1; }
106
107 bool isSplit() const { return IsSplit; }
108 void setSplit() { IsSplit = 1; }
109
110 bool isSplitEnd() const { return IsSplitEnd; }
111 void setSplitEnd() { IsSplitEnd = 1; }
112
113 bool isCopyElisionCandidate() const { return IsCopyElisionCandidate; }
114 void setCopyElisionCandidate() { IsCopyElisionCandidate = 1; }
115
116 unsigned getByValAlign() const { return (1U << ByValAlign) / 2; }
117 void setByValAlign(unsigned A) {
118 ByValAlign = Log2_32(A) + 1;
119 assert(getByValAlign() == A && "bitfield overflow");
120 }
121
122 unsigned getOrigAlign() const { return (1U << OrigAlign) / 2; }
123 void setOrigAlign(unsigned A) {
124 OrigAlign = Log2_32(A) + 1;
125 assert(getOrigAlign() == A && "bitfield overflow");
126 }
127
128 unsigned getByValSize() const { return ByValSize; }
129 void setByValSize(unsigned S) { ByValSize = S; }
130 };
131
132 /// InputArg - This struct carries flags and type information about a
133 /// single incoming (formal) argument or incoming (from the perspective
134 /// of the caller) return value virtual register.
135 ///
136 struct InputArg {
137 ArgFlagsTy Flags;
138 MVT VT = MVT::Other;
139 EVT ArgVT;
140 bool Used = false;
141
142 /// Index original Function's argument.
143 unsigned OrigArgIndex;
144 /// Sentinel value for implicit machine-level input arguments.
145 static const unsigned NoArgIndex = UINT_MAX;
146
147 /// Offset in bytes of current input value relative to the beginning of
148 /// original argument. E.g. if argument was splitted into four 32 bit
149 /// registers, we got 4 InputArgs with PartOffsets 0, 4, 8 and 12.
150 unsigned PartOffset;
151
152 InputArg() = default;
153 InputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
154 unsigned origIdx, unsigned partOffs)
155 : Flags(flags), Used(used), OrigArgIndex(origIdx), PartOffset(partOffs) {
156 VT = vt.getSimpleVT();
157 ArgVT = argvt;
158 }
159
160 bool isOrigArg() const {
161 return OrigArgIndex != NoArgIndex;
162 }
163
164 unsigned getOrigArgIndex() const {
165 assert(OrigArgIndex != NoArgIndex && "Implicit machine-level argument");
166 return OrigArgIndex;
167 }
168 };
169
170 /// OutputArg - This struct carries flags and a value for a
171 /// single outgoing (actual) argument or outgoing (from the perspective
172 /// of the caller) return value virtual register.
173 ///
174 struct OutputArg {
175 ArgFlagsTy Flags;
176 MVT VT;
177 EVT ArgVT;
178
179 /// IsFixed - Is this a "fixed" value, ie not passed through a vararg "...".
180 bool IsFixed = false;
181
182 /// Index original Function's argument.
183 unsigned OrigArgIndex;
184
185 /// Offset in bytes of current output value relative to the beginning of
186 /// original argument. E.g. if argument was splitted into four 32 bit
187 /// registers, we got 4 OutputArgs with PartOffsets 0, 4, 8 and 12.
188 unsigned PartOffset;
189
190 OutputArg() = default;
191 OutputArg(ArgFlagsTy flags, EVT vt, EVT argvt, bool isfixed,
192 unsigned origIdx, unsigned partOffs)
193 : Flags(flags), IsFixed(isfixed), OrigArgIndex(origIdx),
194 PartOffset(partOffs) {
195 VT = vt.getSimpleVT();
196 ArgVT = argvt;
197 }
198 };
199
200 } // end namespace ISD
201 } // end namespace llvm
202
203 #endif // LLVM_CODEGEN_TARGETCALLINGCONV_H
None //===-- llvm/CodeGen/TargetFrameLowering.h ---------------------------*- C++ -*-===//
0 //===-- llvm/CodeGen/TargetFrameLowering.h ----------------------*- C++ -*-===//
11 //
22 // The LLVM Compiler Infrastructure
33 //
0 //===- llvm/CodeGen/TargetLowering.h - Target Lowering Info -----*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// This file describes how to lower LLVM code to machine code. This has two
11 /// main components:
12 ///
13 /// 1. Which ValueTypes are natively supported by the target.
14 /// 2. Which operations are supported for supported ValueTypes.
15 /// 3. Cost thresholds for alternative implementations of certain operations.
16 ///
17 /// In addition it has a few other components, like information about FP
18 /// immediates.
19 ///
20 //===----------------------------------------------------------------------===//
21
22 #ifndef LLVM_CODEGEN_TARGETLOWERING_H
23 #define LLVM_CODEGEN_TARGETLOWERING_H
24
25 #include "llvm/ADT/APInt.h"
26 #include "llvm/ADT/ArrayRef.h"
27 #include "llvm/ADT/DenseMap.h"
28 #include "llvm/ADT/STLExtras.h"
29 #include "llvm/ADT/SmallVector.h"
30 #include "llvm/ADT/StringRef.h"
31 #include "llvm/CodeGen/DAGCombine.h"
32 #include "llvm/CodeGen/ISDOpcodes.h"
33 #include "llvm/CodeGen/MachineValueType.h"
34 #include "llvm/CodeGen/RuntimeLibcalls.h"
35 #include "llvm/CodeGen/SelectionDAG.h"
36 #include "llvm/CodeGen/SelectionDAGNodes.h"
37 #include "llvm/CodeGen/TargetCallingConv.h"
38 #include "llvm/CodeGen/ValueTypes.h"
39 #include "llvm/IR/Attributes.h"
40 #include "llvm/IR/CallSite.h"
41 #include "llvm/IR/CallingConv.h"
42 #include "llvm/IR/DataLayout.h"
43 #include "llvm/IR/DerivedTypes.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/IRBuilder.h"
46 #include "llvm/IR/InlineAsm.h"
47 #include "llvm/IR/Instruction.h"
48 #include "llvm/IR/Instructions.h"
49 #include "llvm/IR/Type.h"
50 #include "llvm/MC/MCRegisterInfo.h"
51 #include "llvm/Support/AtomicOrdering.h"
52 #include "llvm/Support/Casting.h"
53 #include "llvm/Support/ErrorHandling.h"
54 #include "llvm/Target/TargetMachine.h"
55 #include
56 #include
57 #include
58 #include
59 #include
60 #include
61 #include
62 #include
63 #include
64
65 namespace llvm {
66
67 class BranchProbability;
68 class CCState;
69 class CCValAssign;
70 class Constant;
71 class FastISel;
72 class FunctionLoweringInfo;
73 class GlobalValue;
74 class IntrinsicInst;
75 struct KnownBits;
76 class LLVMContext;
77 class MachineBasicBlock;
78 class MachineFunction;
79 class MachineInstr;
80 class MachineJumpTableInfo;
81 class MachineLoop;
82 class MachineRegisterInfo;
83 class MCContext;
84 class MCExpr;
85 class Module;
86 class TargetRegisterClass;
87 class TargetLibraryInfo;
88 class TargetRegisterInfo;
89 class Value;
90
91 namespace Sched {
92
93 enum Preference {
94 None, // No preference
95 Source, // Follow source order.
96 RegPressure, // Scheduling for lowest register pressure.
97 Hybrid, // Scheduling for both latency and register pressure.
98 ILP, // Scheduling for ILP in low register pressure mode.
99 VLIW // Scheduling for VLIW targets.
100 };
101
102 } // end namespace Sched
103
104 /// This base class for TargetLowering contains the SelectionDAG-independent
105 /// parts that can be used from the rest of CodeGen.
106 class TargetLoweringBase {
107 public:
108 /// This enum indicates whether operations are valid for a target, and if not,
109 /// what action should be used to make them valid.
110 enum LegalizeAction : uint8_t {
111 Legal, // The target natively supports this operation.
112 Promote, // This operation should be executed in a larger type.
113 Expand, // Try to expand this to other ops, otherwise use a libcall.
114 LibCall, // Don't try to expand this to other ops, always use a libcall.
115 Custom // Use the LowerOperation hook to implement custom lowering.
116 };
117
118 /// This enum indicates whether a types are legal for a target, and if not,
119 /// what action should be used to make them valid.
120 enum LegalizeTypeAction : uint8_t {
121 TypeLegal, // The target natively supports this type.
122 TypePromoteInteger, // Replace this integer with a larger one.
123 TypeExpandInteger, // Split this integer into two of half the size.
124 TypeSoftenFloat, // Convert this float to a same size integer type,
125 // if an operation is not supported in target HW.
126 TypeExpandFloat, // Split this float into two of half the size.
127 TypeScalarizeVector, // Replace this one-element vector with its element.
128 TypeSplitVector, // Split this vector into two of half the size.
129 TypeWidenVector, // This vector should be widened into a larger vector.
130 TypePromoteFloat // Replace this float with a larger one.
131 };
132
133 /// LegalizeKind holds the legalization kind that needs to happen to EVT
134 /// in order to type-legalize it.
135 using LegalizeKind = std::pair;
136
137 /// Enum that describes how the target represents true/false values.
138 enum BooleanContent {
139 UndefinedBooleanContent, // Only bit 0 counts, the rest can hold garbage.
140 ZeroOrOneBooleanContent, // All bits zero except for bit 0.
141 ZeroOrNegativeOneBooleanContent // All bits equal to bit 0.
142 };
143
144 /// Enum that describes what type of support for selects the target has.
145 enum SelectSupportKind {
146 ScalarValSelect, // The target supports scalar selects (ex: cmov).
147 ScalarCondVectorVal, // The target supports selects with a scalar condition
148 // and vector values (ex: cmov).
149 VectorMaskSelect // The target supports vector selects with a vector
150 // mask (ex: x86 blends).
151 };
152
153 /// Enum that specifies what an atomic load/AtomicRMWInst is expanded
154 /// to, if at all. Exists because different targets have different levels of
155 /// support for these atomic instructions, and also have different options
156 /// w.r.t. what they should expand to.
157 enum class AtomicExpansionKind {
158 None, // Don't expand the instruction.
159 LLSC, // Expand the instruction into loadlinked/storeconditional; used
160 // by ARM/AArch64.
161 LLOnly, // Expand the (load) instruction into just a load-linked, which has
162 // greater atomic guarantees than a normal load.
163 CmpXChg, // Expand the instruction into cmpxchg; used by at least X86.
164 };
165
166 /// Enum that specifies when a multiplication should be expanded.
167 enum class MulExpansionKind {
168 Always, // Always expand the instruction.
169 OnlyLegalOrCustom, // Only expand when the resulting instructions are legal
170 // or custom.
171 };
172
173 class ArgListEntry {
174 public:
175 Value *Val = nullptr;
176 SDValue Node = SDValue();
177 Type *Ty = nullptr;
178 bool IsSExt : 1;
179 bool IsZExt : 1;
180 bool IsInReg : 1;
181 bool IsSRet : 1;
182 bool IsNest : 1;
183 bool IsByVal : 1;
184 bool IsInAlloca : 1;
185 bool IsReturned : 1;
186 bool IsSwiftSelf : 1;
187 bool IsSwiftError : 1;
188 uint16_t Alignment = 0;
189
190 ArgListEntry()
191 : IsSExt(false), IsZExt(false), IsInReg(false), IsSRet(false),
192 IsNest(false), IsByVal(false), IsInAlloca(false), IsReturned(false),
193 IsSwiftSelf(false), IsSwiftError(false) {}
194
195 void setAttributes(ImmutableCallSite *CS, unsigned ArgIdx);
196 };
197 using ArgListTy = std::vector;
198
199 virtual void markLibCallAttributes(MachineFunction *MF, unsigned CC,
200 ArgListTy &Args) const {};
201
202 static ISD::NodeType getExtendForContent(BooleanContent Content) {
203 switch (Content) {
204 case UndefinedBooleanContent:
205 // Extend by adding rubbish bits.
206 return ISD::ANY_EXTEND;
207 case ZeroOrOneBooleanContent:
208 // Extend by adding zero bits.
209 return ISD::ZERO_EXTEND;
210 case ZeroOrNegativeOneBooleanContent:
211 // Extend by copying the sign bit.
212 return ISD::SIGN_EXTEND;
213 }
214 llvm_unreachable("Invalid content kind");
215 }
216
217 /// NOTE: The TargetMachine owns TLOF.
218 explicit TargetLoweringBase(const TargetMachine &TM);
219 TargetLoweringBase(const TargetLoweringBase &) = delete;
220 TargetLoweringBase &operator=(const TargetLoweringBase &) = delete;
221 virtual ~TargetLoweringBase() = default;
222
223 protected:
224 /// \brief Initialize all of the actions to default values.
225 void initActions();
226
227 public:
228 const TargetMachine &getTargetMachine() const { return TM; }
229
230 virtual bool useSoftFloat() const { return false; }
231
232 /// Return the pointer type for the given address space, defaults to
233 /// the pointer type from the data layout.
234 /// FIXME: The default needs to be removed once all the code is updated.
235 MVT getPointerTy(const DataLayout &DL, uint32_t AS = 0) const {
236 return MVT::getIntegerVT(DL.getPointerSizeInBits(AS));
237 }
238
239 /// Return the type for frame index, which is determined by
240 /// the alloca address space specified through the data layout.
241 MVT getFrameIndexTy(const DataLayout &DL) const {
242 return getPointerTy(DL, DL.getAllocaAddrSpace());
243 }
244
245 /// Return the type for operands of fence.
246 /// TODO: Let fence operands be of i32 type and remove this.
247 virtual MVT getFenceOperandTy(const DataLayout &DL) const {
248 return getPointerTy(DL);
249 }
250
251 /// EVT is not used in-tree, but is used by out-of-tree target.
252 /// A documentation for this function would be nice...
253 virtual MVT getScalarShiftAmountTy(const DataLayout &, EVT) const;
254
255 EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL) const;
256
257 /// Returns the type to be used for the index operand of:
258 /// ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
259 /// ISD::INSERT_SUBVECTOR, and ISD::EXTRACT_SUBVECTOR
260 virtual MVT getVectorIdxTy(const DataLayout &DL) const {
261 return getPointerTy(DL);
262 }
263
264 virtual bool isSelectSupported(SelectSupportKind /*kind*/) const {
265 return true;
266 }
267
268 /// Return true if multiple condition registers are available.
269 bool hasMultipleConditionRegisters() const {
270 return HasMultipleConditionRegisters;
271 }
272
273 /// Return true if the target has BitExtract instructions.
274 bool hasExtractBitsInsn() const { return HasExtractBitsInsn; }
275
276 /// Return the preferred vector type legalization action.
277 virtual TargetLoweringBase::LegalizeTypeAction
278 getPreferredVectorAction(EVT VT) const {
279 // The default action for one element vectors is to scalarize
280 if (VT.getVectorNumElements() == 1)
281 return TypeScalarizeVector;
282 // The default action for other vectors is to promote
283 return TypePromoteInteger;
284 }
285
286 // There are two general methods for expanding a BUILD_VECTOR node:
287 // 1. Use SCALAR_TO_VECTOR on the defined scalar values and then shuffle
288 // them together.
289 // 2. Build the vector on the stack and then load it.
290 // If this function returns true, then method (1) will be used, subject to
291 // the constraint that all of the necessary shuffles are legal (as determined
292 // by isShuffleMaskLegal). If this function returns false, then method (2) is
293 // always used. The vector type, and the number of defined values, are
294 // provided.
295 virtual bool
296 shouldExpandBuildVectorWithShuffles(EVT /* VT */,
297 unsigned DefinedValues) const {
298 return DefinedValues < 3;
299 }
300
301 /// Return true if integer divide is usually cheaper than a sequence of
302 /// several shifts, adds, and multiplies for this target.
303 /// The definition of "cheaper" may depend on whether we're optimizing
304 /// for speed or for size.
305 virtual bool isIntDivCheap(EVT VT, AttributeList Attr) const { return false; }
306
307 /// Return true if the target can handle a standalone remainder operation.
308 virtual bool hasStandaloneRem(EVT VT) const {
309 return true;
310 }
311
312 /// Return true if SQRT(X) shouldn't be replaced with X*RSQRT(X).
313 virtual bool isFsqrtCheap(SDValue X, SelectionDAG &DAG) const {
314 // Default behavior is to replace SQRT(X) with X*RSQRT(X).
315 return false;
316 }
317
318 /// Reciprocal estimate status values used by the functions below.
319 enum ReciprocalEstimate : int {
320 Unspecified = -1,
321 Disabled = 0,
322 Enabled = 1
323 };
324
325 /// Return a ReciprocalEstimate enum value for a square root of the given type
326 /// based on the function's attributes. If the operation is not overridden by
327 /// the function's attributes, "Unspecified" is returned and target defaults
328 /// are expected to be used for instruction selection.
329 int getRecipEstimateSqrtEnabled(EVT VT, MachineFunction &MF) const;
330
331 /// Return a ReciprocalEstimate enum value for a division of the given type
332 /// based on the function's attributes. If the operation is not overridden by
333 /// the function's attributes, "Unspecified" is returned and target defaults
334 /// are expected to be used for instruction selection.
335 int getRecipEstimateDivEnabled(EVT VT, MachineFunction &MF) const;
336
337 /// Return the refinement step count for a square root of the given type based
338 /// on the function's attributes. If the operation is not overridden by
339 /// the function's attributes, "Unspecified" is returned and target defaults
340 /// are expected to be used for instruction selection.
341 int getSqrtRefinementSteps(EVT VT, MachineFunction &MF) const;
342
343 /// Return the refinement step count for a division of the given type based
344 /// on the function's attributes. If the operation is not overridden by
345 /// the function's attributes, "Unspecified" is returned and target defaults
346 /// are expected to be used for instruction selection.
347 int getDivRefinementSteps(EVT VT, MachineFunction &MF) const;
348
349 /// Returns true if target has indicated at least one type should be bypassed.
350 bool isSlowDivBypassed() const { return !BypassSlowDivWidths.empty(); }
351
352 /// Returns map of slow types for division or remainder with corresponding
353 /// fast types
354 const DenseMap &getBypassSlowDivWidths() const {
355 return BypassSlowDivWidths;
356 }
357
358 /// Return true if Flow Control is an expensive operation that should be
359 /// avoided.
360 bool isJumpExpensive() const { return JumpIsExpensive; }
361
362 /// Return true if selects are only cheaper than branches if the branch is
363 /// unlikely to be predicted right.
364 bool isPredictableSelectExpensive() const {
365 return PredictableSelectIsExpensive;
366 }
367
368 /// If a branch or a select condition is skewed in one direction by more than
369 /// this factor, it is very likely to be predicted correctly.
370 virtual BranchProbability getPredictableBranchThreshold() const;
371
372 /// Return true if the following transform is beneficial:
373 /// fold (conv (load x)) -> (load (conv*)x)
374 /// On architectures that don't natively support some vector loads
375 /// efficiently, casting the load to a smaller vector of larger types and
376 /// loading is more efficient, however, this can be undone by optimizations in
377 /// dag combiner.
378 virtual bool isLoadBitCastBeneficial(EVT LoadVT,
379 EVT BitcastVT) const {
380 // Don't do if we could do an indexed load on the original type, but not on
381 // the new one.
382 if (!LoadVT.isSimple() || !BitcastVT.isSimple())
383 return true;
384
385 MVT LoadMVT = LoadVT.getSimpleVT();
386
387 // Don't bother doing this if it's just going to be promoted again later, as
388 // doing so might interfere with other combines.
389 if (getOperationAction(ISD::LOAD, LoadMVT) == Promote &&
390 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT())
391 return false;
392
393 return true;
394 }
395
396 /// Return true if the following transform is beneficial:
397 /// (store (y (conv x)), y*)) -> (store x, (x*))
398 virtual bool isStoreBitCastBeneficial(EVT StoreVT, EVT BitcastVT) const {
399 // Default to the same logic as loads.
400 return isLoadBitCastBeneficial(StoreVT, BitcastVT);
401 }
402
403 /// Return true if it is expected to be cheaper to do a store of a non-zero
404 /// vector constant with the given size and type for the address space than to
405 /// store the individual scalar element constants.
406 virtual bool storeOfVectorConstantIsCheap(EVT MemVT,
407 unsigned NumElem,
408 unsigned AddrSpace) const {
409 return false;
410 }
411
412 /// Allow store merging after legalization in addition to before legalization.
413 /// This may catch stores that do not exist earlier (eg, stores created from
414 /// intrinsics).
415 virtual bool mergeStoresAfterLegalization() const { return false; }
416
417 /// Returns if it's reasonable to merge stores to MemVT size.
418 virtual bool canMergeStoresTo(unsigned AS, EVT MemVT,
419 const SelectionDAG &DAG) const {
420 return true;
421 }
422
423 /// \brief Return true if it is cheap to speculate a call to intrinsic cttz.
424 virtual bool isCheapToSpeculateCttz() const {
425 return false;
426 }
427
428 /// \brief Return true if it is cheap to speculate a call to intrinsic ctlz.
429 virtual bool isCheapToSpeculateCtlz() const {
430 return false;
431 }
432
433 /// \brief Return true if ctlz instruction is fast.
434 virtual bool isCtlzFast() const {
435 return false;
436 }
437
438 /// Return true if it is safe to transform an integer-domain bitwise operation
439 /// into the equivalent floating-point operation. This should be set to true
440 /// if the target has IEEE-754-compliant fabs/fneg operations for the input
441 /// type.
442 virtual bool hasBitPreservingFPLogic(EVT VT) const {
443 return false;
444 }
445
446 /// \brief Return true if it is cheaper to split the store of a merged int val
447 /// from a pair of smaller values into multiple stores.
448 virtual bool isMultiStoresCheaperThanBitsMerge(EVT LTy, EVT HTy) const {
449 return false;
450 }
451
452 /// \brief Return if the target supports combining a
453 /// chain like:
454 /// \code
455 /// %andResult = and %val1, #mask
456 /// %icmpResult = icmp %andResult, 0
457 /// \endcode
458 /// into a single machine instruction of a form like:
459 /// \code
460 /// cc = test %register, #mask
461 /// \endcode
462 virtual bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const {
463 return false;
464 }
465
466 /// Use bitwise logic to make pairs of compares more efficient. For example:
467 /// and (seteq A, B), (seteq C, D) --> seteq (or (xor A, B), (xor C, D)), 0
468 /// This should be true when it takes more than one instruction to lower
469 /// setcc (cmp+set on x86 scalar), when bitwise ops are faster than logic on
470 /// condition bits (crand on PowerPC), and/or when reducing cmp+br is a win.
471 virtual bool convertSetCCLogicToBitwiseLogic(EVT VT) const {
472 return false;
473 }
474
475 /// Return the preferred operand type if the target has a quick way to compare
476 /// integer values of the given size. Assume that any legal integer type can
477 /// be compared efficiently. Targets may override this to allow illegal wide
478 /// types to return a vector type if there is support to compare that type.
479 virtual MVT hasFastEqualityCompare(unsigned NumBits) const {
480 MVT VT = MVT::getIntegerVT(NumBits);
481 return isTypeLegal(VT) ? VT : MVT::INVALID_SIMPLE_VALUE_TYPE;
482 }
483
484 /// Return true if the target should transform:
485 /// (X & Y) == Y ---> (~X & Y) == 0
486 /// (X & Y) != Y ---> (~X & Y) != 0
487 ///
488 /// This may be profitable if the target has a bitwise and-not operation that
489 /// sets comparison flags. A target may want to limit the transformation based
490 /// on the type of Y or if Y is a constant.
491 ///
492 /// Note that the transform will not occur if Y is known to be a power-of-2
493 /// because a mask and compare of a single bit can be handled by inverting the
494 /// predicate, for example:
495 /// (X & 8) == 8 ---> (X & 8) != 0
496 virtual bool hasAndNotCompare(SDValue Y) const {
497 return false;
498 }
499
500 /// Return true if the target has a bitwise and-not operation:
501 /// X = ~A & B
502 /// This can be used to simplify select or other instructions.
503 virtual bool hasAndNot(SDValue X) const {
504 // If the target has the more complex version of this operation, assume that
505 // it has this operation too.
506 return hasAndNotCompare(X);
507 }
508
509 /// \brief Return true if the target wants to use the optimization that
510 /// turns ext(promotableInst1(...(promotableInstN(load)))) into
511 /// promotedInst1(...(promotedInstN(ext(load)))).
512 bool enableExtLdPromotion() const { return EnableExtLdPromotion; }
513
514 /// Return true if the target can combine store(extractelement VectorTy,
515 /// Idx).
516 /// \p Cost[out] gives the cost of that transformation when this is true.
517 virtual bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
518 unsigned &Cost) const {
519 return false;
520 }
521
522 /// Return true if target supports floating point exceptions.
523 bool hasFloatingPointExceptions() const {
524 return HasFloatingPointExceptions;
525 }
526
527 /// Return true if target always beneficiates from combining into FMA for a
528 /// given value type. This must typically return false on targets where FMA
529 /// takes more cycles to execute than FADD.
530 virtual bool enableAggressiveFMAFusion(EVT VT) const {
531 return false;
532 }
533
534 /// Return the ValueType of the result of SETCC operations.
535 virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
536 EVT VT) const;
537
538 /// Return the ValueType for comparison libcalls. Comparions libcalls include
539 /// floating point comparion calls, and Ordered/Unordered check calls on
540 /// floating point numbers.
541 virtual
542 MVT::SimpleValueType getCmpLibcallReturnType() const;
543
544 /// For targets without i1 registers, this gives the nature of the high-bits
545 /// of boolean values held in types wider than i1.
546 ///
547 /// "Boolean values" are special true/false values produced by nodes like
548 /// SETCC and consumed (as the condition) by nodes like SELECT and BRCOND.
549 /// Not to be confused with general values promoted from i1. Some cpus
550 /// distinguish between vectors of boolean and scalars; the isVec parameter
551 /// selects between the two kinds. For example on X86 a scalar boolean should
552 /// be zero extended from i1, while the elements of a vector of booleans
553 /// should be sign extended from i1.
554 ///
555 /// Some cpus also treat floating point types the same way as they treat
556 /// vectors instead of the way they treat scalars.
557 BooleanContent getBooleanContents(bool isVec, bool isFloat) const {
558 if (isVec)
559 return BooleanVectorContents;
560 return isFloat ? BooleanFloatContents : BooleanContents;
561 }
562
563 BooleanContent getBooleanContents(EVT Type) const {
564 return getBooleanContents(Type.isVector(), Type.isFloatingPoint());
565 }
566
567 /// Return target scheduling preference.
568 Sched::Preference getSchedulingPreference() const {
569 return SchedPreferenceInfo;
570 }
571
572 /// Some scheduler, e.g. hybrid, can switch to different scheduling heuristics
573 /// for different nodes. This function returns the preference (or none) for
574 /// the given node.
575 virtual Sched::Preference getSchedulingPreference(SDNode *) const {
576 return Sched::None;
577 }
578
579 /// Return the register class that should be used for the specified value
580 /// type.
581 virtual const TargetRegisterClass *getRegClassFor(MVT VT) const {
582 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
583 assert(RC && "This value type is not natively supported!");
584 return RC;
585 }
586
587 /// Return the 'representative' register class for the specified value
588 /// type.
589 ///
590 /// The 'representative' register class is the largest legal super-reg
591 /// register class for the register class of the value type. For example, on
592 /// i386 the rep register class for i8, i16, and i32 are GR32; while the rep
593 /// register class is GR64 on x86_64.
594 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
595 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
596 return RC;
597 }
598
599 /// Return the cost of the 'representative' register class for the specified
600 /// value type.
601 virtual uint8_t getRepRegClassCostFor(MVT VT) const {
602 return RepRegClassCostForVT[VT.SimpleTy];
603 }
604
605 /// Return true if the target has native support for the specified value type.
606 /// This means that it has a register that directly holds it without
607 /// promotions or expansions.
608 bool isTypeLegal(EVT VT) const {
609 assert(!VT.isSimple() ||
610 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT));
611 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr;
612 }
613
614 class ValueTypeActionImpl {
615 /// ValueTypeActions - For each value type, keep a LegalizeTypeAction enum
616 /// that indicates how instruction selection should deal with the type.
617 LegalizeTypeAction ValueTypeActions[MVT::LAST_VALUETYPE];
618
619 public:
620 ValueTypeActionImpl() {
621 std::fill(std::begin(ValueTypeActions), std::end(ValueTypeActions),
622 TypeLegal);
623 }
624
625 LegalizeTypeAction getTypeAction(MVT VT) const {
626 return ValueTypeActions[VT.SimpleTy];
627 }
628
629 void setTypeAction(MVT VT, LegalizeTypeAction Action) {
630 ValueTypeActions[VT.SimpleTy] = Action;
631 }
632 };
633
634 const ValueTypeActionImpl &getValueTypeActions() const {
635 return ValueTypeActions;
636 }
637
638 /// Return how we should legalize values of this type, either it is already
639 /// legal (return 'Legal') or we need to promote it to a larger type (return
640 /// 'Promote'), or we need to expand it into multiple registers of smaller
641 /// integer type (return 'Expand'). 'Custom' is not an option.
642 LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const {
643 return getTypeConversion(Context, VT).first;
644 }
645 LegalizeTypeAction getTypeAction(MVT VT) const {
646 return ValueTypeActions.getTypeAction(VT);
647 }
648
649 /// For types supported by the target, this is an identity function. For
650 /// types that must be promoted to larger types, this returns the larger type
651 /// to promote to. For integer types that are larger than the largest integer
652 /// register, this contains one step in the expansion to get to the smaller
653 /// register. For illegal floating point types, this returns the integer type
654 /// to transform to.
655 EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const {
656 return getTypeConversion(Context, VT).second;
657 }
658
659 /// For types supported by the target, this is an identity function. For
660 /// types that must be expanded (i.e. integer types that are larger than the
661 /// largest integer register or illegal floating point types), this returns
662 /// the largest legal type it will be expanded to.
663 EVT getTypeToExpandTo(LLVMContext &Context, EVT VT) const {
664 assert(!VT.isVector());
665 while (true) {
666 switch (getTypeAction(Context, VT)) {
667 case TypeLegal:
668 return VT;
669 case TypeExpandInteger:
670 VT = getTypeToTransformTo(Context, VT);
671 break;
672 default:
673 llvm_unreachable("Type is not legal nor is it to be expanded!");
674 }
675 }
676 }
677
678 /// Vector types are broken down into some number of legal first class types.
679 /// For example, EVT::v8f32 maps to 2 EVT::v4f32 with Altivec or SSE1, or 8
680 /// promoted EVT::f64 values with the X86 FP stack. Similarly, EVT::v2i64
681 /// turns into 4 EVT::i32 values with both PPC and X86.
682 ///
683 /// This method returns the number of registers needed, and the VT for each
684 /// register. It also returns the VT and quantity of the intermediate values
685 /// before they are promoted/expanded.
686 unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
687 EVT &IntermediateVT,
688 unsigned &NumIntermediates,
689 MVT &RegisterVT) const;
690
691 /// Certain targets such as MIPS require that some types such as vectors are
692 /// always broken down into scalars in some contexts. This occurs even if the
693 /// vector type is legal.
694 virtual unsigned getVectorTypeBreakdownForCallingConv(
695 LLVMContext &Context, EVT VT, EVT &IntermediateVT,
696 unsigned &NumIntermediates, MVT &RegisterVT) const {
697 return getVectorTypeBreakdown(Context, VT, IntermediateVT, NumIntermediates,
698 RegisterVT);
699 }
700
701 struct IntrinsicInfo {
702 unsigned opc = 0; // target opcode
703 EVT memVT; // memory VT
704 const Value* ptrVal = nullptr; // value representing memory location
705 int offset = 0; // offset off of ptrVal
706 unsigned size = 0; // the size of the memory location
707 // (taken from memVT if zero)
708 unsigned align = 1; // alignment
709 bool vol = false; // is volatile?
710 bool readMem = false; // reads memory?
711 bool writeMem = false; // writes memory?
712
713 IntrinsicInfo() = default;
714 };
715
716 /// Given an intrinsic, checks if on the target the intrinsic will need to map
717 /// to a MemIntrinsicNode (touches memory). If this is the case, it returns
718 /// true and store the intrinsic information into the IntrinsicInfo that was
719 /// passed to the function.
720 virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
721 unsigned /*Intrinsic*/) const {
722 return false;
723 }
724
725 /// Returns true if the target can instruction select the specified FP
726 /// immediate natively. If false, the legalizer will materialize the FP
727 /// immediate as a load from a constant pool.
728 virtual bool isFPImmLegal(const APFloat &/*Imm*/, EVT /*VT*/) const {
729 return false;
730 }
731
732 /// Targets can use this to indicate that they only support *some*
733 /// VECTOR_SHUFFLE operations, those with specific masks. By default, if a
734 /// target supports the VECTOR_SHUFFLE node, all mask values are assumed to be
735 /// legal.
736 virtual bool isShuffleMaskLegal(ArrayRef /*Mask*/, EVT /*VT*/) const {
737 return true;
738 }
739
740 /// Returns true if the operation can trap for the value type.
741 ///
742 /// VT must be a legal type. By default, we optimistically assume most
743 /// operations don't trap except for integer divide and remainder.
744 virtual bool canOpTrap(unsigned Op, EVT VT) const;
745
746 /// Similar to isShuffleMaskLegal. This is used by Targets can use this to
747 /// indicate if there is a suitable VECTOR_SHUFFLE that can be used to replace
748 /// a VAND with a constant pool entry.
749 virtual bool isVectorClearMaskLegal(const SmallVectorImpl &/*Mask*/,
750 EVT /*VT*/) const {
751 return false;
752 }
753
754 /// Return how this operation should be treated: either it is legal, needs to
755 /// be promoted to a larger size, needs to be expanded to some other code
756 /// sequence, or the target has a custom expander for it.
757 LegalizeAction getOperationAction(unsigned Op, EVT VT) const {
758 if (VT.isExtended()) return Expand;
759 // If a target-specific SDNode requires legalization, require the target
760 // to provide custom legalization for it.
761 if (Op >= array_lengthof(OpActions[0])) return Custom;
762 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op];
763 }
764
765 /// Return true if the specified operation is legal on this target or can be
766 /// made legal with custom lowering. This is used to help guide high-level
767 /// lowering decisions.
768 bool isOperationLegalOrCustom(unsigned Op, EVT VT) const {
769 return (VT == MVT::Other || isTypeLegal(VT)) &&
770 (getOperationAction(Op, VT) == Legal ||
771 getOperationAction(Op, VT) == Custom);
772 }
773
774 /// Return true if the specified operation is legal on this target or can be
775 /// made legal using promotion. This is used to help guide high-level lowering
776 /// decisions.
777 bool isOperationLegalOrPromote(unsigned Op, EVT VT) const {
778 return (VT == MVT::Other || isTypeLegal(VT)) &&
779 (getOperationAction(Op, VT) == Legal ||
780 getOperationAction(Op, VT) == Promote);
781 }
782
783 /// Return true if the specified operation is legal on this target or can be
784 /// made legal with custom lowering or using promotion. This is used to help
785 /// guide high-level lowering decisions.
786 bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT) const {
787 return (VT == MVT::Other || isTypeLegal(VT)) &&
788 (getOperationAction(Op, VT) == Legal ||
789 getOperationAction(Op, VT) == Custom ||
790 getOperationAction(Op, VT) == Promote);
791 }
792
793 /// Return true if the operation uses custom lowering, regardless of whether
794 /// the type is legal or not.
795 bool isOperationCustom(unsigned Op, EVT VT) const {
796 return getOperationAction(Op, VT) == Custom;
797 }
798
799 /// Return true if lowering to a jump table is allowed.
800 bool areJTsAllowed(const Function *Fn) const {
801 if (Fn->getFnAttribute("no-jump-tables").getValueAsString() == "true")
802 return false;
803
804 return isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
805 isOperationLegalOrCustom(ISD::BRIND, MVT::Other);
806 }
807
808 /// Check whether the range [Low,High] fits in a machine word.
809 bool rangeFitsInWord(const APInt &Low, const APInt &High,
810 const DataLayout &DL) const {
811 // FIXME: Using the pointer type doesn't seem ideal.
812 uint64_t BW = DL.getPointerSizeInBits();
813 uint64_t Range = (High - Low).getLimitedValue(UINT64_MAX - 1) + 1;
814 return Range <= BW;
815 }
816
817 /// Return true if lowering to a jump table is suitable for a set of case
818 /// clusters which may contain \p NumCases cases, \p Range range of values.
819 /// FIXME: This function check the maximum table size and density, but the
820 /// minimum size is not checked. It would be nice if the the minimum size is
821 /// also combined within this function. Currently, the minimum size check is
822 /// performed in findJumpTable() in SelectionDAGBuiler and
823 /// getEstimatedNumberOfCaseClusters() in BasicTTIImpl.
824 bool isSuitableForJumpTable(const SwitchInst *SI, uint64_t NumCases,
825 uint64_t Range) const {
826 const bool OptForSize = SI->getParent()->getParent()->optForSize();
827 const unsigned MinDensity = getMinimumJumpTableDensity(OptForSize);
828 const unsigned MaxJumpTableSize =
829 OptForSize || getMaximumJumpTableSize() == 0
830 ? UINT_MAX
831 : getMaximumJumpTableSize();
832 // Check whether a range of clusters is dense enough for a jump table.
833 if (Range <= MaxJumpTableSize &&
834 (NumCases * 100 >= Range * MinDensity)) {
835 return true;
836 }
837 return false;
838 }
839
840 /// Return true if lowering to a bit test is suitable for a set of case
841 /// clusters which contains \p NumDests unique destinations, \p Low and
842 /// \p High as its lowest and highest case values, and expects \p NumCmps
843 /// case value comparisons. Check if the number of destinations, comparison
844 /// metric, and range are all suitable.
845 bool isSuitableForBitTests(unsigned NumDests, unsigned NumCmps,
846 const APInt &Low, const APInt &High,
847 const DataLayout &DL) const {
848 // FIXME: I don't think NumCmps is the correct metric: a single case and a
849 // range of cases both require only one branch to lower. Just looking at the
850 // number of clusters and destinations should be enough to decide whether to
851 // build bit tests.
852
853 // To lower a range with bit tests, the range must fit the bitwidth of a
854 // machine word.
855 if (!rangeFitsInWord(Low, High, DL))
856 return false;
857
858 // Decide whether it's profitable to lower this range with bit tests. Each
859 // destination requires a bit test and branch, and there is an overall range
860 // check branch. For a small number of clusters, separate comparisons might
861 // be cheaper, and for many destinations, splitting the range might be
862 // better.
863 return (NumDests == 1 && NumCmps >= 3) || (NumDests == 2 && NumCmps >= 5) ||
864 (NumDests == 3 && NumCmps >= 6);
865 }
866
867 /// Return true if the specified operation is illegal on this target or
868 /// unlikely to be made legal with custom lowering. This is used to help guide
869 /// high-level lowering decisions.
870 bool isOperationExpand(unsigned Op, EVT VT) const {
871 return (!isTypeLegal(VT) || getOperationAction(Op, VT) == Expand);
872 }
873
874 /// Return true if the specified operation is legal on this target.
875 bool isOperationLegal(unsigned Op, EVT VT) const {
876 return (VT == MVT::Other || isTypeLegal(VT)) &&
877 getOperationAction(Op, VT) == Legal;
878 }
879
880 /// Return how this load with extension should be treated: either it is legal,
881 /// needs to be promoted to a larger size, needs to be expanded to some other
882 /// code sequence, or the target has a custom expander for it.
883 LegalizeAction getLoadExtAction(unsigned ExtType, EVT ValVT,
884 EVT MemVT) const {
885 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
886 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
887 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
888 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValI < MVT::LAST_VALUETYPE &&
889 MemI < MVT::LAST_VALUETYPE && "Table isn't big enough!");
890 unsigned Shift = 4 * ExtType;
891 return (LegalizeAction)((LoadExtActions[ValI][MemI] >> Shift) & 0xf);
892 }
893
894 /// Return true if the specified load with extension is legal on this target.
895 bool isLoadExtLegal(unsigned ExtType, EVT ValVT, EVT MemVT) const {
896 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal;
897 }
898
899 /// Return true if the specified load with extension is legal or custom
900 /// on this target.
901 bool isLoadExtLegalOrCustom(unsigned ExtType, EVT ValVT, EVT MemVT) const {
902 return getLoadExtAction(ExtType, ValVT, MemVT) == Legal ||
903 getLoadExtAction(ExtType, ValVT, MemVT) == Custom;
904 }
905
906 /// Return how this store with truncation should be treated: either it is
907 /// legal, needs to be promoted to a larger size, needs to be expanded to some
908 /// other code sequence, or the target has a custom expander for it.
909 LegalizeAction getTruncStoreAction(EVT ValVT, EVT MemVT) const {
910 if (ValVT.isExtended() || MemVT.isExtended()) return Expand;
911 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy;
912 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy;
913 assert(ValI < MVT::LAST_VALUETYPE && MemI < MVT::LAST_VALUETYPE &&
914 "Table isn't big enough!");
915 return TruncStoreActions[ValI][MemI];
916 }
917
918 /// Return true if the specified store with truncation is legal on this
919 /// target.
920 bool isTruncStoreLegal(EVT ValVT, EVT MemVT) const {
921 return isTypeLegal(ValVT) && getTruncStoreAction(ValVT, MemVT) == Legal;
922 }
923
924 /// Return true if the specified store with truncation has solution on this
925 /// target.
926 bool isTruncStoreLegalOrCustom(EVT ValVT, EVT MemVT) const {
927 return isTypeLegal(ValVT) &&
928 (getTruncStoreAction(ValVT, MemVT) == Legal ||
929 getTruncStoreAction(ValVT, MemVT) == Custom);
930 }
931
932 /// Return how the indexed load should be treated: either it is legal, needs
933 /// to be promoted to a larger size, needs to be expanded to some other code
934 /// sequence, or the target has a custom expander for it.
935 LegalizeAction
936 getIndexedLoadAction(unsigned IdxMode, MVT VT) const {
937 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
938 "Table isn't big enough!");
939 unsigned Ty = (unsigned)VT.SimpleTy;
940 return (LegalizeAction)((IndexedModeActions[Ty][IdxMode] & 0xf0) >> 4);
941 }
942
943 /// Return true if the specified indexed load is legal on this target.
944 bool isIndexedLoadLegal(unsigned IdxMode, EVT VT) const {
945 return VT.isSimple() &&
946 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal ||
947 getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Custom);
948 }
949
950 /// Return how the indexed store should be treated: either it is legal, needs
951 /// to be promoted to a larger size, needs to be expanded to some other code
952 /// sequence, or the target has a custom expander for it.
953 LegalizeAction
954 getIndexedStoreAction(unsigned IdxMode, MVT VT) const {
955 assert(IdxMode < ISD::LAST_INDEXED_MODE && VT.isValid() &&
956 "Table isn't big enough!");
957 unsigned Ty = (unsigned)VT.SimpleTy;
958 return (LegalizeAction)(IndexedModeActions[Ty][IdxMode] & 0x0f);
959 }
960
961 /// Return true if the specified indexed load is legal on this target.
962 bool isIndexedStoreLegal(unsigned IdxMode, EVT VT) const {
963 return VT.isSimple() &&
964 (getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Legal ||
965 getIndexedStoreAction(IdxMode, VT.getSimpleVT()) == Custom);
966 }
967
968 /// Return how the condition code should be treated: either it is legal, needs
969 /// to be expanded to some other code sequence, or the target has a custom
970 /// expander for it.
971 LegalizeAction
972 getCondCodeAction(ISD::CondCode CC, MVT VT) const {
973 assert((unsigned)CC < array_lengthof(CondCodeActions) &&
974 ((unsigned)VT.SimpleTy >> 3) < array_lengthof(CondCodeActions[0]) &&
975 "Table isn't big enough!");
976 // See setCondCodeAction for how this is encoded.
977 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
978 uint32_t Value = CondCodeActions[CC][VT.SimpleTy >> 3];
979 LegalizeAction Action = (LegalizeAction) ((Value >> Shift) & 0xF);
980 assert(Action != Promote && "Can't promote condition code!");
981 return Action;
982 }
983
984 /// Return true if the specified condition code is legal on this target.
985 bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const {
986 return
987 getCondCodeAction(CC, VT) == Legal ||
988 getCondCodeAction(CC, VT) == Custom;
989 }
990
991 /// If the action for this operation is to promote, this method returns the
992 /// ValueType to promote to.
993 MVT getTypeToPromoteTo(unsigned Op, MVT VT) const {
994 assert(getOperationAction(Op, VT) == Promote &&
995 "This operation isn't promoted!");
996
997 // See if this has an explicit type specified.
998 std::map,
999 MVT::SimpleValueType>::const_iterator PTTI =
1000 PromoteToType.find(std::make_pair(Op, VT.SimpleTy));
1001 if (PTTI != PromoteToType.end()) return PTTI->second;
1002
1003 assert((VT.isInteger() || VT.isFloatingPoint()) &&
1004 "Cannot autopromote this type, add it with AddPromotedToType.");
1005
1006 MVT NVT = VT;
1007 do {
1008 NVT = (MVT::SimpleValueType)(NVT.SimpleTy+1);
1009 assert(NVT.isInteger() == VT.isInteger() && NVT != MVT::isVoid &&
1010 "Didn't find type to promote to!");
1011 } while (!isTypeLegal(NVT) ||
1012 getOperationAction(Op, NVT) == Promote);
1013 return NVT;
1014 }
1015
1016 /// Return the EVT corresponding to this LLVM type. This is fixed by the LLVM
1017 /// operations except for the pointer size. If AllowUnknown is true, this
1018 /// will return MVT::Other for types with no EVT counterpart (e.g. structs),
1019 /// otherwise it will assert.
1020 EVT getValueType(const DataLayout &DL, Type *Ty,
1021 bool AllowUnknown = false) const {
1022 // Lower scalar pointers to native pointer types.
1023 if (PointerType *PTy = dyn_cast(Ty))
1024 return getPointerTy(DL, PTy->getAddressSpace());
1025
1026 if (Ty->isVectorTy()) {
1027 VectorType *VTy = cast(Ty);
1028 Type *Elm = VTy->getElementType();
1029 // Lower vectors of pointers to native pointer types.
1030 if (PointerType *PT = dyn_cast(Elm)) {
1031 EVT PointerTy(getPointerTy(DL, PT->getAddressSpace()));
1032 Elm = PointerTy.getTypeForEVT(Ty->getContext());
1033 }
1034
1035 return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
1036 VTy->getNumElements());
1037 }
1038 return EVT::getEVT(Ty, AllowUnknown);
1039 }
1040
1041 /// Return the MVT corresponding to this LLVM type. See getValueType.
1042 MVT getSimpleValueType(const DataLayout &DL, Type *Ty,
1043 bool AllowUnknown = false) const {
1044 return getValueType(DL, Ty, AllowUnknown).getSimpleVT();
1045 }
1046
1047 /// Return the desired alignment for ByVal or InAlloca aggregate function
1048 /// arguments in the caller parameter area. This is the actual alignment, not
1049 /// its logarithm.
1050 virtual unsigned getByValTypeAlignment(Type *Ty, const DataLayout &DL) const;
1051
1052 /// Return the type of registers that this ValueType will eventually require.
1053 MVT getRegisterType(MVT VT) const {
1054 assert((unsigned)VT.SimpleTy < array_lengthof(RegisterTypeForVT));
1055 return RegisterTypeForVT[VT.SimpleTy];
1056 }
1057
1058 /// Return the type of registers that this ValueType will eventually require.
1059 MVT getRegisterType(LLVMContext &Context, EVT VT) const {
1060 if (VT.isSimple()) {
1061 assert((unsigned)VT.getSimpleVT().SimpleTy <
1062 array_lengthof(RegisterTypeForVT));
1063 return RegisterTypeForVT[VT.getSimpleVT().SimpleTy];
1064 }
1065 if (VT.isVector()) {
1066 EVT VT1;
1067 MVT RegisterVT;
1068 unsigned NumIntermediates;
1069 (void)getVectorTypeBreakdown(Context, VT, VT1,
1070 NumIntermediates, RegisterVT);
1071 return RegisterVT;
1072 }
1073 if (VT.isInteger()) {
1074 return getRegisterType(Context, getTypeToTransformTo(Context, VT));
1075 }
1076 llvm_unreachable("Unsupported extended type!");
1077 }
1078
1079 /// Return the number of registers that this ValueType will eventually
1080 /// require.
1081 ///
1082 /// This is one for any types promoted to live in larger registers, but may be
1083 /// more than one for types (like i64) that are split into pieces. For types
1084 /// like i140, which are first promoted then expanded, it is the number of
1085 /// registers needed to hold all the bits of the original type. For an i140
1086 /// on a 32 bit machine this means 5 registers.
1087 unsigned getNumRegisters(LLVMContext &Context, EVT VT) const {
1088 if (VT.isSimple()) {
1089 assert((unsigned)VT.getSimpleVT().SimpleTy <
1090 array_lengthof(NumRegistersForVT));
1091 return NumRegistersForVT[VT.getSimpleVT().SimpleTy];
1092 }
1093 if (VT.isVector()) {
1094 EVT VT1;
1095 MVT VT2;
1096 unsigned NumIntermediates;
1097 return getVectorTypeBreakdown(Context, VT, VT1, NumIntermediates, VT2);
1098 }
1099 if (VT.isInteger()) {
1100 unsigned BitWidth = VT.getSizeInBits();
1101 unsigned RegWidth = getRegisterType(Context, VT).getSizeInBits();
1102 return (BitWidth + RegWidth - 1) / RegWidth;
1103 }
1104 llvm_unreachable("Unsupported extended type!");
1105 }
1106
1107 /// Certain combinations of ABIs, Targets and features require that types
1108 /// are legal for some operations and not for other operations.
1109 /// For MIPS all vector types must be passed through the integer register set.
1110 virtual MVT getRegisterTypeForCallingConv(MVT VT) const {
1111 return getRegisterType(VT);
1112 }
1113
1114 virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context,
1115 EVT VT) const {
1116 return getRegisterType(Context, VT);
1117 }
1118
1119 /// Certain targets require unusual breakdowns of certain types. For MIPS,
1120 /// this occurs when a vector type is used, as vector are passed through the
1121 /// integer register set.
1122 virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context,
1123 EVT VT) const {
1124 return getNumRegisters(Context, VT);
1125 }
1126
1127 /// Certain targets have context senstive alignment requirements, where one
1128 /// type has the alignment requirement of another type.
1129 virtual unsigned getABIAlignmentForCallingConv(Type *ArgTy,
1130 DataLayout DL) const {
1131 return DL.getABITypeAlignment(ArgTy);
1132 }
1133
1134 /// If true, then instruction selection should seek to shrink the FP constant
1135 /// of the specified type to a smaller type in order to save space and / or
1136 /// reduce runtime.
1137 virtual bool ShouldShrinkFPConstant(EVT) const { return true; }
1138
1139 // Return true if it is profitable to reduce the given load node to a smaller
1140 // type.
1141 //
1142 // e.g. (i16 (trunc (i32 (load x))) -> i16 load x should be performed
1143 virtual bool shouldReduceLoadWidth(SDNode *Load,
1144 ISD::LoadExtType ExtTy,
1145 EVT NewVT) const {
1146 return true;
1147 }
1148
1149 /// When splitting a value of the specified type into parts, does the Lo
1150 /// or Hi part come first? This usually follows the endianness, except
1151 /// for ppcf128, where the Hi part always comes first.
1152 bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const {
1153 return DL.isBigEndian() || VT == MVT::ppcf128;
1154 }
1155
1156 /// If true, the target has custom DAG combine transformations that it can
1157 /// perform for the specified node.
1158 bool hasTargetDAGCombine(ISD::NodeType NT) const {
1159 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1160 return TargetDAGCombineArray[NT >> 3] & (1 << (NT&7));
1161 }
1162
1163 unsigned getGatherAllAliasesMaxDepth() const {
1164 return GatherAllAliasesMaxDepth;
1165 }
1166
1167 /// Returns the size of the platform's va_list object.
1168 virtual unsigned getVaListSizeInBits(const DataLayout &DL) const {
1169 return getPointerTy(DL).getSizeInBits();
1170 }
1171
1172 /// \brief Get maximum # of store operations permitted for llvm.memset
1173 ///
1174 /// This function returns the maximum number of store operations permitted
1175 /// to replace a call to llvm.memset. The value is set by the target at the
1176 /// performance threshold for such a replacement. If OptSize is true,
1177 /// return the limit for functions that have OptSize attribute.
1178 unsigned getMaxStoresPerMemset(bool OptSize) const {
1179 return OptSize ? MaxStoresPerMemsetOptSize : MaxStoresPerMemset;
1180 }
1181
1182 /// \brief Get maximum # of store operations permitted for llvm.memcpy
1183 ///
1184 /// This function returns the maximum number of store operations permitted
1185 /// to replace a call to llvm.memcpy. The value is set by the target at the
1186 /// performance threshold for such a replacement. If OptSize is true,
1187 /// return the limit for functions that have OptSize attribute.
1188 unsigned getMaxStoresPerMemcpy(bool OptSize) const {
1189 return OptSize ? MaxStoresPerMemcpyOptSize : MaxStoresPerMemcpy;
1190 }
1191
1192 /// Get maximum # of load operations permitted for memcmp
1193 ///
1194 /// This function returns the maximum number of load operations permitted
1195 /// to replace a call to memcmp. The value is set by the target at the
1196 /// performance threshold for such a replacement. If OptSize is true,
1197 /// return the limit for functions that have OptSize attribute.
1198 unsigned getMaxExpandSizeMemcmp(bool OptSize) const {
1199 return OptSize ? MaxLoadsPerMemcmpOptSize : MaxLoadsPerMemcmp;
1200 }
1201
1202 /// \brief Get maximum # of store operations permitted for llvm.memmove
1203 ///
1204 /// This function returns the maximum number of store operations permitted
1205 /// to replace a call to llvm.memmove. The value is set by the target at the
1206 /// performance threshold for such a replacement. If OptSize is true,
1207 /// return the limit for functions that have OptSize attribute.
1208 unsigned getMaxStoresPerMemmove(bool OptSize) const {
1209 return OptSize ? MaxStoresPerMemmoveOptSize : MaxStoresPerMemmove;
1210 }
1211
1212 /// \brief Determine if the target supports unaligned memory accesses.
1213 ///
1214 /// This function returns true if the target allows unaligned memory accesses
1215 /// of the specified type in the given address space. If true, it also returns
1216 /// whether the unaligned memory access is "fast" in the last argument by
1217 /// reference. This is used, for example, in situations where an array
1218 /// copy/move/set is converted to a sequence of store operations. Its use
1219 /// helps to ensure that such replacements don't generate code that causes an
1220 /// alignment error (trap) on the target machine.
1221 virtual bool allowsMisalignedMemoryAccesses(EVT,
1222 unsigned AddrSpace = 0,
1223 unsigned Align = 1,
1224 bool * /*Fast*/ = nullptr) const {
1225 return false;
1226 }
1227
1228 /// Return true if the target supports a memory access of this type for the
1229 /// given address space and alignment. If the access is allowed, the optional
1230 /// final parameter returns if the access is also fast (as defined by the
1231 /// target).
1232 bool allowsMemoryAccess(LLVMContext &Context, const DataLayout &DL, EVT VT,
1233 unsigned AddrSpace = 0, unsigned Alignment = 1,
1234 bool *Fast = nullptr) const;
1235
1236 /// Returns the target specific optimal type for load and store operations as
1237 /// a result of memset, memcpy, and memmove lowering.
1238 ///
1239 /// If DstAlign is zero that means it's safe to destination alignment can
1240 /// satisfy any constraint. Similarly if SrcAlign is zero it means there isn't
1241 /// a need to check it against alignment requirement, probably because the
1242 /// source does not need to be loaded. If 'IsMemset' is true, that means it's
1243 /// expanding a memset. If 'ZeroMemset' is true, that means it's a memset of
1244 /// zero. 'MemcpyStrSrc' indicates whether the memcpy source is constant so it
1245 /// does not need to be loaded. It returns EVT::Other if the type should be
1246 /// determined using generic target-independent logic.
1247 virtual EVT getOptimalMemOpType(uint64_t /*Size*/,
1248 unsigned /*DstAlign*/, unsigned /*SrcAlign*/,
1249 bool /*IsMemset*/,
1250 bool /*ZeroMemset*/,
1251 bool /*MemcpyStrSrc*/,
1252 MachineFunction &/*MF*/) const {
1253 return MVT::Other;
1254 }
1255
1256 /// Returns true if it's safe to use load / store of the specified type to
1257 /// expand memcpy / memset inline.
1258 ///
1259 /// This is mostly true for all types except for some special cases. For
1260 /// example, on X86 targets without SSE2 f64 load / store are done with fldl /
1261 /// fstpl which also does type conversion. Note the specified type doesn't
1262 /// have to be legal as the hook is used before type legalization.
1263 virtual bool isSafeMemOpType(MVT /*VT*/) const { return true; }
1264
1265 /// Determine if we should use _setjmp or setjmp to implement llvm.setjmp.
1266 bool usesUnderscoreSetJmp() const {
1267 return UseUnderscoreSetJmp;
1268 }
1269
1270 /// Determine if we should use _longjmp or longjmp to implement llvm.longjmp.
1271 bool usesUnderscoreLongJmp() const {
1272 return UseUnderscoreLongJmp;
1273 }
1274
1275 /// Return lower limit for number of blocks in a jump table.
1276 unsigned getMinimumJumpTableEntries() const;
1277
1278 /// Return lower limit of the density in a jump table.
1279 unsigned getMinimumJumpTableDensity(bool OptForSize) const;
1280
1281 /// Return upper limit for number of entries in a jump table.
1282 /// Zero if no limit.
1283 unsigned getMaximumJumpTableSize() const;
1284
1285 virtual bool isJumpTableRelative() const {
1286 return TM.isPositionIndependent();
1287 }
1288
1289 /// If a physical register, this specifies the register that
1290 /// llvm.savestack/llvm.restorestack should save and restore.
1291 unsigned getStackPointerRegisterToSaveRestore() const {
1292 return StackPointerRegisterToSaveRestore;
1293 }
1294
1295 /// If a physical register, this returns the register that receives the
1296 /// exception address on entry to an EH pad.
1297 virtual unsigned
1298 getExceptionPointerRegister(const Constant *PersonalityFn) const {
1299 // 0 is guaranteed to be the NoRegister value on all targets
1300 return 0;
1301 }
1302
1303 /// If a physical register, this returns the register that receives the
1304 /// exception typeid on entry to a landing pad.
1305 virtual unsigned
1306 getExceptionSelectorRegister(const Constant *PersonalityFn) const {
1307 // 0 is guaranteed to be the NoRegister value on all targets
1308 return 0;
1309 }
1310
1311 virtual bool needsFixedCatchObjects() const {
1312 report_fatal_error("Funclet EH is not implemented for this target");
1313 }
1314
1315 /// Returns the target's jmp_buf size in bytes (if never set, the default is
1316 /// 200)
1317 unsigned getJumpBufSize() const {
1318 return JumpBufSize;
1319 }
1320
1321 /// Returns the target's jmp_buf alignment in bytes (if never set, the default
1322 /// is 0)
1323 unsigned getJumpBufAlignment() const {
1324 return JumpBufAlignment;
1325 }
1326
1327 /// Return the minimum stack alignment of an argument.
1328 unsigned getMinStackArgumentAlignment() const {
1329 return MinStackArgumentAlignment;
1330 }
1331
1332 /// Return the minimum function alignment.
1333 unsigned getMinFunctionAlignment() const {
1334 return MinFunctionAlignment;
1335 }
1336
1337 /// Return the preferred function alignment.
1338 unsigned getPrefFunctionAlignment() const {
1339 return PrefFunctionAlignment;
1340 }
1341
1342 /// Return the preferred loop alignment.
1343 virtual unsigned getPrefLoopAlignment(MachineLoop *ML = nullptr) const {
1344 return PrefLoopAlignment;
1345 }
1346
1347 /// If the target has a standard location for the stack protector guard,
1348 /// returns the address of that location. Otherwise, returns nullptr.
1349 /// DEPRECATED: please override useLoadStackGuardNode and customize
1350 /// LOAD_STACK_GUARD, or customize @llvm.stackguard().
1351 virtual Value *getIRStackGuard(IRBuilder<> &IRB) const;
1352
1353 /// Inserts necessary declarations for SSP (stack protection) purpose.
1354 /// Should be used only when getIRStackGuard returns nullptr.
1355 virtual void insertSSPDeclarations(Module &M) const;
1356
1357 /// Return the variable that's previously inserted by insertSSPDeclarations,
1358 /// if any, otherwise return nullptr. Should be used only when
1359 /// getIRStackGuard returns nullptr.
1360 virtual Value *getSDagStackGuard(const Module &M) const;
1361
1362 /// If the target has a standard stack protection check function that
1363 /// performs validation and error handling, returns the function. Otherwise,
1364 /// returns nullptr. Must be previously inserted by insertSSPDeclarations.
1365 /// Should be used only when getIRStackGuard returns nullptr.
1366 virtual Value *getSSPStackGuardCheck(const Module &M) const;
1367
1368 protected:
1369 Value *getDefaultSafeStackPointerLocation(IRBuilder<> &IRB,
1370 bool UseTLS) const;
1371
1372 public:
1373 /// Returns the target-specific address of the unsafe stack pointer.
1374 virtual Value *getSafeStackPointerLocation(IRBuilder<> &IRB) const;
1375
1376 /// Returns the name of the symbol used to emit stack probes or the empty
1377 /// string if not applicable.
1378 virtual StringRef getStackProbeSymbolName(MachineFunction &MF) const {
1379 return "";
1380 }
1381
1382 /// Returns true if a cast between SrcAS and DestAS is a noop.
1383 virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1384 return false;
1385 }
1386
1387 /// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
1388 /// are happy to sink it into basic blocks.
1389 virtual bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
1390 return isNoopAddrSpaceCast(SrcAS, DestAS);
1391 }
1392
1393 /// Return true if the pointer arguments to CI should be aligned by aligning
1394 /// the object whose address is being passed. If so then MinSize is set to the
1395 /// minimum size the object must be to be aligned and PrefAlign is set to the
1396 /// preferred alignment.
1397 virtual bool shouldAlignPointerArgs(CallInst * /*CI*/, unsigned & /*MinSize*/,
1398 unsigned & /*PrefAlign*/) const {
1399 return false;
1400 }
1401
1402 //===--------------------------------------------------------------------===//
1403 /// \name Helpers for TargetTransformInfo implementations
1404 /// @{
1405
1406 /// Get the ISD node that corresponds to the Instruction class opcode.
1407 int InstructionOpcodeToISD(unsigned Opcode) const;
1408
1409 /// Estimate the cost of type-legalization and the legalized type.
1410 std::pair getTypeLegalizationCost(const DataLayout &DL,
1411 Type *Ty) const;
1412
1413 /// @}
1414
1415 //===--------------------------------------------------------------------===//
1416 /// \name Helpers for atomic expansion.
1417 /// @{
1418
1419 /// Returns the maximum atomic operation size (in bits) supported by
1420 /// the backend. Atomic operations greater than this size (as well
1421 /// as ones that are not naturally aligned), will be expanded by
1422 /// AtomicExpandPass into an __atomic_* library call.
1423 unsigned getMaxAtomicSizeInBitsSupported() const {
1424 return MaxAtomicSizeInBitsSupported;
1425 }
1426
1427 /// Returns the size of the smallest cmpxchg or ll/sc instruction
1428 /// the backend supports. Any smaller operations are widened in
1429 /// AtomicExpandPass.
1430 ///
1431 /// Note that *unlike* operations above the maximum size, atomic ops
1432 /// are still natively supported below the minimum; they just
1433 /// require a more complex expansion.
1434 unsigned getMinCmpXchgSizeInBits() const { return MinCmpXchgSizeInBits; }
1435
1436 /// Whether AtomicExpandPass should automatically insert fences and reduce
1437 /// ordering for this atomic. This should be true for most architectures with
1438 /// weak memory ordering. Defaults to false.
1439 virtual bool shouldInsertFencesForAtomic(const Instruction *I) const {
1440 return false;
1441 }
1442
1443 /// Perform a load-linked operation on Addr, returning a "Value *" with the
1444 /// corresponding pointee type. This may entail some non-trivial operations to
1445 /// truncate or reconstruct types that will be illegal in the backend. See
1446 /// ARMISelLowering for an example implementation.
1447 virtual Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
1448 AtomicOrdering Ord) const {
1449 llvm_unreachable("Load linked unimplemented on this target");
1450 }
1451
1452 /// Perform a store-conditional operation to Addr. Return the status of the
1453 /// store. This should be 0 if the store succeeded, non-zero otherwise.
1454 virtual Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
1455 Value *Addr, AtomicOrdering Ord) const {
1456 llvm_unreachable("Store conditional unimplemented on this target");
1457 }
1458
1459 /// Inserts in the IR a target-specific intrinsic specifying a fence.
1460 /// It is called by AtomicExpandPass before expanding an
1461 /// AtomicRMW/AtomicCmpXchg/AtomicStore/AtomicLoad
1462 /// if shouldInsertFencesForAtomic returns true.
1463 ///
1464 /// Inst is the original atomic instruction, prior to other expansions that
1465 /// may be performed.
1466 ///
1467 /// This function should either return a nullptr, or a pointer to an IR-level
1468 /// Instruction*. Even complex fence sequences can be represented by a
1469 /// single Instruction* through an intrinsic to be lowered later.
1470 /// Backends should override this method to produce target-specific intrinsic
1471 /// for their fences.
1472 /// FIXME: Please note that the default implementation here in terms of
1473 /// IR-level fences exists for historical/compatibility reasons and is
1474 /// *unsound* ! Fences cannot, in general, be used to restore sequential
1475 /// consistency. For example, consider the following example:
1476 /// atomic x = y = 0;
1477 /// int r1, r2, r3, r4;
1478 /// Thread 0:
1479 /// x.store(1);
1480 /// Thread 1:
1481 /// y.store(1);
1482 /// Thread 2:
1483 /// r1 = x.load();
1484 /// r2 = y.load();
1485 /// Thread 3:
1486 /// r3 = y.load();
1487 /// r4 = x.load();
1488 /// r1 = r3 = 1 and r2 = r4 = 0 is impossible as long as the accesses are all
1489 /// seq_cst. But if they are lowered to monotonic accesses, no amount of
1490 /// IR-level fences can prevent it.
1491 /// @{
1492 virtual Instruction *emitLeadingFence(IRBuilder<> &Builder, Instruction *Inst,
1493 AtomicOrdering Ord) const {
1494 if (isReleaseOrStronger(Ord) && Inst->hasAtomicStore())
1495 return Builder.CreateFence(Ord);
1496 else
1497 return nullptr;
1498 }
1499
1500 virtual Instruction *emitTrailingFence(IRBuilder<> &Builder,
1501 Instruction *Inst,
1502 AtomicOrdering Ord) const {
1503 if (isAcquireOrStronger(Ord))
1504 return Builder.CreateFence(Ord);
1505 else
1506 return nullptr;
1507 }
1508 /// @}
1509
1510 // Emits code that executes when the comparison result in the ll/sc
1511 // expansion of a cmpxchg instruction is such that the store-conditional will
1512 // not execute. This makes it possible to balance out the load-linked with
1513 // a dedicated instruction, if desired.
1514 // E.g., on ARM, if ldrex isn't followed by strex, the exclusive monitor would
1515 // be unnecessarily held, except if clrex, inserted by this hook, is executed.
1516 virtual void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const {}
1517
1518 /// Returns true if the given (atomic) store should be expanded by the
1519 /// IR-level AtomicExpand pass into an "atomic xchg" which ignores its input.
1520 virtual bool shouldExpandAtomicStoreInIR(StoreInst *SI) const {
1521 return false;
1522 }
1523
1524 /// Returns true if arguments should be sign-extended in lib calls.
1525 virtual bool shouldSignExtendTypeInLibCall(EVT Type, bool IsSigned) const {
1526 return IsSigned;
1527 }
1528
1529 /// Returns how the given (atomic) load should be expanded by the
1530 /// IR-level AtomicExpand pass.
1531 virtual AtomicExpansionKind shouldExpandAtomicLoadInIR(LoadInst *LI) const {
1532 return AtomicExpansionKind::None;
1533 }
1534
1535 /// Returns true if the given atomic cmpxchg should be expanded by the
1536 /// IR-level AtomicExpand pass into a load-linked/store-conditional sequence
1537 /// (through emitLoadLinked() and emitStoreConditional()).
1538 virtual bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const {
1539 return false;
1540 }
1541
1542 /// Returns how the IR-level AtomicExpand pass should expand the given
1543 /// AtomicRMW, if at all. Default is to never expand.
1544 virtual AtomicExpansionKind shouldExpandAtomicRMWInIR(AtomicRMWInst *) const {
1545 return AtomicExpansionKind::None;
1546 }
1547
1548 /// On some platforms, an AtomicRMW that never actually modifies the value
1549 /// (such as fetch_add of 0) can be turned into a fence followed by an
1550 /// atomic load. This may sound useless, but it makes it possible for the
1551 /// processor to keep the cacheline shared, dramatically improving
1552 /// performance. And such idempotent RMWs are useful for implementing some
1553 /// kinds of locks, see for example (justification + benchmarks):
1554 /// http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
1555 /// This method tries doing that transformation, returning the atomic load if
1556 /// it succeeds, and nullptr otherwise.
1557 /// If shouldExpandAtomicLoadInIR returns true on that load, it will undergo
1558 /// another round of expansion.
1559 virtual LoadInst *
1560 lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *RMWI) const {
1561 return nullptr;
1562 }
1563
1564 /// Returns how the platform's atomic operations are extended (ZERO_EXTEND,
1565 /// SIGN_EXTEND, or ANY_EXTEND).
1566 virtual ISD::NodeType getExtendForAtomicOps() const {
1567 return ISD::ZERO_EXTEND;
1568 }
1569
1570 /// @}
1571
1572 /// Returns true if we should normalize
1573 /// select(N0&N1, X, Y) => select(N0, select(N1, X, Y), Y) and
1574 /// select(N0|N1, X, Y) => select(N0, select(N1, X, Y, Y)) if it is likely
1575 /// that it saves us from materializing N0 and N1 in an integer register.
1576 /// Targets that are able to perform and/or on flags should return false here.
1577 virtual bool shouldNormalizeToSelectSequence(LLVMContext &Context,
1578 EVT VT) const {
1579 // If a target has multiple condition registers, then it likely has logical
1580 // operations on those registers.
1581 if (hasMultipleConditionRegisters())
1582 return false;
1583 // Only do the transform if the value won't be split into multiple
1584 // registers.
1585 LegalizeTypeAction Action = getTypeAction(Context, VT);
1586 return Action != TypeExpandInteger && Action != TypeExpandFloat &&
1587 Action != TypeSplitVector;
1588 }
1589
1590 /// Return true if a select of constants (select Cond, C1, C2) should be
1591 /// transformed into simple math ops with the condition value. For example:
1592 /// select Cond, C1, C1-1 --> add (zext Cond), C1-1
1593 virtual bool convertSelectOfConstantsToMath(EVT VT) const {
1594 return false;
1595 }
1596
1597 //===--------------------------------------------------------------------===//
1598 // TargetLowering Configuration Methods - These methods should be invoked by
1599 // the derived class constructor to configure this object for the target.
1600 //
1601 protected:
1602 /// Specify how the target extends the result of integer and floating point
1603 /// boolean values from i1 to a wider type. See getBooleanContents.
1604 void setBooleanContents(BooleanContent Ty) {
1605 BooleanContents = Ty;
1606 BooleanFloatContents = Ty;
1607 }
1608
1609 /// Specify how the target extends the result of integer and floating point
1610 /// boolean values from i1 to a wider type. See getBooleanContents.
1611 void setBooleanContents(BooleanContent IntTy, BooleanContent FloatTy) {
1612 BooleanContents = IntTy;
1613 BooleanFloatContents = FloatTy;
1614 }
1615
1616 /// Specify how the target extends the result of a vector boolean value from a
1617 /// vector of i1 to a wider type. See getBooleanContents.
1618 void setBooleanVectorContents(BooleanContent Ty) {
1619 BooleanVectorContents = Ty;
1620 }
1621
1622 /// Specify the target scheduling preference.
1623 void setSchedulingPreference(Sched::Preference Pref) {
1624 SchedPreferenceInfo = Pref;
1625 }
1626
1627 /// Indicate whether this target prefers to use _setjmp to implement
1628 /// llvm.setjmp or the version without _. Defaults to false.
1629 void setUseUnderscoreSetJmp(bool Val) {
1630 UseUnderscoreSetJmp = Val;
1631 }
1632
1633 /// Indicate whether this target prefers to use _longjmp to implement
1634 /// llvm.longjmp or the version without _. Defaults to false.
1635 void setUseUnderscoreLongJmp(bool Val) {
1636 UseUnderscoreLongJmp = Val;
1637 }
1638
1639 /// Indicate the minimum number of blocks to generate jump tables.
1640 void setMinimumJumpTableEntries(unsigned Val);
1641
1642 /// Indicate the maximum number of entries in jump tables.
1643 /// Set to zero to generate unlimited jump tables.
1644 void setMaximumJumpTableSize(unsigned);
1645
1646 /// If set to a physical register, this specifies the register that
1647 /// llvm.savestack/llvm.restorestack should save and restore.
1648 void setStackPointerRegisterToSaveRestore(unsigned R) {
1649 StackPointerRegisterToSaveRestore = R;
1650 }
1651
1652 /// Tells the code generator that the target has multiple (allocatable)
1653 /// condition registers that can be used to store the results of comparisons
1654 /// for use by selects and conditional branches. With multiple condition
1655 /// registers, the code generator will not aggressively sink comparisons into
1656 /// the blocks of their users.
1657 void setHasMultipleConditionRegisters(bool hasManyRegs = true) {
1658 HasMultipleConditionRegisters = hasManyRegs;
1659 }
1660
1661 /// Tells the code generator that the target has BitExtract instructions.
1662 /// The code generator will aggressively sink "shift"s into the blocks of
1663 /// their users if the users will generate "and" instructions which can be
1664 /// combined with "shift" to BitExtract instructions.
1665 void setHasExtractBitsInsn(bool hasExtractInsn = true) {
1666 HasExtractBitsInsn = hasExtractInsn;
1667 }
1668
1669 /// Tells the code generator not to expand logic operations on comparison
1670 /// predicates into separate sequences that increase the amount of flow
1671 /// control.
1672 void setJumpIsExpensive(bool isExpensive = true);
1673
1674 /// Tells the code generator that this target supports floating point
1675 /// exceptions and cares about preserving floating point exception behavior.
1676 void setHasFloatingPointExceptions(bool FPExceptions = true) {
1677 HasFloatingPointExceptions = FPExceptions;
1678 }
1679
1680 /// Tells the code generator which bitwidths to bypass.
1681 void addBypassSlowDiv(unsigned int SlowBitWidth, unsigned int FastBitWidth) {
1682 BypassSlowDivWidths[SlowBitWidth] = FastBitWidth;
1683 }
1684
1685 /// Add the specified register class as an available regclass for the
1686 /// specified value type. This indicates the selector can handle values of
1687 /// that class natively.
1688 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
1689 assert((unsigned)VT.SimpleTy < array_lengthof(RegClassForVT));
1690 RegClassForVT[VT.SimpleTy] = RC;
1691 }
1692
1693 /// Return the largest legal super-reg register class of the register class
1694 /// for the specified type and its associated "cost".
1695 virtual std::pair
1696 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
1697
1698 /// Once all of the register classes are added, this allows us to compute
1699 /// derived properties we expose.
1700 void computeRegisterProperties(const TargetRegisterInfo *TRI);
1701
1702 /// Indicate that the specified operation does not work with the specified
1703 /// type and indicate what to do about it. Note that VT may refer to either
1704 /// the type of a result or that of an operand of Op.
1705 void setOperationAction(unsigned Op, MVT VT,
1706 LegalizeAction Action) {
1707 assert(Op < array_lengthof(OpActions[0]) && "Table isn't big enough!");
1708 OpActions[(unsigned)VT.SimpleTy][Op] = Action;
1709 }
1710
1711 /// Indicate that the specified load with extension does not work with the
1712 /// specified type and indicate what to do about it.
1713 void setLoadExtAction(unsigned ExtType, MVT ValVT, MVT MemVT,
1714 LegalizeAction Action) {
1715 assert(ExtType < ISD::LAST_LOADEXT_TYPE && ValVT.isValid() &&
1716 MemVT.isValid() && "Table isn't big enough!");
1717 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1718 unsigned Shift = 4 * ExtType;
1719 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] &= ~((uint16_t)0xF << Shift);
1720 LoadExtActions[ValVT.SimpleTy][MemVT.SimpleTy] |= (uint16_t)Action << Shift;
1721 }
1722
1723 /// Indicate that the specified truncating store does not work with the
1724 /// specified type and indicate what to do about it.
1725 void setTruncStoreAction(MVT ValVT, MVT MemVT,
1726 LegalizeAction Action) {
1727 assert(ValVT.isValid() && MemVT.isValid() && "Table isn't big enough!");
1728 TruncStoreActions[(unsigned)ValVT.SimpleTy][MemVT.SimpleTy] = Action;
1729 }
1730
1731 /// Indicate that the specified indexed load does or does not work with the
1732 /// specified type and indicate what to do abort it.
1733 ///
1734 /// NOTE: All indexed mode loads are initialized to Expand in
1735 /// TargetLowering.cpp
1736 void setIndexedLoadAction(unsigned IdxMode, MVT VT,
1737 LegalizeAction Action) {
1738 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1739 (unsigned)Action < 0xf && "Table isn't big enough!");
1740 // Load action are kept in the upper half.
1741 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0xf0;
1742 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action) <<4;
1743 }
1744
1745 /// Indicate that the specified indexed store does or does not work with the
1746 /// specified type and indicate what to do about it.
1747 ///
1748 /// NOTE: All indexed mode stores are initialized to Expand in
1749 /// TargetLowering.cpp
1750 void setIndexedStoreAction(unsigned IdxMode, MVT VT,
1751 LegalizeAction Action) {
1752 assert(VT.isValid() && IdxMode < ISD::LAST_INDEXED_MODE &&
1753 (unsigned)Action < 0xf && "Table isn't big enough!");
1754 // Store action are kept in the lower half.
1755 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] &= ~0x0f;
1756 IndexedModeActions[(unsigned)VT.SimpleTy][IdxMode] |= ((uint8_t)Action);
1757 }
1758
1759 /// Indicate that the specified condition code is or isn't supported on the
1760 /// target and indicate what to do about it.
1761 void setCondCodeAction(ISD::CondCode CC, MVT VT,
1762 LegalizeAction Action) {
1763 assert(VT.isValid() && (unsigned)CC < array_lengthof(CondCodeActions) &&
1764 "Table isn't big enough!");
1765 assert((unsigned)Action < 0x10 && "too many bits for bitfield array");
1766 /// The lower 3 bits of the SimpleTy index into Nth 4bit set from the 32-bit
1767 /// value and the upper 29 bits index into the second dimension of the array
1768 /// to select what 32-bit value to use.
1769 uint32_t Shift = 4 * (VT.SimpleTy & 0x7);
1770 CondCodeActions[CC][VT.SimpleTy >> 3] &= ~((uint32_t)0xF << Shift);
1771 CondCodeActions[CC][VT.SimpleTy >> 3] |= (uint32_t)Action << Shift;
1772 }
1773
1774 /// If Opc/OrigVT is specified as being promoted, the promotion code defaults
1775 /// to trying a larger integer/fp until it can find one that works. If that
1776 /// default is insufficient, this method can be used by the target to override
1777 /// the default.
1778 void AddPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1779 PromoteToType[std::make_pair(Opc, OrigVT.SimpleTy)] = DestVT.SimpleTy;
1780 }
1781
1782 /// Convenience method to set an operation to Promote and specify the type
1783 /// in a single call.
1784 void setOperationPromotedToType(unsigned Opc, MVT OrigVT, MVT DestVT) {
1785 setOperationAction(Opc, OrigVT, Promote);
1786 AddPromotedToType(Opc, OrigVT, DestVT);
1787 }
1788
1789 /// Targets should invoke this method for each target independent node that
1790 /// they want to provide a custom DAG combiner for by implementing the
1791 /// PerformDAGCombine virtual method.
1792 void setTargetDAGCombine(ISD::NodeType NT) {
1793 assert(unsigned(NT >> 3) < array_lengthof(TargetDAGCombineArray));
1794 TargetDAGCombineArray[NT >> 3] |= 1 << (NT&7);
1795 }
1796
1797 /// Set the target's required jmp_buf buffer size (in bytes); default is 200
1798 void setJumpBufSize(unsigned Size) {
1799 JumpBufSize = Size;
1800 }
1801
1802 /// Set the target's required jmp_buf buffer alignment (in bytes); default is
1803 /// 0
1804 void setJumpBufAlignment(unsigned Align) {
1805 JumpBufAlignment = Align;
1806 }
1807
1808 /// Set the target's minimum function alignment (in log2(bytes))
1809 void setMinFunctionAlignment(unsigned Align) {
1810 MinFunctionAlignment = Align;
1811 }
1812
1813 /// Set the target's preferred function alignment. This should be set if
1814 /// there is a performance benefit to higher-than-minimum alignment (in
1815 /// log2(bytes))
1816 void setPrefFunctionAlignment(unsigned Align) {
1817 PrefFunctionAlignment = Align;
1818 }
1819
1820 /// Set the target's preferred loop alignment. Default alignment is zero, it
1821 /// means the target does not care about loop alignment. The alignment is
1822 /// specified in log2(bytes). The target may also override
1823 /// getPrefLoopAlignment to provide per-loop values.
1824 void setPrefLoopAlignment(unsigned Align) {
1825 PrefLoopAlignment = Align;
1826 }
1827
1828 /// Set the minimum stack alignment of an argument (in log2(bytes)).
1829 void setMinStackArgumentAlignment(unsigned Align) {
1830 MinStackArgumentAlignment = Align;
1831 }
1832
1833 /// Set the maximum atomic operation size supported by the
1834 /// backend. Atomic operations greater than this size (as well as
1835 /// ones that are not naturally aligned), will be expanded by
1836 /// AtomicExpandPass into an __atomic_* library call.
1837 void setMaxAtomicSizeInBitsSupported(unsigned SizeInBits) {
1838 MaxAtomicSizeInBitsSupported = SizeInBits;
1839 }
1840
1841 // Sets the minimum cmpxchg or ll/sc size supported by the backend.
1842 void setMinCmpXchgSizeInBits(unsigned SizeInBits) {
1843 MinCmpXchgSizeInBits = SizeInBits;
1844 }
1845
1846 public:
1847 //===--------------------------------------------------------------------===//
1848 // Addressing mode description hooks (used by LSR etc).
1849 //
1850
1851 /// CodeGenPrepare sinks address calculations into the same BB as Load/Store
1852 /// instructions reading the address. This allows as much computation as
1853 /// possible to be done in the address mode for that operand. This hook lets
1854 /// targets also pass back when this should be done on intrinsics which
1855 /// load/store.
1856 virtual bool getAddrModeArguments(IntrinsicInst * /*I*/,
1857 SmallVectorImpl &/*Ops*/,
1858 Type *&/*AccessTy*/) const {
1859 return false;
1860 }
1861
1862 /// This represents an addressing mode of:
1863 /// BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
1864 /// If BaseGV is null, there is no BaseGV.
1865 /// If BaseOffs is zero, there is no base offset.
1866 /// If HasBaseReg is false, there is no base register.
1867 /// If Scale is zero, there is no ScaleReg. Scale of 1 indicates a reg with
1868 /// no scale.
1869 struct AddrMode {
1870 GlobalValue *BaseGV = nullptr;
1871 int64_t BaseOffs = 0;
1872 bool HasBaseReg = false;
1873 int64_t Scale = 0;
1874 AddrMode() = default;
1875 };
1876
1877 /// Return true if the addressing mode represented by AM is legal for this
1878 /// target, for a load/store of the specified type.
1879 ///
1880 /// The type may be VoidTy, in which case only return true if the addressing
1881 /// mode is legal for a load/store of any legal type. TODO: Handle
1882 /// pre/postinc as well.
1883 ///
1884 /// If the address space cannot be determined, it will be -1.
1885 ///
1886 /// TODO: Remove default argument
1887 virtual bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
1888 Type *Ty, unsigned AddrSpace,
1889 Instruction *I = nullptr) const;
1890
1891 /// \brief Return the cost of the scaling factor used in the addressing mode
1892 /// represented by AM for this target, for a load/store of the specified type.
1893 ///
1894 /// If the AM is supported, the return value must be >= 0.
1895 /// If the AM is not supported, it returns a negative value.
1896 /// TODO: Handle pre/postinc as well.
1897 /// TODO: Remove default argument
1898 virtual int getScalingFactorCost(const DataLayout &DL, const AddrMode &AM,
1899 Type *Ty, unsigned AS = 0) const {
1900 // Default: assume that any scaling factor used in a legal AM is free.
1901 if (isLegalAddressingMode(DL, AM, Ty, AS))
1902 return 0;
1903 return -1;
1904 }
1905
1906 /// Return true if the specified immediate is legal icmp immediate, that is
1907 /// the target has icmp instructions which can compare a register against the
1908 /// immediate without having to materialize the immediate into a register.
1909 virtual bool isLegalICmpImmediate(int64_t) const {
1910 return true;
1911 }
1912
1913 /// Return true if the specified immediate is legal add immediate, that is the
1914 /// target has add instructions which can add a register with the immediate
1915 /// without having to materialize the immediate into a register.
1916 virtual bool isLegalAddImmediate(int64_t) const {
1917 return true;
1918 }
1919
1920 /// Return true if it's significantly cheaper to shift a vector by a uniform
1921 /// scalar than by an amount which will vary across each lane. On x86, for
1922 /// example, there is a "psllw" instruction for the former case, but no simple
1923 /// instruction for a general "a << b" operation on vectors.
1924 virtual bool isVectorShiftByScalarCheap(Type *Ty) const {
1925 return false;
1926 }
1927
1928 /// Returns true if the opcode is a commutative binary operation.
1929 virtual bool isCommutativeBinOp(unsigned Opcode) const {
1930 // FIXME: This should get its info from the td file.
1931 switch (Opcode) {
1932 case ISD::ADD:
1933 case ISD::SMIN:
1934 case ISD::SMAX:
1935 case ISD::UMIN:
1936 case ISD::UMAX:
1937 case ISD::MUL:
1938 case ISD::MULHU:
1939 case ISD::MULHS:
1940 case ISD::SMUL_LOHI:
1941 case ISD::UMUL_LOHI:
1942 case ISD::FADD:
1943 case ISD::FMUL:
1944 case ISD::AND:
1945 case ISD::OR:
1946 case ISD::XOR:
1947 case ISD::SADDO:
1948 case ISD::UADDO:
1949 case ISD::ADDC:
1950 case ISD::ADDE:
1951 case ISD::FMINNUM:
1952 case ISD::FMAXNUM:
1953 case ISD::FMINNAN:
1954 case ISD::FMAXNAN:
1955 return true;
1956 default: return false;
1957 }
1958 }
1959
1960 /// Return true if it's free to truncate a value of type FromTy to type
1961 /// ToTy. e.g. On x86 it's free to truncate a i32 value in register EAX to i16
1962 /// by referencing its sub-register AX.
1963 /// Targets must return false when FromTy <= ToTy.
1964 virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const {
1965 return false;
1966 }
1967
1968 /// Return true if a truncation from FromTy to ToTy is permitted when deciding
1969 /// whether a call is in tail position. Typically this means that both results
1970 /// would be assigned to the same register or stack slot, but it could mean
1971 /// the target performs adequate checks of its own before proceeding with the
1972 /// tail call. Targets must return false when FromTy <= ToTy.
1973 virtual bool allowTruncateForTailCall(Type *FromTy, Type *ToTy) const {
1974 return false;
1975 }
1976
1977 virtual bool isTruncateFree(EVT FromVT, EVT ToVT) const {
1978 return false;
1979 }
1980
1981 virtual bool isProfitableToHoist(Instruction *I) const { return true; }
1982
1983 /// Return true if the extension represented by \p I is free.
1984 /// Unlikely the is[Z|FP]ExtFree family which is based on types,
1985 /// this method can use the context provided by \p I to decide
1986 /// whether or not \p I is free.
1987 /// This method extends the behavior of the is[Z|FP]ExtFree family.
1988 /// In other words, if is[Z|FP]Free returns true, then this method
1989 /// returns true as well. The converse is not true.
1990 /// The target can perform the adequate checks by overriding isExtFreeImpl.
1991 /// \pre \p I must be a sign, zero, or fp extension.
1992 bool isExtFree(const Instruction *I) const {
1993 switch (I->getOpcode()) {
1994 case Instruction::FPExt:
1995 if (isFPExtFree(EVT::getEVT(I->getType()),
1996 EVT::getEVT(I->getOperand(0)->getType())))
1997 return true;
1998 break;
1999 case Instruction::ZExt:
2000 if (isZExtFree(I->getOperand(0)->getType(), I->getType()))
2001 return true;
2002 break;
2003 case Instruction::SExt:
2004 break;
2005 default:
2006 llvm_unreachable("Instruction is not an extension");
2007 }
2008 return isExtFreeImpl(I);
2009 }
2010
2011 /// Return true if \p Load and \p Ext can form an ExtLoad.
2012 /// For example, in AArch64
2013 /// %L = load i8, i8* %ptr
2014 /// %E = zext i8 %L to i32
2015 /// can be lowered into one load instruction
2016 /// ldrb w0, [x0]
2017 bool isExtLoad(const LoadInst *Load, const Instruction *Ext,
2018 const DataLayout &DL) const {
2019 EVT VT = getValueType(DL, Ext->getType());
2020 EVT LoadVT = getValueType(DL, Load->getType());
2021
2022 // If the load has other users and the truncate is not free, the ext
2023 // probably isn't free.
2024 if (!Load->hasOneUse() && (isTypeLegal(LoadVT) || !isTypeLegal(VT)) &&
2025 !isTruncateFree(Ext->getType(), Load->getType()))
2026 return false;
2027
2028 // Check whether the target supports casts folded into loads.
2029 unsigned LType;
2030 if (isa(Ext))
2031 LType = ISD::ZEXTLOAD;
2032 else {
2033 assert(isa(Ext) && "Unexpected ext type!");
2034 LType = ISD::SEXTLOAD;
2035 }
2036
2037 return isLoadExtLegal(LType, VT, LoadVT);
2038 }
2039
2040 /// Return true if any actual instruction that defines a value of type FromTy
2041 /// implicitly zero-extends the value to ToTy in the result register.
2042 ///
2043 /// The function should return true when it is likely that the truncate can
2044 /// be freely folded with an instruction defining a value of FromTy. If
2045 /// the defining instruction is unknown (because you're looking at a
2046 /// function argument, PHI, etc.) then the target may require an
2047 /// explicit truncate, which is not necessarily free, but this function
2048 /// does not deal with those cases.
2049 /// Targets must return false when FromTy >= ToTy.
2050 virtual bool isZExtFree(Type *FromTy, Type *ToTy) const {
2051 return false;
2052 }
2053
2054 virtual bool isZExtFree(EVT FromTy, EVT ToTy) const {
2055 return false;
2056 }
2057
2058 /// Return true if the target supplies and combines to a paired load
2059 /// two loaded values of type LoadedType next to each other in memory.
2060 /// RequiredAlignment gives the minimal alignment constraints that must be met
2061 /// to be able to select this paired load.
2062 ///
2063 /// This information is *not* used to generate actual paired loads, but it is
2064 /// used to generate a sequence of loads that is easier to combine into a
2065 /// paired load.
2066 /// For instance, something like this:
2067 /// a = load i64* addr
2068 /// b = trunc i64 a to i32
2069 /// c = lshr i64 a, 32
2070 /// d = trunc i64 c to i32
2071 /// will be optimized into:
2072 /// b = load i32* addr1
2073 /// d = load i32* addr2
2074 /// Where addr1 = addr2 +/- sizeof(i32).
2075 ///
2076 /// In other words, unless the target performs a post-isel load combining,
2077 /// this information should not be provided because it will generate more
2078 /// loads.
2079 virtual bool hasPairedLoad(EVT /*LoadedType*/,
2080 unsigned & /*RequiredAlignment*/) const {
2081 return false;
2082 }
2083
2084 /// \brief Get the maximum supported factor for interleaved memory accesses.
2085 /// Default to be the minimum interleave factor: 2.
2086 virtual unsigned getMaxSupportedInterleaveFactor() const { return 2; }
2087
2088 /// \brief Lower an interleaved load to target specific intrinsics. Return
2089 /// true on success.
2090 ///
2091 /// \p LI is the vector load instruction.
2092 /// \p Shuffles is the shufflevector list to DE-interleave the loaded vector.
2093 /// \p Indices is the corresponding indices for each shufflevector.
2094 /// \p Factor is the interleave factor.
2095 virtual bool lowerInterleavedLoad(LoadInst *LI,
2096 ArrayRef Shuffles,
2097 ArrayRef Indices,
2098 unsigned Factor) const {
2099 return false;
2100 }
2101
2102 /// \brief Lower an interleaved store to target specific intrinsics. Return
2103 /// true on success.
2104 ///
2105 /// \p SI is the vector store instruction.
2106 /// \p SVI is the shufflevector to RE-interleave the stored vector.
2107 /// \p Factor is the interleave factor.
2108 virtual bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
2109 unsigned Factor) const {
2110 return false;
2111 }
2112
2113 /// Return true if zero-extending the specific node Val to type VT2 is free
2114 /// (either because it's implicitly zero-extended such as ARM ldrb / ldrh or
2115 /// because it's folded such as X86 zero-extending loads).
2116 virtual bool isZExtFree(SDValue Val, EVT VT2) const {
2117 return isZExtFree(Val.getValueType(), VT2);
2118 }
2119
2120 /// Return true if an fpext operation is free (for instance, because
2121 /// single-precision floating-point numbers are implicitly extended to
2122 /// double-precision).
2123 virtual bool isFPExtFree(EVT DestVT, EVT SrcVT) const {
2124 assert(SrcVT.isFloatingPoint() && DestVT.isFloatingPoint() &&
2125 "invalid fpext types");
2126 return false;
2127 }
2128
2129 /// Return true if an fpext operation input to an \p Opcode operation is free
2130 /// (for instance, because half-precision floating-point numbers are
2131 /// implicitly extended to float-precision) for an FMA instruction.
2132 virtual bool isFPExtFoldable(unsigned Opcode, EVT DestVT, EVT SrcVT) const {
2133 assert(DestVT.isFloatingPoint() && SrcVT.isFloatingPoint() &&
2134 "invalid fpext types");
2135 return isFPExtFree(DestVT, SrcVT);
2136 }
2137
2138 /// Return true if folding a vector load into ExtVal (a sign, zero, or any
2139 /// extend node) is profitable.
2140 virtual bool isVectorLoadExtDesirable(SDValue ExtVal) const { return false; }
2141
2142 /// Return true if an fneg operation is free to the point where it is never
2143 /// worthwhile to replace it with a bitwise operation.
2144 virtual bool isFNegFree(EVT VT) const {
2145 assert(VT.isFloatingPoint());
2146 return false;
2147 }
2148
2149 /// Return true if an fabs operation is free to the point where it is never
2150 /// worthwhile to replace it with a bitwise operation.
2151 virtual bool isFAbsFree(EVT VT) const {
2152 assert(VT.isFloatingPoint());
2153 return false;
2154 }
2155
2156 /// Return true if an FMA operation is faster than a pair of fmul and fadd
2157 /// instructions. fmuladd intrinsics will be expanded to FMAs when this method
2158 /// returns true, otherwise fmuladd is expanded to fmul + fadd.
2159 ///
2160 /// NOTE: This may be called before legalization on types for which FMAs are
2161 /// not legal, but should return true if those types will eventually legalize
2162 /// to types that support FMAs. After legalization, it will only be called on
2163 /// types that support FMAs (via Legal or Custom actions)
2164 virtual bool isFMAFasterThanFMulAndFAdd(EVT) const {
2165 return false;
2166 }
2167
2168 /// Return true if it's profitable to narrow operations of type VT1 to
2169 /// VT2. e.g. on x86, it's profitable to narrow from i32 to i8 but not from
2170 /// i32 to i16.
2171 virtual bool isNarrowingProfitable(EVT /*VT1*/, EVT /*VT2*/) const {
2172 return false;
2173 }
2174
2175 /// \brief Return true if it is beneficial to convert a load of a constant to
2176 /// just the constant itself.
2177 /// On some targets it might be more efficient to use a combination of
2178 /// arithmetic instructions to materialize the constant instead of loading it
2179 /// from a constant pool.
2180 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
2181 Type *Ty) const {
2182 return false;
2183 }
2184
2185 /// Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type
2186 /// from this source type with this index. This is needed because
2187 /// EXTRACT_SUBVECTOR usually has custom lowering that depends on the index of
2188 /// the first element, and only the target knows which lowering is cheap.
2189 virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT,
2190 unsigned Index) const {
2191 return false;
2192 }
2193
2194 // Return true if it is profitable to use a scalar input to a BUILD_VECTOR
2195 // even if the vector itself has multiple uses.
2196 virtual bool aggressivelyPreferBuildVectorSources(EVT VecVT) const {
2197 return false;
2198 }
2199
2200 //===--------------------------------------------------------------------===//
2201 // Runtime Library hooks
2202 //
2203
2204 /// Rename the default libcall routine name for the specified libcall.
2205 void setLibcallName(RTLIB::Libcall Call, const char *Name) {
2206 LibcallRoutineNames[Call] = Name;
2207 }
2208
2209 /// Get the libcall routine name for the specified libcall.
2210 const char *getLibcallName(RTLIB::Libcall Call) const {
2211 return LibcallRoutineNames[Call];
2212 }
2213
2214 /// Override the default CondCode to be used to test the result of the
2215 /// comparison libcall against zero.
2216 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) {
2217 CmpLibcallCCs[Call] = CC;
2218 }
2219
2220 /// Get the CondCode that's to be used to test the result of the comparison
2221 /// libcall against zero.
2222 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const {
2223 return CmpLibcallCCs[Call];
2224 }
2225
2226 /// Set the CallingConv that should be used for the specified libcall.
2227 void setLibcallCallingConv(RTLIB::Libcall Call, CallingConv::ID CC) {
2228 LibcallCallingConvs[Call] = CC;
2229 }
2230
2231 /// Get the CallingConv that should be used for the specified libcall.
2232 CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const {
2233 return LibcallCallingConvs[Call];
2234 }
2235
2236 /// Execute target specific actions to finalize target lowering.
2237 /// This is used to set extra flags in MachineFrameInformation and freezing
2238 /// the set of reserved registers.
2239 /// The default implementation just freezes the set of reserved registers.
2240 virtual void finalizeLowering(MachineFunction &MF) const;
2241
2242 private:
2243 const TargetMachine &TM;
2244
2245 /// Tells the code generator that the target has multiple (allocatable)
2246 /// condition registers that can be used to store the results of comparisons
2247 /// for use by selects and conditional branches. With multiple condition
2248 /// registers, the code generator will not aggressively sink comparisons into
2249 /// the blocks of their users.
2250 bool HasMultipleConditionRegisters;
2251
2252 /// Tells the code generator that the target has BitExtract instructions.
2253 /// The code generator will aggressively sink "shift"s into the blocks of
2254 /// their users if the users will generate "and" instructions which can be
2255 /// combined with "shift" to BitExtract instructions.
2256 bool HasExtractBitsInsn;
2257
2258 /// Tells the code generator to bypass slow divide or remainder
2259 /// instructions. For example, BypassSlowDivWidths[32,8] tells the code
2260 /// generator to bypass 32-bit integer div/rem with an 8-bit unsigned integer
2261 /// div/rem when the operands are positive and less than 256.
2262 DenseMap BypassSlowDivWidths;
2263
2264 /// Tells the code generator that it shouldn't generate extra flow control
2265 /// instructions and should attempt to combine flow control instructions via
2266 /// predication.
2267 bool JumpIsExpensive;
2268
2269 /// Whether the target supports or cares about preserving floating point
2270 /// exception behavior.
2271 bool HasFloatingPointExceptions;
2272
2273 /// This target prefers to use _setjmp to implement llvm.setjmp.
2274 ///
2275 /// Defaults to false.
2276 bool UseUnderscoreSetJmp;
2277
2278 /// This target prefers to use _longjmp to implement llvm.longjmp.
2279 ///
2280 /// Defaults to false.
2281 bool UseUnderscoreLongJmp;
2282
2283 /// Information about the contents of the high-bits in boolean values held in
2284 /// a type wider than i1. See getBooleanContents.
2285 BooleanContent BooleanContents;
2286
2287 /// Information about the contents of the high-bits in boolean values held in
2288 /// a type wider than i1. See getBooleanContents.
2289 BooleanContent BooleanFloatContents;
2290
2291 /// Information about the contents of the high-bits in boolean vector values
2292 /// when the element type is wider than i1. See getBooleanContents.
2293 BooleanContent BooleanVectorContents;
2294
2295 /// The target scheduling preference: shortest possible total cycles or lowest
2296 /// register usage.
2297 Sched::Preference SchedPreferenceInfo;
2298
2299 /// The size, in bytes, of the target's jmp_buf buffers
2300 unsigned JumpBufSize;
2301
2302 /// The alignment, in bytes, of the target's jmp_buf buffers
2303 unsigned JumpBufAlignment;
2304
2305 /// The minimum alignment that any argument on the stack needs to have.
2306 unsigned MinStackArgumentAlignment;
2307
2308 /// The minimum function alignment (used when optimizing for size, and to
2309 /// prevent explicitly provided alignment from leading to incorrect code).
2310 unsigned MinFunctionAlignment;
2311
2312 /// The preferred function alignment (used when alignment unspecified and
2313 /// optimizing for speed).
2314 unsigned PrefFunctionAlignment;
2315
2316 /// The preferred loop alignment.
2317 unsigned PrefLoopAlignment;
2318
2319 /// Size in bits of the maximum atomics size the backend supports.
2320 /// Accesses larger than this will be expanded by AtomicExpandPass.
2321 unsigned MaxAtomicSizeInBitsSupported;
2322
2323 /// Size in bits of the minimum cmpxchg or ll/sc operation the
2324 /// backend supports.
2325 unsigned MinCmpXchgSizeInBits;
2326
2327 /// If set to a physical register, this specifies the register that
2328 /// llvm.savestack/llvm.restorestack should save and restore.
2329 unsigned StackPointerRegisterToSaveRestore;
2330
2331 /// This indicates the default register class to use for each ValueType the
2332 /// target supports natively.
2333 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2334 unsigned char NumRegistersForVT[MVT::LAST_VALUETYPE];
2335 MVT RegisterTypeForVT[MVT::LAST_VALUETYPE];
2336
2337 /// This indicates the "representative" register class to use for each
2338 /// ValueType the target supports natively. This information is used by the
2339 /// scheduler to track register pressure. By default, the representative
2340 /// register class is the largest legal super-reg register class of the
2341 /// register class of the specified type. e.g. On x86, i8, i16, and i32's
2342 /// representative class would be GR32.
2343 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2344
2345 /// This indicates the "cost" of the "representative" register class for each
2346 /// ValueType. The cost is used by the scheduler to approximate register
2347 /// pressure.
2348 uint8_t RepRegClassCostForVT[MVT::LAST_VALUETYPE];
2349
2350 /// For any value types we are promoting or expanding, this contains the value
2351 /// type that we are changing to. For Expanded types, this contains one step
2352 /// of the expand (e.g. i64 -> i32), even if there are multiple steps required
2353 /// (e.g. i64 -> i16). For types natively supported by the system, this holds
2354 /// the same type (e.g. i32 -> i32).
2355 MVT TransformToType[MVT::LAST_VALUETYPE];
2356
2357 /// For each operation and each value type, keep a LegalizeAction that
2358 /// indicates how instruction selection should deal with the operation. Most
2359 /// operations are Legal (aka, supported natively by the target), but
2360 /// operations that are not should be described. Note that operations on
2361 /// non-legal value types are not described here.
2362 LegalizeAction OpActions[MVT::LAST_VALUETYPE][ISD::BUILTIN_OP_END];
2363
2364 /// For each load extension type and each value type, keep a LegalizeAction
2365 /// that indicates how instruction selection should deal with a load of a
2366 /// specific value type and extension type. Uses 4-bits to store the action
2367 /// for each of the 4 load ext types.
2368 uint16_t LoadExtActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2369
2370 /// For each value type pair keep a LegalizeAction that indicates whether a
2371 /// truncating store of a specific value type and truncating type is legal.
2372 LegalizeAction TruncStoreActions[MVT::LAST_VALUETYPE][MVT::LAST_VALUETYPE];
2373
2374 /// For each indexed mode and each value type, keep a pair of LegalizeAction
2375 /// that indicates how instruction selection should deal with the load /
2376 /// store.
2377 ///
2378 /// The first dimension is the value_type for the reference. The second
2379 /// dimension represents the various modes for load store.
2380 uint8_t IndexedModeActions[MVT::LAST_VALUETYPE][ISD::LAST_INDEXED_MODE];
2381
2382 /// For each condition code (ISD::CondCode) keep a LegalizeAction that
2383 /// indicates how instruction selection should deal with the condition code.
2384 ///
2385 /// Because each CC action takes up 4 bits, we need to have the array size be
2386 /// large enough to fit all of the value types. This can be done by rounding
2387 /// up the MVT::LAST_VALUETYPE value to the next multiple of 8.
2388 uint32_t CondCodeActions[ISD::SETCC_INVALID][(MVT::LAST_VALUETYPE + 7) / 8];
2389
2390 protected:
2391 ValueTypeActionImpl ValueTypeActions;
2392
2393 private:
2394 LegalizeKind getTypeConversion(LLVMContext &Context, EVT VT) const;
2395
2396 /// Targets can specify ISD nodes that they would like PerformDAGCombine
2397 /// callbacks for by calling setTargetDAGCombine(), which sets a bit in this
2398 /// array.
2399 unsigned char
2400 TargetDAGCombineArray[(ISD::BUILTIN_OP_END+CHAR_BIT-1)/CHAR_BIT];
2401
2402 /// For operations that must be promoted to a specific type, this holds the
2403 /// destination type. This map should be sparse, so don't hold it as an
2404 /// array.
2405 ///
2406 /// Targets add entries to this map with AddPromotedToType(..), clients access
2407 /// this with getTypeToPromoteTo(..).
2408 std::map, MVT::SimpleValueType>
2409 PromoteToType;
2410
2411 /// Stores the name each libcall.
2412 const char *LibcallRoutineNames[RTLIB::UNKNOWN_LIBCALL];
2413
2414 /// The ISD::CondCode that should be used to test the result of each of the
2415 /// comparison libcall against zero.
2416 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
2417
2418 /// Stores the CallingConv that should be used for each libcall.
2419 CallingConv::ID LibcallCallingConvs[RTLIB::UNKNOWN_LIBCALL];
2420
2421 protected:
2422 /// Return true if the extension represented by \p I is free.
2423 /// \pre \p I is a sign, zero, or fp extension and
2424 /// is[Z|FP]ExtFree of the related types is not true.
2425 virtual bool isExtFreeImpl(const Instruction *I) const { return false; }
2426
2427 /// Depth that GatherAllAliases should should continue looking for chain
2428 /// dependencies when trying to find a more preferable chain. As an
2429 /// approximation, this should be more than the number of consecutive stores
2430 /// expected to be merged.
2431 unsigned GatherAllAliasesMaxDepth;
2432
2433 /// \brief Specify maximum number of store instructions per memset call.
2434 ///
2435 /// When lowering \@llvm.memset this field specifies the maximum number of
2436 /// store operations that may be substituted for the call to memset. Targets
2437 /// must set this value based on the cost threshold for that target. Targets
2438 /// should assume that the memset will be done using as many of the largest
2439 /// store operations first, followed by smaller ones, if necessary, per
2440 /// alignment restrictions. For example, storing 9 bytes on a 32-bit machine
2441 /// with 16-bit alignment would result in four 2-byte stores and one 1-byte
2442 /// store. This only applies to setting a constant array of a constant size.
2443 unsigned MaxStoresPerMemset;
2444
2445 /// Maximum number of stores operations that may be substituted for the call
2446 /// to memset, used for functions with OptSize attribute.
2447 unsigned MaxStoresPerMemsetOptSize;
2448
2449 /// \brief Specify maximum bytes of store instructions per memcpy call.
2450 ///
2451 /// When lowering \@llvm.memcpy this field specifies the maximum number of
2452 /// store operations that may be substituted for a call to memcpy. Targets
2453 /// must set this value based on the cost threshold for that target. Targets
2454 /// should assume that the memcpy will be done using as many of the largest
2455 /// store operations first, followed by smaller ones, if necessary, per
2456 /// alignment restrictions. For example, storing 7 bytes on a 32-bit machine
2457 /// with 32-bit alignment would result in one 4-byte store, a one 2-byte store
2458 /// and one 1-byte store. This only applies to copying a constant array of
2459 /// constant size.
2460 unsigned MaxStoresPerMemcpy;
2461
2462 /// Maximum number of store operations that may be substituted for a call to
2463 /// memcpy, used for functions with OptSize attribute.
2464 unsigned MaxStoresPerMemcpyOptSize;
2465 unsigned MaxLoadsPerMemcmp;
2466 unsigned MaxLoadsPerMemcmpOptSize;
2467
2468 /// \brief Specify maximum bytes of store instructions per memmove call.
2469 ///
2470 /// When lowering \@llvm.memmove this field specifies the maximum number of
2471 /// store instructions that may be substituted for a call to memmove. Targets
2472 /// must set this value based on the cost threshold for that target. Targets
2473 /// should assume that the memmove will be done using as many of the largest
2474 /// store operations first, followed by smaller ones, if necessary, per
2475 /// alignment restrictions. For example, moving 9 bytes on a 32-bit machine
2476 /// with 8-bit alignment would result in nine 1-byte stores. This only
2477 /// applies to copying a constant array of constant size.
2478 unsigned MaxStoresPerMemmove;
2479
2480 /// Maximum number of store instructions that may be substituted for a call to
2481 /// memmove, used for functions with OptSize attribute.
2482 unsigned MaxStoresPerMemmoveOptSize;
2483
2484 /// Tells the code generator that select is more expensive than a branch if
2485 /// the branch is usually predicted right.
2486 bool PredictableSelectIsExpensive;
2487
2488 /// \see enableExtLdPromotion.
2489 bool EnableExtLdPromotion;
2490
2491 /// Return true if the value types that can be represented by the specified
2492 /// register class are all legal.
2493 bool isLegalRC(const TargetRegisterInfo &TRI,
2494 const TargetRegisterClass &RC) const;
2495
2496 /// Replace/modify any TargetFrameIndex operands with a targte-dependent
2497 /// sequence of memory operands that is recognized by PrologEpilogInserter.
2498 MachineBasicBlock *emitPatchPoint(MachineInstr &MI,
2499 MachineBasicBlock *MBB) const;
2500 };
2501
2502 /// This class defines information used to lower LLVM code to legal SelectionDAG
2503 /// operators that the target instruction selector can accept natively.
2504 ///
2505 /// This class also defines callbacks that targets must implement to lower
2506 /// target-specific constructs to SelectionDAG operators.
2507 class TargetLowering : public TargetLoweringBase {
2508 public:
2509 struct DAGCombinerInfo;
2510
2511 TargetLowering(const TargetLowering &) = delete;
2512 TargetLowering &operator=(const TargetLowering &) = delete;
2513
2514 /// NOTE: The TargetMachine owns TLOF.
2515 explicit TargetLowering(const TargetMachine &TM);
2516
2517 bool isPositionIndependent() const;
2518
2519 /// Returns true by value, base pointer and offset pointer and addressing mode
2520 /// by reference if the node's address can be legally represented as
2521 /// pre-indexed load / store address.
2522 virtual bool getPreIndexedAddressParts(SDNode * /*N*/, SDValue &/*Base*/,
2523 SDValue &/*Offset*/,
2524 ISD::MemIndexedMode &/*AM*/,
2525 SelectionDAG &/*DAG*/) const {
2526 return false;
2527 }
2528
2529 /// Returns true by value, base pointer and offset pointer and addressing mode
2530 /// by reference if this node can be combined with a load / store to form a
2531 /// post-indexed load / store.
2532 virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
2533 SDValue &/*Base*/,
2534 SDValue &/*Offset*/,
2535 ISD::MemIndexedMode &/*AM*/,
2536 SelectionDAG &/*DAG*/) const {
2537 return false;
2538 }
2539
2540 /// Return the entry encoding for a jump table in the current function. The
2541 /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum.
2542 virtual unsigned getJumpTableEncoding() const;
2543
2544 virtual const MCExpr *
2545 LowerCustomJumpTableEntry(const MachineJumpTableInfo * /*MJTI*/,
2546 const MachineBasicBlock * /*MBB*/, unsigned /*uid*/,
2547 MCContext &/*Ctx*/) const {
2548 llvm_unreachable("Need to implement this hook if target has custom JTIs");
2549 }
2550
2551 /// Returns relocation base for the given PIC jumptable.
2552 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
2553 SelectionDAG &DAG) const;
2554
2555 /// This returns the relocation base for the given PIC jumptable, the same as
2556 /// getPICJumpTableRelocBase, but as an MCExpr.
2557 virtual const MCExpr *
2558 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
2559 unsigned JTI, MCContext &Ctx) const;
2560
2561 /// Return true if folding a constant offset with the given GlobalAddress is
2562 /// legal. It is frequently not legal in PIC relocation models.
2563 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
2564
2565 bool isInTailCallPosition(SelectionDAG &DAG, SDNode *Node,
2566 SDValue &Chain) const;
2567
2568 void softenSetCCOperands(SelectionDAG &DAG, EVT VT, SDValue &NewLHS,
2569 SDValue &NewRHS, ISD::CondCode &CCCode,
2570 const SDLoc &DL) const;
2571
2572 /// Returns a pair of (return value, chain).
2573 /// It is an error to pass RTLIB::UNKNOWN_LIBCALL as \p LC.
2574 std::pair makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC,
2575 EVT RetVT, ArrayRef Ops,
2576 bool isSigned, const SDLoc &dl,
2577 bool doesNotReturn = false,
2578 bool isReturnValueUsed = true) const;
2579
2580 /// Check whether parameters to a call that are passed in callee saved
2581 /// registers are the same as from the calling function. This needs to be
2582 /// checked for tail call eligibility.
2583 bool parametersInCSRMatch(const MachineRegisterInfo &MRI,
2584 const uint32_t *CallerPreservedMask,
2585 const SmallVectorImpl &ArgLocs,
2586 const SmallVectorImpl &OutVals) const;
2587
2588 //===--------------------------------------------------------------------===//
2589 // TargetLowering Optimization Methods
2590 //
2591
2592 /// A convenience struct that encapsulates a DAG, and two SDValues for
2593 /// returning information from TargetLowering to its clients that want to
2594 /// combine.
2595 struct TargetLoweringOpt {
2596 SelectionDAG &DAG;
2597 bool LegalTys;
2598 bool LegalOps;
2599 SDValue Old;
2600 SDValue New;
2601
2602 explicit TargetLoweringOpt(SelectionDAG &InDAG,
2603 bool LT, bool LO) :
2604 DAG(InDAG), LegalTys(LT), LegalOps(LO) {}
2605
2606 bool LegalTypes() const { return LegalTys; }
2607 bool LegalOperations() const { return LegalOps; }
2608
2609 bool CombineTo(SDValue O, SDValue N) {
2610 Old = O;
2611 New = N;
2612 return true;
2613 }
2614 };
2615
2616 /// Check to see if the specified operand of the specified instruction is a
2617 /// constant integer. If so, check to see if there are any bits set in the
2618 /// constant that are not demanded. If so, shrink the constant and return
2619 /// true.
2620 bool ShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2621 TargetLoweringOpt &TLO) const;
2622
2623 // Target hook to do target-specific const optimization, which is called by
2624 // ShrinkDemandedConstant. This function should return true if the target
2625 // doesn't want ShrinkDemandedConstant to further optimize the constant.
2626 virtual bool targetShrinkDemandedConstant(SDValue Op, const APInt &Demanded,
2627 TargetLoweringOpt &TLO) const {
2628 return false;
2629 }
2630
2631 /// Convert x+y to (VT)((SmallVT)x+(SmallVT)y) if the casts are free. This
2632 /// uses isZExtFree and ZERO_EXTEND for the widening cast, but it could be
2633 /// generalized for targets with other types of implicit widening casts.
2634 bool ShrinkDemandedOp(SDValue Op, unsigned BitWidth, const APInt &Demanded,
2635 TargetLoweringOpt &TLO) const;
2636
2637 /// Helper for SimplifyDemandedBits that can simplify an operation with
2638 /// multiple uses. This function simplifies operand \p OpIdx of \p User and
2639 /// then updates \p User with the simplified version. No other uses of
2640 /// \p OpIdx are updated. If \p User is the only user of \p OpIdx, this
2641 /// function behaves exactly like function SimplifyDemandedBits declared
2642 /// below except that it also updates the DAG by calling
2643 /// DCI.CommitTargetLoweringOpt.
2644 bool SimplifyDemandedBits(SDNode *User, unsigned OpIdx, const APInt &Demanded,
2645 DAGCombinerInfo &DCI, TargetLoweringOpt &TLO) const;
2646
2647 /// Look at Op. At this point, we know that only the DemandedMask bits of the
2648 /// result of Op are ever used downstream. If we can use this information to
2649 /// simplify Op, create a new simplified DAG node and return true, returning
2650 /// the original and new nodes in Old and New. Otherwise, analyze the
2651 /// expression and return a mask of KnownOne and KnownZero bits for the
2652 /// expression (used to simplify the caller). The KnownZero/One bits may only
2653 /// be accurate for those bits in the DemandedMask.
2654 /// \p AssumeSingleUse When this parameter is true, this function will
2655 /// attempt to simplify \p Op even if there are multiple uses.
2656 /// Callers are responsible for correctly updating the DAG based on the
2657 /// results of this function, because simply replacing replacing TLO.Old
2658 /// with TLO.New will be incorrect when this parameter is true and TLO.Old
2659 /// has multiple uses.
2660 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2661 KnownBits &Known,
2662 TargetLoweringOpt &TLO,
2663 unsigned Depth = 0,
2664 bool AssumeSingleUse = false) const;
2665
2666 /// Helper wrapper around SimplifyDemandedBits
2667 bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask,
2668 DAGCombinerInfo &DCI) const;
2669
2670 /// Determine which of the bits specified in Mask are known to be either zero
2671 /// or one and return them in the KnownZero/KnownOne bitsets. The DemandedElts
2672 /// argument allows us to only collect the known bits that are shared by the
2673 /// requested vector elements.
2674 virtual void computeKnownBitsForTargetNode(const SDValue Op,
2675 KnownBits &Known,
2676 const APInt &DemandedElts,
2677 const SelectionDAG &DAG,
2678 unsigned Depth = 0) const;
2679
2680 /// Determine which of the bits of FrameIndex \p FIOp are known to be 0.
2681 /// Default implementation computes low bits based on alignment
2682 /// information. This should preserve known bits passed into it.
2683 virtual void computeKnownBitsForFrameIndex(const SDValue FIOp,
2684 KnownBits &Known,
2685 const APInt &DemandedElts,
2686 const SelectionDAG &DAG,
2687 unsigned Depth = 0) const;
2688
2689 /// This method can be implemented by targets that want to expose additional
2690 /// information about sign bits to the DAG Combiner. The DemandedElts
2691 /// argument allows us to only collect the minimum sign bits that are shared
2692 /// by the requested vector elements.
2693 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
2694 const APInt &DemandedElts,
2695 const SelectionDAG &DAG,
2696 unsigned Depth = 0) const;
2697
2698 struct DAGCombinerInfo {
2699 void *DC; // The DAG Combiner object.
2700 CombineLevel Level;
2701 bool CalledByLegalizer;
2702
2703 public:
2704 SelectionDAG &DAG;
2705
2706 DAGCombinerInfo(SelectionDAG &dag, CombineLevel level, bool cl, void *dc)
2707 : DC(dc), Level(level), CalledByLegalizer(cl), DAG(dag) {}
2708
2709 bool isBeforeLegalize() const { return Level == BeforeLegalizeTypes; }
2710 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; }
2711 bool isAfterLegalizeVectorOps() const {
2712 return Level == AfterLegalizeDAG;
2713 }
2714 CombineLevel getDAGCombineLevel() { return Level; }
2715 bool isCalledByLegalizer() const { return CalledByLegalizer; }
2716
2717 void AddToWorklist(SDNode *N);
2718 SDValue CombineTo(SDNode *N, ArrayRef To, bool AddTo = true);
2719 SDValue CombineTo(SDNode *N, SDValue Res, bool AddTo = true);
2720 SDValue CombineTo(SDNode *N, SDValue Res0, SDValue Res1, bool AddTo = true);
2721
2722 void CommitTargetLoweringOpt(const TargetLoweringOpt &TLO);
2723 };
2724
2725 /// Return if the N is a constant or constant vector equal to the true value
2726 /// from getBooleanContents().
2727 bool isConstTrueVal(const SDNode *N) const;
2728
2729 /// Return if the N is a constant or constant vector equal to the false value
2730 /// from getBooleanContents().
2731 bool isConstFalseVal(const SDNode *N) const;
2732
2733 /// Return a constant of type VT that contains a true value that respects
2734 /// getBooleanContents()
2735 SDValue getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const;
2736
2737 /// Return if \p N is a True value when extended to \p VT.
2738 bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
2739
2740 /// Try to simplify a setcc built with the specified operands and cc. If it is
2741 /// unable to simplify it, return a null SDValue.
2742 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
2743 bool foldBooleans, DAGCombinerInfo &DCI,
2744 const SDLoc &dl) const;
2745
2746 // For targets which wrap address, unwrap for analysis.
2747 virtual SDValue unwrapAddress(SDValue N) const { return N; }
2748
2749 /// Returns true (and the GlobalValue and the offset) if the node is a
2750 /// GlobalAddress + offset.
2751 virtual bool
2752 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
2753
2754 /// This method will be invoked for all target nodes and for any
2755 /// target-independent nodes that the target has registered with invoke it
2756 /// for.
2757 ///
2758 /// The semantics are as follows:
2759 /// Return Value:
2760 /// SDValue.Val == 0 - No change was made
2761 /// SDValue.Val == N - N was replaced, is dead, and is already handled.
2762 /// otherwise - N should be replaced by the returned Operand.
2763 ///
2764 /// In addition, methods provided by DAGCombinerInfo may be used to perform
2765 /// more complex transformations.
2766 ///
2767 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
2768
2769 /// Return true if it is profitable to move a following shift through this
2770 // node, adjusting any immediate operands as necessary to preserve semantics.
2771 // This transformation may not be desirable if it disrupts a particularly
2772 // auspicious target-specific tree (e.g. bitfield extraction in AArch64).
2773 // By default, it returns true.
2774 virtual bool isDesirableToCommuteWithShift(const SDNode *N) const {
2775 return true;
2776 }
2777
2778 // Return true if it is profitable to combine a BUILD_VECTOR with a stride-pattern
2779 // to a shuffle and a truncate.
2780 // Example of such a combine:
2781 // v4i32 build_vector((extract_elt V, 1),
2782 // (extract_elt V, 3),
2783 // (extract_elt V, 5),
2784 // (extract_elt V, 7))
2785 // -->
2786 // v4i32 truncate (bitcast (shuffle<1,u,3,u,5,u,7,u> V, u) to v4i64)
2787 virtual bool isDesirableToCombineBuildVectorToShuffleTruncate(
2788 ArrayRef ShuffleMask, EVT SrcVT, EVT TruncVT) const {
2789 return false;
2790 }
2791
2792 /// Return true if the target has native support for the specified value type
2793 /// and it is 'desirable' to use the type for the given node type. e.g. On x86
2794 /// i16 is legal, but undesirable since i16 instruction encodings are longer
2795 /// and some i16 instructions are slow.
2796 virtual bool isTypeDesirableForOp(unsigned /*Opc*/, EVT VT) const {
2797 // By default, assume all legal types are desirable.
2798 return isTypeLegal(VT);
2799 }
2800
2801 /// Return true if it is profitable for dag combiner to transform a floating
2802 /// point op of specified opcode to a equivalent op of an integer
2803 /// type. e.g. f32 load -> i32 load can be profitable on ARM.
2804 virtual bool isDesirableToTransformToIntegerOp(unsigned /*Opc*/,
2805 EVT /*VT*/) const {
2806 return false;
2807 }
2808
2809 /// This method query the target whether it is beneficial for dag combiner to
2810 /// promote the specified node. If true, it should return the desired
2811 /// promotion type by reference.
2812 virtual bool IsDesirableToPromoteOp(SDValue /*Op*/, EVT &/*PVT*/) const {
2813