llvm.org GIT mirror llvm / e2d5b75
[AMDGPU][MC][DOC] Updated AMD GPU assembler description git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@338125 91177308-0d34-0410-b5e6-96231b3b80d8 Dmitry Preobrazhensky 2 years ago
4 changed file(s) with 161 addition(s) and 32 deletion(s). Raw diff Collapse all Expand all
262262 image_get_resinfo dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
263263 image_load dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
264264 image_load_mip dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
265 image_load_mip_pck dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
266 image_load_mip_pck_sgn dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
267 image_load_pck dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
268 image_load_pck_sgn dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
265269 image_sample dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
266270 image_sample_b dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
267271 image_sample_b_cl dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
278282 image_sample_lz dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
279283 image_store src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
280284 image_store_mip src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
285 image_store_mip_pck src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
286 image_store_pck src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
281287
282288 MUBUF
283289 ===========================
2121 ds_add_rtn_f32 dst, src0, src1 :ref:`ds_offset16` :ref:`gds`
2222 ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16` :ref:`gds`
2323 ds_add_rtn_u64 dst, src0, src1 :ref:`ds_offset16` :ref:`gds`
24 ds_add_src2_f32 src0 :ref:`ds_offset16` :ref:`gds`
2425 ds_add_src2_u32 src0 :ref:`ds_offset16` :ref:`gds`
2526 ds_add_src2_u64 src0 :ref:`ds_offset16` :ref:`gds`
2627 ds_add_u32 src0, src1 :ref:`ds_offset16` :ref:`gds`
260261 image_get_resinfo dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
261262 image_load dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
262263 image_load_mip dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
264 image_load_mip_pck dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
265 image_load_mip_pck_sgn dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
266 image_load_pck dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
267 image_load_pck_sgn dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
263268 image_sample dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
264269 image_sample_b dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
265270 image_sample_b_cl dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
274279 image_sample_lz dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
275280 image_store src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
276281 image_store_mip src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
282 image_store_mip_pck src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
283 image_store_pck src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
277284
278285 MUBUF
279286 ===========================
335342 buffer_store_format_xy src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
336343 buffer_store_format_xyz src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
337344 buffer_store_format_xyzw src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
345 buffer_store_lds_dword src0, src1 :ref:`buf_offset12` :ref:`lds` :ref:`glc` :ref:`slc`
338346 buffer_store_short src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
339347 buffer_wbinvl1
340348 buffer_wbinvl1_vol
344352
345353 .. parsed-literal::
346354
355 s_atc_probe src0, src1, src2
356 s_atc_probe_buffer src0, src1, src2
347357 s_buffer_load_dword dst, src0, src1 :ref:`glc`
348358 s_buffer_load_dwordx16 dst, src0, src1 :ref:`glc`
349359 s_buffer_load_dwordx2 dst, src0, src1 :ref:`glc`
793803 v_ashrrev_i32_dpp dst, src0, src1 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
794804 v_ashrrev_i32_sdwa dst, src0, src1 :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel`
795805 v_cndmask_b32 dst, src0, src1, src2
806 v_cndmask_b32_dpp dst, src0, src1, src2 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
807 v_cndmask_b32_sdwa dst, src0, src1, src2 :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel`
796808 v_ldexp_f16 dst, src0, src1
797809 v_ldexp_f16_dpp dst, src0, src1 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
798810 v_ldexp_f16_sdwa dst, src0, src1 :ref:`clamp` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel`
2121 ds_add_rtn_f32 dst, src0, src1 :ref:`ds_offset16` :ref:`gds`
2222 ds_add_rtn_u32 dst, src0, src1 :ref:`ds_offset16` :ref:`gds`
2323 ds_add_rtn_u64 dst, src0, src1 :ref:`ds_offset16` :ref:`gds`
24 ds_add_src2_f32 src0 :ref:`ds_offset16` :ref:`gds`
2425 ds_add_src2_u32 src0 :ref:`ds_offset16` :ref:`gds`
2526 ds_add_src2_u64 src0 :ref:`ds_offset16` :ref:`gds`
2627 ds_add_u32 src0, src1 :ref:`ds_offset16` :ref:`gds`
318319 image_atomic_umax dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
319320 image_atomic_umin dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
320321 image_atomic_xor dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
322 image_gather4 dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
321323 image_gather4_b dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
322324 image_gather4_c dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
323325 image_gather4_c_lz dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
324326 image_gather4_cl dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
325327 image_gather4_l dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
328 image_gather4_lz dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
326329 image_gather4_lz_o dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
327330 image_gather4_o dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
331 image_get_lod dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
328332 image_get_resinfo dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
329333 image_load dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
330334 image_load_mip dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
335 image_load_mip_pck dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
336 image_load_mip_pck_sgn dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
337 image_load_pck dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
338 image_load_pck_sgn dst, src0, src1 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da`
339 image_sample dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
331340 image_sample_b dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
332341 image_sample_c dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
333342 image_sample_c_lz dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
334343 image_sample_cl dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
335344 image_sample_l dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
345 image_sample_lz dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
336346 image_sample_lz_o dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
337347 image_sample_o dst, src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`tfe` :ref:`lwe` :ref:`da` :ref:`d16`
338348 image_store src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
339349 image_store_mip src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da` :ref:`d16`
350 image_store_mip_pck src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
351 image_store_pck src0, src1, src2 :ref:`dmask` :ref:`unorm` :ref:`glc` :ref:`slc` :ref:`lwe` :ref:`da`
340352
341353 MUBUF
342354 ===========================
373385 buffer_load_dwordx2 dst, src0, src1, src2 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
374386 buffer_load_dwordx3 dst, src0, src1, src2 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
375387 buffer_load_dwordx4 dst, src0, src1, src2 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
388 buffer_load_format_d16_hi_x dst, src0, src1, src2 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
376389 buffer_load_format_d16_x dst, src0, src1, src2 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
377390 buffer_load_format_d16_xy dst, src0, src1, src2 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
378391 buffer_load_format_d16_xyz dst, src0, src1, src2 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
397410 buffer_store_dwordx2 src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
398411 buffer_store_dwordx3 src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
399412 buffer_store_dwordx4 src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
413 buffer_store_format_d16_hi_x src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
400414 buffer_store_format_d16_x src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
401415 buffer_store_format_d16_xy src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
402416 buffer_store_format_d16_xyz src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
405419 buffer_store_format_xy src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
406420 buffer_store_format_xyz src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
407421 buffer_store_format_xyzw src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
422 buffer_store_lds_dword src0, src1 :ref:`buf_offset12` :ref:`lds`
408423 buffer_store_short src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
409424 buffer_store_short_d16_hi src0, src1, src2, src3 :ref:`idxen` :ref:`offen` :ref:`buf_offset12` :ref:`glc` :ref:`slc`
410425 buffer_wbinvl1
415430
416431 .. parsed-literal::
417432
433 s_atc_probe src0, src1, src2
434 s_atc_probe_buffer src0, src1, src2
435 s_atomic_add dst, src0, src1 :ref:`glc`
436 s_atomic_add_x2 dst, src0, src1 :ref:`glc`
437 s_atomic_and dst, src0, src1 :ref:`glc`
438 s_atomic_and_x2 dst, src0, src1 :ref:`glc`
439 s_atomic_cmpswap dst, src0, src1 :ref:`glc`
440 s_atomic_cmpswap_x2 dst, src0, src1 :ref:`glc`
441 s_atomic_dec dst, src0, src1 :ref:`glc`
442 s_atomic_dec_x2 dst, src0, src1 :ref:`glc`
443 s_atomic_inc dst, src0, src1 :ref:`glc`
444 s_atomic_inc_x2 dst, src0, src1 :ref:`glc`
445 s_atomic_or dst, src0, src1 :ref:`glc`
446 s_atomic_or_x2 dst, src0, src1 :ref:`glc`
447 s_atomic_smax dst, src0, src1 :ref:`glc`
448 s_atomic_smax_x2 dst, src0, src1 :ref:`glc`
449 s_atomic_smin dst, src0, src1 :ref:`glc`
450 s_atomic_smin_x2 dst, src0, src1 :ref:`glc`
451 s_atomic_sub dst, src0, src1 :ref:`glc`
452 s_atomic_sub_x2 dst, src0, src1 :ref:`glc`
453 s_atomic_swap dst, src0, src1 :ref:`glc`
454 s_atomic_swap_x2 dst, src0, src1 :ref:`glc`
455 s_atomic_umax dst, src0, src1 :ref:`glc`
456 s_atomic_umax_x2 dst, src0, src1 :ref:`glc`
457 s_atomic_umin dst, src0, src1 :ref:`glc`
458 s_atomic_umin_x2 dst, src0, src1 :ref:`glc`
459 s_atomic_xor dst, src0, src1 :ref:`glc`
460 s_atomic_xor_x2 dst, src0, src1 :ref:`glc`
461 s_buffer_atomic_add dst, src0, src1 :ref:`glc`
462 s_buffer_atomic_add_x2 dst, src0, src1 :ref:`glc`
463 s_buffer_atomic_and dst, src0, src1 :ref:`glc`
464 s_buffer_atomic_and_x2 dst, src0, src1 :ref:`glc`
465 s_buffer_atomic_cmpswap dst, src0, src1 :ref:`glc`
466 s_buffer_atomic_cmpswap_x2 dst, src0, src1 :ref:`glc`
467 s_buffer_atomic_dec dst, src0, src1 :ref:`glc`
468 s_buffer_atomic_dec_x2 dst, src0, src1 :ref:`glc`
469 s_buffer_atomic_inc dst, src0, src1 :ref:`glc`
470 s_buffer_atomic_inc_x2 dst, src0, src1 :ref:`glc`
471 s_buffer_atomic_or dst, src0, src1 :ref:`glc`
472 s_buffer_atomic_or_x2 dst, src0, src1 :ref:`glc`
473 s_buffer_atomic_smax dst, src0, src1 :ref:`glc`
474 s_buffer_atomic_smax_x2 dst, src0, src1 :ref:`glc`
475 s_buffer_atomic_smin dst, src0, src1 :ref:`glc`
476 s_buffer_atomic_smin_x2 dst, src0, src1 :ref:`glc`
477 s_buffer_atomic_sub dst, src0, src1 :ref:`glc`
478 s_buffer_atomic_sub_x2 dst, src0, src1 :ref:`glc`
479 s_buffer_atomic_swap dst, src0, src1 :ref:`glc`
480 s_buffer_atomic_swap_x2 dst, src0, src1 :ref:`glc`
481 s_buffer_atomic_umax dst, src0, src1 :ref:`glc`
482 s_buffer_atomic_umax_x2 dst, src0, src1 :ref:`glc`
483 s_buffer_atomic_umin dst, src0, src1 :ref:`glc`
484 s_buffer_atomic_umin_x2 dst, src0, src1 :ref:`glc`
485 s_buffer_atomic_xor dst, src0, src1 :ref:`glc`
486 s_buffer_atomic_xor_x2 dst, src0, src1 :ref:`glc`
418487 s_buffer_load_dword dst, src0, src1 :ref:`glc`
419488 s_buffer_load_dwordx16 dst, src0, src1 :ref:`glc`
420489 s_buffer_load_dwordx2 dst, src0, src1 :ref:`glc`
423492 s_buffer_store_dword src0, src1, src2 :ref:`glc`
424493 s_buffer_store_dwordx2 src0, src1, src2 :ref:`glc`
425494 s_buffer_store_dwordx4 src0, src1, src2 :ref:`glc`
495 s_dcache_discard src0, src1
496 s_dcache_discard_x2 src0, src1
426497 s_dcache_inv
427498 s_dcache_inv_vol
428499 s_dcache_wb
434505 s_load_dwordx8 dst, src0, src1 :ref:`glc`
435506 s_memrealtime dst
436507 s_memtime dst
508 s_scratch_load_dword dst, src0, src1 :ref:`glc`
509 s_scratch_load_dwordx2 dst, src0, src1 :ref:`glc`
510 s_scratch_load_dwordx4 dst, src0, src1 :ref:`glc`
511 s_scratch_store_dword src0, src1, src2 :ref:`glc`
512 s_scratch_store_dwordx2 src0, src1, src2 :ref:`glc`
513 s_scratch_store_dwordx4 src0, src1, src2 :ref:`glc`
437514 s_store_dword src0, src1, src2 :ref:`glc`
438515 s_store_dwordx2 src0, src1, src2 :ref:`glc`
439516 s_store_dwordx4 src0, src1, src2 :ref:`glc`
445522
446523 s_abs_i32 dst, src0
447524 s_and_saveexec_b64 dst, src0
525 s_andn1_saveexec_b64 dst, src0
526 s_andn1_wrexec_b64 dst, src0
448527 s_andn2_saveexec_b64 dst, src0
528 s_andn2_wrexec_b64 dst, src0
449529 s_bcnt0_i32_b32 dst, src0
450530 s_bcnt0_i32_b64 dst, src0
451531 s_bcnt1_i32_b32 dst, src0
452532 s_bcnt1_i32_b64 dst, src0
533 s_bitreplicate_b64_b32 dst, src0
453534 s_bitset0_b32 dst, src0
454535 s_bitset0_b64 dst, src0
455536 s_bitset1_b32 dst, src0
480561 s_not_b32 dst, src0
481562 s_not_b64 dst, src0
482563 s_or_saveexec_b64 dst, src0
564 s_orn1_saveexec_b64 dst, src0
483565 s_orn2_saveexec_b64 dst, src0
484566 s_quadmask_b32 dst, src0
485567 s_quadmask_b64 dst, src0
518600 s_cbranch_g_fork src0, src1
519601 s_cselect_b32 dst, src0, src1
520602 s_cselect_b64 dst, src0, src1
603 s_lshl1_add_u32 dst, src0, src1
604 s_lshl2_add_u32 dst, src0, src1
605 s_lshl3_add_u32 dst, src0, src1
606 s_lshl4_add_u32 dst, src0, src1
521607 s_lshl_b32 dst, src0, src1
522608 s_lshl_b64 dst, src0, src1
523609 s_lshr_b32 dst, src0, src1
526612 s_max_u32 dst, src0, src1
527613 s_min_i32 dst, src0, src1
528614 s_min_u32 dst, src0, src1
615 s_mul_hi_i32 dst, src0, src1
616 s_mul_hi_u32 dst, src0, src1
529617 s_mul_i32 dst, src0, src1
530618 s_nand_b32 dst, src0, src1
531619 s_nand_b64 dst, src0, src1
579667 .. parsed-literal::
580668
581669 s_addk_i32 dst, src0
670 s_call_b64 dst, src0
582671 s_cbranch_i_fork src0, src1
583672 s_cmovk_i32 dst, src0
584673 s_cmpk_eq_i32 src0, src1
618707 s_cbranch_vccz src0
619708 s_decperflevel src0
620709 s_endpgm
710 s_endpgm_ordered_ps_done
621711 s_endpgm_saved
622712 s_icache_inv
623713 s_incperflevel src0
710800 v_cvt_i32_f32_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
711801 v_cvt_i32_f32_sdwa dst, src0 :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
712802 v_cvt_i32_f64 dst, src0
803 v_cvt_norm_i16_f16 dst, src0
804 v_cvt_norm_i16_f16_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
805 v_cvt_norm_i16_f16_sdwa dst, src0 :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
806 v_cvt_norm_u16_f16 dst, src0
807 v_cvt_norm_u16_f16_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
808 v_cvt_norm_u16_f16_sdwa dst, src0 :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
713809 v_cvt_off_f32_i4 dst, src0
714810 v_cvt_off_f32_i4_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
715811 v_cvt_off_f32_i4_sdwa dst, src0 :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
813909 v_rsq_f32_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
814910 v_rsq_f32_sdwa dst, src0 :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
815911 v_rsq_f64 dst, src0
912 v_sat_pk_u8_i16 dst, src0
913 v_sat_pk_u8_i16_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
914 v_sat_pk_u8_i16_sdwa dst, src0 :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
915 v_screen_partition_4se_b32 dst, src0
916 v_screen_partition_4se_b32_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
917 v_screen_partition_4se_b32_sdwa dst, src0 :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
816918 v_sin_f16 dst, src0
817919 v_sin_f16_dpp dst, src0 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
818920 v_sin_f16_sdwa dst, src0 :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel`
868970 v_ashrrev_i32_dpp dst, src0, src1 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
869971 v_ashrrev_i32_sdwa dst, src0, src1 :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel`
870972 v_cndmask_b32 dst, src0, src1, src2
973 v_cndmask_b32_dpp dst, src0, src1, src2 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
974 v_cndmask_b32_sdwa dst, src0, src1, src2 :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel`
871975 v_ldexp_f16 dst, src0, src1
872976 v_ldexp_f16_dpp dst, src0, src1 :ref:`dpp_ctrl` :ref:`row_mask` :ref:`bank_mask` :ref:`bound_ctrl`
873977 v_ldexp_f16_sdwa dst, src0, src1 :ref:`clamp` :ref:`omod` :ref:`dst_sel` :ref:`dst_unused` :ref:`src0_sel` :ref:`src1_sel`
12501354 v_cvt_i16_f16_e64 dst, src0 :ref:`clamp` :ref:`omod`
12511355 v_cvt_i32_f32_e64 dst, src0 :ref:`clamp` :ref:`omod`
12521356 v_cvt_i32_f64_e64 dst, src0 :ref:`clamp` :ref:`omod`
1357 v_cvt_norm_i16_f16_e64 dst, src0 :ref:`omod`
1358 v_cvt_norm_u16_f16_e64 dst, src0 :ref:`omod`
12531359 v_cvt_off_f32_i4_e64 dst, src0 :ref:`clamp` :ref:`omod`
12541360 v_cvt_pk_i16_i32 dst, src0, src1 :ref:`omod`
12551361 v_cvt_pk_u16_u32 dst, src0, src1 :ref:`omod`
14051511 v_sad_u16 dst, src0, src1, src2 :ref:`clamp` :ref:`omod`
14061512 v_sad_u32 dst, src0, src1, src2 :ref:`clamp` :ref:`omod`
14071513 v_sad_u8 dst, src0, src1, src2 :ref:`clamp` :ref:`omod`
1514 v_sat_pk_u8_i16_e64 dst, src0 :ref:`omod`
1515 v_screen_partition_4se_b32_e64 dst, src0 :ref:`omod`
14081516 v_sin_f16_e64 dst, src0 :ref:`clamp` :ref:`omod`
14091517 v_sin_f32_e64 dst, src0 :ref:`clamp` :ref:`omod`
14101518 v_sqrt_f16_e64 dst, src0 :ref:`clamp` :ref:`omod`
14371545
14381546 .. parsed-literal::
14391547
1440 v_mad_mix_f32 dst, src0, src1, src2 :ref:`mad_op_sel` :ref:`mad_op_sel_hi` :ref:`clamp`
1441 v_mad_mixhi_f16 dst, src0, src1, src2 :ref:`mad_op_sel` :ref:`mad_op_sel_hi` :ref:`clamp`
1442 v_mad_mixlo_f16 dst, src0, src1, src2 :ref:`mad_op_sel` :ref:`mad_op_sel_hi_op_sel_hi>` :ref:`clamp`
1548 v_mad_mix_f32 dst, src0, src1, src2 :ref:`mad_mix_op_sel` :ref:`mad_mix_op_sel_hi_op_sel_hi>` :ref:`clamp`
1549 v_mad_mixhi_f16 dst, src0, src1, src2 :ref:`mad_mix_op_sel` :ref:`mad_mix_op_sel_hi` :ref:`clamp`
1550 v_mad_mixlo_f16 dst, src0, src1, src2 :ref:`mad_mix_op_sel` :ref:`mad_mix_op_sel_hi` :ref:`clamp`
14431551 v_pk_add_f16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp`
14441552 v_pk_add_i16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp`
14451553 v_pk_add_u16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp`
14461554 v_pk_ashrrev_i16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi`
1555 v_pk_fma_f16 dst, src0, src1, src2 :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp`
14471556 v_pk_lshlrev_b16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi`
14481557 v_pk_lshrrev_b16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi`
1558 v_pk_mad_i16 dst, src0, src1, src2 :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp`
1559 v_pk_mad_u16 dst, src0, src1, src2 :ref:`op_sel` :ref:`op_sel_hi` :ref:`clamp`
14491560 v_pk_max_f16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi` :ref:`neg_lo` :ref:`neg_hi` :ref:`clamp`
14501561 v_pk_max_i16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi`
14511562 v_pk_max_u16 dst, src0, src1 :ref:`op_sel` :ref:`op_sel_hi`
10011001
10021002 GFX9 only.
10031003
1004 .. _amdgpu_synid_mad_op_sel:
1005
1006 mad_op_sel
1007 ~~~~~~~~~~
1004 .. _amdgpu_synid_mad_mix_op_sel:
1005
1006 mad_mix_op_sel
1007 ~~~~~~~~~~~~~~
1008
1009 This operand has meaning only for 16-bit source operands as indicated by
1010 :ref:`mad_mix_op_sel_hi`.
1011 It specifies to select either the low [15:0] or high [31:16] operand bits
1012 as input to the operation.
1013
1014 The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
1015 By default, low bits are used for all operands.
1016
1017 ======================================== ================================================
1018 Syntax Description
1019 ======================================== ================================================
1020 op_sel:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand.
1021 ======================================== ================================================
1022
1023 .. _amdgpu_synid_mad_mix_op_sel_hi:
1024
1025 mad_mix_op_sel_hi
1026 ~~~~~~~~~~~~~~~~~
10081027
10091028 Selects the size of source operands: either 32 bits or 16 bits.
10101029 By default, 32 bits are used for all source operands.
10111030
10121031 The value 0 indicates 32 bits, the value 1 indicates 16 bits.
10131032 The location of 16 bits in the operand may be specified by
1014 :ref:`mad_op_sel_hi`.
1015
1016 ======================================== ================================================
1017 Syntax Description
1018 ======================================== ================================================
1019 op_sel:[{0..1},{0..1},{0..1}] Select size of each source operand.
1020 ======================================== ================================================
1021
1022 .. _amdgpu_synid_mad_op_sel_hi:
1023
1024 mad_op_sel_hi
1025 ~~~~~~~~~~~~~
1026
1027 This operand has meaning only for 16-bit source operands as indicated by
1028 :ref:`mad_op_sel`.
1029 It specifies to select either the low [15:0] or high [31:16] operand bits
1030 as input to the operation.
1031
1032 The value 0 indicates the low bits, the value 1 indicates the high 16 bits.
1033 By default, low bits are used for all operands.
1034
1035 ======================================== ================================================
1036 Syntax Description
1037 ======================================== ================================================
1038 op_sel_hi:[{0..1},{0..1},{0..1}] Select location of each 16-bit source operand.
1033 :ref:`mad_mix_op_sel`.
1034
1035 ======================================== ================================================
1036 Syntax Description
1037 ======================================== ================================================
1038 op_sel_hi:[{0..1},{0..1},{0..1}] Select size of each source operand.
10391039 ======================================== ================================================
10401040
10411041 abs