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Merging r324885: ------------------------------------------------------------------------ r324885 | atanasyan | 2018-02-12 04:21:55 -0800 (Mon, 12 Feb 2018) | 8 lines [mips] Fix 'l' constraint handling for types smaller than 32 bits In case of correct using of the 'l' constraint llvm now generates valid code; otherwise it shows an error message. Initially these triggers an assertion. This commit is the same as r324869 with fixed the test's file name. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@332776 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 4 months ago
3 changed file(s) with 24 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
38673867 return std::make_pair(0U, nullptr);
38683868 case 'l': // use the `lo` register to store values
38693869 // that are no bigger than a word
3870 if (VT == MVT::i32)
3870 if (VT == MVT::i32 || VT == MVT::i16 || VT == MVT::i8)
38713871 return std::make_pair((unsigned)Mips::LO0, &Mips::LO32RegClass);
38723872 return std::make_pair((unsigned)Mips::LO0_64, &Mips::LO64RegClass);
38733873 case 'x': // use the concatenated `hi` and `lo` registers
0 ; Negative test. The constraint 'l' represents the register 'lo'.
1 ; Check error message in case of invalid usage.
2 ;
3 ; RUN: not llc -march=mips -filetype=obj < %s 2>&1 | FileCheck %s
4
5 define void @constraint_l() nounwind {
6 entry:
7
8 ; CHECK: error: invalid operand for instruction
9
10 tail call i16 asm sideeffect "addiu $0,$1,$2", "=l,r,r,~{$1}"(i16 0, i16 0)
11 ret void
12 }
4040 call i32 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
4141 store volatile i32 %4, i32* %bosco, align 4
4242
43 ; Check the 'l' constraint for 16-bit type.
44 ; CHECK: #APP
45 ; CHECK: mtlo ${{[0-9]+}}
46 ; CHECK-NEXT: madd ${{[0-9]+}}, ${{[0-9]+}}
47 ; CHECK: #NO_APP
48 ; CHECK-NEXT: mflo ${{[0-9]+}}
49 %bosco16 = alloca i16, align 4
50 call i16 asm sideeffect "\09mtlo $3 \0A\09\09madd $1, $2 ", "=l,r,r,r"(i32 7, i32 6, i32 44) nounwind
51 store volatile i16 %5, i16* %bosco16, align 4
52
4353 ret i32 0
4454 }