llvm.org GIT mirror llvm / e2a98dd
Fix ARM memory operand parsing of post indexing with just a base register, that is just "[Rn]" and no tailing comma with an offset, etc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84205 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 11 years ago
1 changed file(s) with 43 addition(s) and 38 deletion(s). Raw diff Collapse all Expand all
382382 Writeback = true;
383383 getLexer().Lex(); // Eat right bracket token.
384384
385 const AsmToken &CommaTok = getLexer().getTok();
386 if (CommaTok.isNot(AsmToken::Comma))
387 return Error(CommaTok.getLoc(), "',' expected");
388 getLexer().Lex(); // Eat comma token.
389
390 const AsmToken &NextTok = getLexer().getTok();
391 if (NextTok.is(AsmToken::Plus))
392 getLexer().Lex(); // Eat plus token.
393 else if (NextTok.is(AsmToken::Minus)) {
394 Negative = true;
395 getLexer().Lex(); // Eat minus token
396 }
397
398 // See if there is a register following the "[Rn]," we have so far.
399 const AsmToken &OffsetRegTok = getLexer().getTok();
400 int OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
385 int OffsetRegNum = 0;
401386 bool OffsetRegShifted = false;
402387 enum ShiftType ShiftType;
403388 const MCExpr *ShiftAmount;
404389 const MCExpr *Offset;
405 if (OffsetRegNum != -1) {
406 OffsetIsReg = true;
407 getLexer().Lex(); // Eat identifier token for the offset register.
408 // Look for a comma then a shift
409 const AsmToken &Tok = getLexer().getTok();
410 if (Tok.is(AsmToken::Comma)) {
411 getLexer().Lex(); // Eat comma token.
412
413 const AsmToken &Tok = getLexer().getTok();
414 if (ParseShift(&ShiftType, ShiftAmount))
415 return Error(Tok.getLoc(), "shift expected");
416 OffsetRegShifted = true;
390
391 const AsmToken &NextTok = getLexer().getTok();
392 if (NextTok.isNot(AsmToken::EndOfStatement)) {
393 if (NextTok.isNot(AsmToken::Comma))
394 return Error(NextTok.getLoc(), "',' expected");
395 getLexer().Lex(); // Eat comma token.
396
397 const AsmToken &PlusMinusTok = getLexer().getTok();
398 if (PlusMinusTok.is(AsmToken::Plus))
399 getLexer().Lex(); // Eat plus token.
400 else if (PlusMinusTok.is(AsmToken::Minus)) {
401 Negative = true;
402 getLexer().Lex(); // Eat minus token
403 }
404
405 // See if there is a register following the "[Rn]," we have so far.
406 const AsmToken &OffsetRegTok = getLexer().getTok();
407 OffsetRegNum = MatchRegisterName(OffsetRegTok.getString());
408 if (OffsetRegNum != -1) {
409 OffsetIsReg = true;
410 getLexer().Lex(); // Eat identifier token for the offset register.
411 // Look for a comma then a shift
412 const AsmToken &Tok = getLexer().getTok();
413 if (Tok.is(AsmToken::Comma)) {
414 getLexer().Lex(); // Eat comma token.
415
416 const AsmToken &Tok = getLexer().getTok();
417 if (ParseShift(&ShiftType, ShiftAmount))
418 return Error(Tok.getLoc(), "shift expected");
419 OffsetRegShifted = true;
420 }
421 }
422 else { // "[Rn]," we have so far was not followed by "Rm"
423 // Look for #offset following the "[Rn],"
424 const AsmToken &HashTok = getLexer().getTok();
425 if (HashTok.isNot(AsmToken::Hash))
426 return Error(HashTok.getLoc(), "'#' expected");
427 getLexer().Lex(); // Eat hash token.
428
429 if (getParser().ParseExpression(Offset))
430 return true;
417431 }
418432 }
419 else { // "[Rn]," we have so far was not followed by "Rm"
420 // Look for #offset following the "[Rn],"
421 const AsmToken &HashTok = getLexer().getTok();
422 if (HashTok.isNot(AsmToken::Hash))
423 return Error(HashTok.getLoc(), "'#' expected");
424 getLexer().Lex(); // Eat hash token.
425
426 if (getParser().ParseExpression(Offset))
427 return true;
428 }
433
429434 Op = ARMOperand::CreateMem(BaseRegNum, OffsetIsReg, Offset, OffsetRegNum,
430435 OffsetRegShifted, ShiftType, ShiftAmount,
431436 Preindexed, Postindexed, Negative, Writeback);