llvm.org GIT mirror llvm / e220c4b
Add support for using the FLAGS result of or, xor, and and instructions on x86, to avoid explicit test instructions. A few existing tests changed due to arbitrary register allocation differences. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82263 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
7 changed file(s) with 456 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
53625362 Opcode = X86ISD::ADD;
53635363 NumOperands = 2;
53645364 break;
5365 case ISD::AND: {
5366 // If the primary and result isn't used, don't bother using X86ISD::AND,
5367 // because a TEST instruction will be better.
5368 bool NonFlagUse = false;
5369 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
5370 UE = Op.getNode()->use_end(); UI != UE; ++UI)
5371 if (UI->getOpcode() != ISD::BRCOND &&
5372 UI->getOpcode() != ISD::SELECT &&
5373 UI->getOpcode() != ISD::SETCC) {
5374 NonFlagUse = true;
5375 break;
5376 }
5377 if (!NonFlagUse)
5378 break;
5379 }
5380 // FALL THROUGH
53655381 case ISD::SUB:
5366 // Due to the ISEL shortcoming noted above, be conservative if this sub is
5382 case ISD::OR:
5383 case ISD::XOR:
5384 // Due to the ISEL shortcoming noted above, be conservative if this op is
53675385 // likely to be selected as part of a load-modify-store instruction.
53685386 for (SDNode::use_iterator UI = Op.getNode()->use_begin(),
53695387 UE = Op.getNode()->use_end(); UI != UE; ++UI)
53705388 if (UI->getOpcode() == ISD::STORE)
53715389 goto default_case;
5372 // Otherwise use a regular EFLAGS-setting sub.
5373 Opcode = X86ISD::SUB;
5390 // Otherwise use a regular EFLAGS-setting instruction.
5391 switch (Op.getNode()->getOpcode()) {
5392 case ISD::SUB: Opcode = X86ISD::SUB; break;
5393 case ISD::OR: Opcode = X86ISD::OR; break;
5394 case ISD::XOR: Opcode = X86ISD::XOR; break;
5395 case ISD::AND: Opcode = X86ISD::AND; break;
5396 default: llvm_unreachable("unexpected operator!");
5397 }
53745398 NumOperands = 2;
53755399 break;
53765400 case X86ISD::ADD:
53775401 case X86ISD::SUB:
53785402 case X86ISD::INC:
53795403 case X86ISD::DEC:
5404 case X86ISD::OR:
5405 case X86ISD::XOR:
5406 case X86ISD::AND:
53805407 return SDValue(Op.getNode(), 1);
53815408 default:
53825409 default_case:
56045631 Opc == X86ISD::SMUL ||
56055632 Opc == X86ISD::UMUL ||
56065633 Opc == X86ISD::INC ||
5607 Opc == X86ISD::DEC))
5634 Opc == X86ISD::DEC ||
5635 Opc == X86ISD::OR ||
5636 Opc == X86ISD::XOR ||
5637 Opc == X86ISD::AND))
56085638 return true;
56095639
56105640 return false;
71327162 case X86ISD::UMUL: return "X86ISD::UMUL";
71337163 case X86ISD::INC: return "X86ISD::INC";
71347164 case X86ISD::DEC: return "X86ISD::DEC";
7165 case X86ISD::OR: return "X86ISD::OR";
7166 case X86ISD::XOR: return "X86ISD::XOR";
7167 case X86ISD::AND: return "X86ISD::AND";
71357168 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM";
71367169 case X86ISD::PTEST: return "X86ISD::PTEST";
71377170 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS";
80938126 case X86ISD::UMUL:
80948127 case X86ISD::INC:
80958128 case X86ISD::DEC:
8129 case X86ISD::OR:
8130 case X86ISD::XOR:
8131 case X86ISD::AND:
80968132 // These nodes' second result is a boolean.
80978133 if (Op.getResNo() == 0)
80988134 break;
236236
237237 // ADD, SUB, SMUL, UMUL, etc. - Arithmetic operations with FLAGS results.
238238 ADD, SUB, SMUL, UMUL,
239 INC, DEC,
239 INC, DEC, OR, XOR, AND,
240240
241241 // MUL_IMM - X86 specific multiply by immediate.
242242 MUL_IMM,
20812081 (implicit EFLAGS)),
20822082 (DEC64m addr:$dst)>;
20832083
2084 // Register-Register Logical Or with EFLAGS result
2085 def : Pat<(parallel (X86or_flag GR64:$src1, GR64:$src2),
2086 (implicit EFLAGS)),
2087 (OR64rr GR64:$src1, GR64:$src2)>;
2088
2089 // Register-Integer Logical Or with EFLAGS result
2090 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt8:$src2),
2091 (implicit EFLAGS)),
2092 (OR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2093 def : Pat<(parallel (X86or_flag GR64:$src1, i64immSExt32:$src2),
2094 (implicit EFLAGS)),
2095 (OR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2096
2097 // Register-Memory Logical Or with EFLAGS result
2098 def : Pat<(parallel (X86or_flag GR64:$src1, (loadi64 addr:$src2)),
2099 (implicit EFLAGS)),
2100 (OR64rm GR64:$src1, addr:$src2)>;
2101
2102 // Memory-Register Logical Or with EFLAGS result
2103 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), GR64:$src2),
2104 addr:$dst),
2105 (implicit EFLAGS)),
2106 (OR64mr addr:$dst, GR64:$src2)>;
2107 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2108 addr:$dst),
2109 (implicit EFLAGS)),
2110 (OR64mi8 addr:$dst, i64immSExt8:$src2)>;
2111 def : Pat<(parallel (store (X86or_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2112 addr:$dst),
2113 (implicit EFLAGS)),
2114 (OR64mi32 addr:$dst, i64immSExt32:$src2)>;
2115
2116 // Register-Register Logical XOr with EFLAGS result
2117 def : Pat<(parallel (X86xor_flag GR64:$src1, GR64:$src2),
2118 (implicit EFLAGS)),
2119 (XOR64rr GR64:$src1, GR64:$src2)>;
2120
2121 // Register-Integer Logical XOr with EFLAGS result
2122 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt8:$src2),
2123 (implicit EFLAGS)),
2124 (XOR64ri8 GR64:$src1, i64immSExt8:$src2)>;
2125 def : Pat<(parallel (X86xor_flag GR64:$src1, i64immSExt32:$src2),
2126 (implicit EFLAGS)),
2127 (XOR64ri32 GR64:$src1, i64immSExt32:$src2)>;
2128
2129 // Register-Memory Logical XOr with EFLAGS result
2130 def : Pat<(parallel (X86xor_flag GR64:$src1, (loadi64 addr:$src2)),
2131 (implicit EFLAGS)),
2132 (XOR64rm GR64:$src1, addr:$src2)>;
2133
2134 // Memory-Register Logical XOr with EFLAGS result
2135 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), GR64:$src2),
2136 addr:$dst),
2137 (implicit EFLAGS)),
2138 (XOR64mr addr:$dst, GR64:$src2)>;
2139 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2140 addr:$dst),
2141 (implicit EFLAGS)),
2142 (XOR64mi8 addr:$dst, i64immSExt8:$src2)>;
2143 def : Pat<(parallel (store (X86xor_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2144 addr:$dst),
2145 (implicit EFLAGS)),
2146 (XOR64mi32 addr:$dst, i64immSExt32:$src2)>;
2147
2148 // Register-Register Logical And with EFLAGS result
2149 def : Pat<(parallel (X86and_flag GR64:$src1, GR64:$src2),
2150 (implicit EFLAGS)),
2151 (AND64rr GR64:$src1, GR64:$src2)>;
2152
2153 // Register-Integer Logical And with EFLAGS result
2154 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt8:$src2),
2155 (implicit EFLAGS)),
2156 (AND64ri8 GR64:$src1, i64immSExt8:$src2)>;
2157 def : Pat<(parallel (X86and_flag GR64:$src1, i64immSExt32:$src2),
2158 (implicit EFLAGS)),
2159 (AND64ri32 GR64:$src1, i64immSExt32:$src2)>;
2160
2161 // Register-Memory Logical And with EFLAGS result
2162 def : Pat<(parallel (X86and_flag GR64:$src1, (loadi64 addr:$src2)),
2163 (implicit EFLAGS)),
2164 (AND64rm GR64:$src1, addr:$src2)>;
2165
2166 // Memory-Register Logical And with EFLAGS result
2167 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), GR64:$src2),
2168 addr:$dst),
2169 (implicit EFLAGS)),
2170 (AND64mr addr:$dst, GR64:$src2)>;
2171 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt8:$src2),
2172 addr:$dst),
2173 (implicit EFLAGS)),
2174 (AND64mi8 addr:$dst, i64immSExt8:$src2)>;
2175 def : Pat<(parallel (store (X86and_flag (loadi64 addr:$dst), i64immSExt32:$src2),
2176 addr:$dst),
2177 (implicit EFLAGS)),
2178 (AND64mi32 addr:$dst, i64immSExt32:$src2)>;
2179
20842180 //===----------------------------------------------------------------------===//
20852181 // X86-64 SSE Instructions
20862182 //===----------------------------------------------------------------------===//
161161 def X86umul_flag : SDNode<"X86ISD::UMUL", SDTUnaryArithWithFlags>;
162162 def X86inc_flag : SDNode<"X86ISD::INC", SDTUnaryArithWithFlags>;
163163 def X86dec_flag : SDNode<"X86ISD::DEC", SDTUnaryArithWithFlags>;
164 def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags>;
165 def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags>;
166 def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags>;
164167
165168 def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>;
166169
44174420 (implicit EFLAGS)),
44184421 (DEC32m addr:$dst)>, Requires<[In32BitMode]>;
44194422
4423 // Register-Register Or with EFLAGS result
4424 def : Pat<(parallel (X86or_flag GR8:$src1, GR8:$src2),
4425 (implicit EFLAGS)),
4426 (OR8rr GR8:$src1, GR8:$src2)>;
4427 def : Pat<(parallel (X86or_flag GR16:$src1, GR16:$src2),
4428 (implicit EFLAGS)),
4429 (OR16rr GR16:$src1, GR16:$src2)>;
4430 def : Pat<(parallel (X86or_flag GR32:$src1, GR32:$src2),
4431 (implicit EFLAGS)),
4432 (OR32rr GR32:$src1, GR32:$src2)>;
4433
4434 // Register-Memory Or with EFLAGS result
4435 def : Pat<(parallel (X86or_flag GR8:$src1, (loadi8 addr:$src2)),
4436 (implicit EFLAGS)),
4437 (OR8rm GR8:$src1, addr:$src2)>;
4438 def : Pat<(parallel (X86or_flag GR16:$src1, (loadi16 addr:$src2)),
4439 (implicit EFLAGS)),
4440 (OR16rm GR16:$src1, addr:$src2)>;
4441 def : Pat<(parallel (X86or_flag GR32:$src1, (loadi32 addr:$src2)),
4442 (implicit EFLAGS)),
4443 (OR32rm GR32:$src1, addr:$src2)>;
4444
4445 // Register-Integer Or with EFLAGS result
4446 def : Pat<(parallel (X86or_flag GR8:$src1, imm:$src2),
4447 (implicit EFLAGS)),
4448 (OR8ri GR8:$src1, imm:$src2)>;
4449 def : Pat<(parallel (X86or_flag GR16:$src1, imm:$src2),
4450 (implicit EFLAGS)),
4451 (OR16ri GR16:$src1, imm:$src2)>;
4452 def : Pat<(parallel (X86or_flag GR32:$src1, imm:$src2),
4453 (implicit EFLAGS)),
4454 (OR32ri GR32:$src1, imm:$src2)>;
4455 def : Pat<(parallel (X86or_flag GR16:$src1, i16immSExt8:$src2),
4456 (implicit EFLAGS)),
4457 (OR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4458 def : Pat<(parallel (X86or_flag GR32:$src1, i32immSExt8:$src2),
4459 (implicit EFLAGS)),
4460 (OR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4461
4462 // Memory-Register Or with EFLAGS result
4463 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), GR8:$src2),
4464 addr:$dst),
4465 (implicit EFLAGS)),
4466 (OR8mr addr:$dst, GR8:$src2)>;
4467 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), GR16:$src2),
4468 addr:$dst),
4469 (implicit EFLAGS)),
4470 (OR16mr addr:$dst, GR16:$src2)>;
4471 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), GR32:$src2),
4472 addr:$dst),
4473 (implicit EFLAGS)),
4474 (OR32mr addr:$dst, GR32:$src2)>;
4475
4476 // Memory-Integer Or with EFLAGS result
4477 def : Pat<(parallel (store (X86or_flag (loadi8 addr:$dst), imm:$src2),
4478 addr:$dst),
4479 (implicit EFLAGS)),
4480 (OR8mi addr:$dst, imm:$src2)>;
4481 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), imm:$src2),
4482 addr:$dst),
4483 (implicit EFLAGS)),
4484 (OR16mi addr:$dst, imm:$src2)>;
4485 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), imm:$src2),
4486 addr:$dst),
4487 (implicit EFLAGS)),
4488 (OR32mi addr:$dst, imm:$src2)>;
4489 def : Pat<(parallel (store (X86or_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4490 addr:$dst),
4491 (implicit EFLAGS)),
4492 (OR16mi8 addr:$dst, i16immSExt8:$src2)>;
4493 def : Pat<(parallel (store (X86or_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4494 addr:$dst),
4495 (implicit EFLAGS)),
4496 (OR32mi8 addr:$dst, i32immSExt8:$src2)>;
4497
4498 // Register-Register XOr with EFLAGS result
4499 def : Pat<(parallel (X86xor_flag GR8:$src1, GR8:$src2),
4500 (implicit EFLAGS)),
4501 (XOR8rr GR8:$src1, GR8:$src2)>;
4502 def : Pat<(parallel (X86xor_flag GR16:$src1, GR16:$src2),
4503 (implicit EFLAGS)),
4504 (XOR16rr GR16:$src1, GR16:$src2)>;
4505 def : Pat<(parallel (X86xor_flag GR32:$src1, GR32:$src2),
4506 (implicit EFLAGS)),
4507 (XOR32rr GR32:$src1, GR32:$src2)>;
4508
4509 // Register-Memory XOr with EFLAGS result
4510 def : Pat<(parallel (X86xor_flag GR8:$src1, (loadi8 addr:$src2)),
4511 (implicit EFLAGS)),
4512 (XOR8rm GR8:$src1, addr:$src2)>;
4513 def : Pat<(parallel (X86xor_flag GR16:$src1, (loadi16 addr:$src2)),
4514 (implicit EFLAGS)),
4515 (XOR16rm GR16:$src1, addr:$src2)>;
4516 def : Pat<(parallel (X86xor_flag GR32:$src1, (loadi32 addr:$src2)),
4517 (implicit EFLAGS)),
4518 (XOR32rm GR32:$src1, addr:$src2)>;
4519
4520 // Register-Integer XOr with EFLAGS result
4521 def : Pat<(parallel (X86xor_flag GR8:$src1, imm:$src2),
4522 (implicit EFLAGS)),
4523 (XOR8ri GR8:$src1, imm:$src2)>;
4524 def : Pat<(parallel (X86xor_flag GR16:$src1, imm:$src2),
4525 (implicit EFLAGS)),
4526 (XOR16ri GR16:$src1, imm:$src2)>;
4527 def : Pat<(parallel (X86xor_flag GR32:$src1, imm:$src2),
4528 (implicit EFLAGS)),
4529 (XOR32ri GR32:$src1, imm:$src2)>;
4530 def : Pat<(parallel (X86xor_flag GR16:$src1, i16immSExt8:$src2),
4531 (implicit EFLAGS)),
4532 (XOR16ri8 GR16:$src1, i16immSExt8:$src2)>;
4533 def : Pat<(parallel (X86xor_flag GR32:$src1, i32immSExt8:$src2),
4534 (implicit EFLAGS)),
4535 (XOR32ri8 GR32:$src1, i32immSExt8:$src2)>;
4536
4537 // Memory-Register XOr with EFLAGS result
4538 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), GR8:$src2),
4539 addr:$dst),
4540 (implicit EFLAGS)),
4541 (XOR8mr addr:$dst, GR8:$src2)>;
4542 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), GR16:$src2),
4543 addr:$dst),
4544 (implicit EFLAGS)),
4545 (XOR16mr addr:$dst, GR16:$src2)>;
4546 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), GR32:$src2),
4547 addr:$dst),
4548 (implicit EFLAGS)),
4549 (XOR32mr addr:$dst, GR32:$src2)>;
4550
4551 // Memory-Integer XOr with EFLAGS result
4552 def : Pat<(parallel (store (X86xor_flag (loadi8 addr:$dst), imm:$src2),
4553 addr:$dst),
4554 (implicit EFLAGS)),
4555 (XOR8mi addr:$dst, imm:$src2)>;
4556 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), imm:$src2),
4557 addr:$dst),
4558 (implicit EFLAGS)),
4559 (XOR16mi addr:$dst, imm:$src2)>;
4560 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), imm:$src2),
4561 addr:$dst),
4562 (implicit EFLAGS)),
4563 (XOR32mi addr:$dst, imm:$src2)>;
4564 def : Pat<(parallel (store (X86xor_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4565 addr:$dst),
4566 (implicit EFLAGS)),
4567 (XOR16mi8 addr:$dst, i16immSExt8:$src2)>;
4568 def : Pat<(parallel (store (X86xor_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4569 addr:$dst),
4570 (implicit EFLAGS)),
4571 (XOR32mi8 addr:$dst, i32immSExt8:$src2)>;
4572
4573 // Register-Register And with EFLAGS result
4574 def : Pat<(parallel (X86and_flag GR8:$src1, GR8:$src2),
4575 (implicit EFLAGS)),
4576 (AND8rr GR8:$src1, GR8:$src2)>;
4577 def : Pat<(parallel (X86and_flag GR16:$src1, GR16:$src2),
4578 (implicit EFLAGS)),
4579 (AND16rr GR16:$src1, GR16:$src2)>;
4580 def : Pat<(parallel (X86and_flag GR32:$src1, GR32:$src2),
4581 (implicit EFLAGS)),
4582 (AND32rr GR32:$src1, GR32:$src2)>;
4583
4584 // Register-Memory And with EFLAGS result
4585 def : Pat<(parallel (X86and_flag GR8:$src1, (loadi8 addr:$src2)),
4586 (implicit EFLAGS)),
4587 (AND8rm GR8:$src1, addr:$src2)>;
4588 def : Pat<(parallel (X86and_flag GR16:$src1, (loadi16 addr:$src2)),
4589 (implicit EFLAGS)),
4590 (AND16rm GR16:$src1, addr:$src2)>;
4591 def : Pat<(parallel (X86and_flag GR32:$src1, (loadi32 addr:$src2)),
4592 (implicit EFLAGS)),
4593 (AND32rm GR32:$src1, addr:$src2)>;
4594
4595 // Register-Integer And with EFLAGS result
4596 def : Pat<(parallel (X86and_flag GR8:$src1, imm:$src2),
4597 (implicit EFLAGS)),
4598 (AND8ri GR8:$src1, imm:$src2)>;
4599 def : Pat<(parallel (X86and_flag GR16:$src1, imm:$src2),
4600 (implicit EFLAGS)),
4601 (AND16ri GR16:$src1, imm:$src2)>;
4602 def : Pat<(parallel (X86and_flag GR32:$src1, imm:$src2),
4603 (implicit EFLAGS)),
4604 (AND32ri GR32:$src1, imm:$src2)>;
4605 def : Pat<(parallel (X86and_flag GR16:$src1, i16immSExt8:$src2),
4606 (implicit EFLAGS)),
4607 (AND16ri8 GR16:$src1, i16immSExt8:$src2)>;
4608 def : Pat<(parallel (X86and_flag GR32:$src1, i32immSExt8:$src2),
4609 (implicit EFLAGS)),
4610 (AND32ri8 GR32:$src1, i32immSExt8:$src2)>;
4611
4612 // Memory-Register And with EFLAGS result
4613 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), GR8:$src2),
4614 addr:$dst),
4615 (implicit EFLAGS)),
4616 (AND8mr addr:$dst, GR8:$src2)>;
4617 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), GR16:$src2),
4618 addr:$dst),
4619 (implicit EFLAGS)),
4620 (AND16mr addr:$dst, GR16:$src2)>;
4621 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), GR32:$src2),
4622 addr:$dst),
4623 (implicit EFLAGS)),
4624 (AND32mr addr:$dst, GR32:$src2)>;
4625
4626 // Memory-Integer And with EFLAGS result
4627 def : Pat<(parallel (store (X86and_flag (loadi8 addr:$dst), imm:$src2),
4628 addr:$dst),
4629 (implicit EFLAGS)),
4630 (AND8mi addr:$dst, imm:$src2)>;
4631 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), imm:$src2),
4632 addr:$dst),
4633 (implicit EFLAGS)),
4634 (AND16mi addr:$dst, imm:$src2)>;
4635 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), imm:$src2),
4636 addr:$dst),
4637 (implicit EFLAGS)),
4638 (AND32mi addr:$dst, imm:$src2)>;
4639 def : Pat<(parallel (store (X86and_flag (loadi16 addr:$dst), i16immSExt8:$src2),
4640 addr:$dst),
4641 (implicit EFLAGS)),
4642 (AND16mi8 addr:$dst, i16immSExt8:$src2)>;
4643 def : Pat<(parallel (store (X86and_flag (loadi32 addr:$dst), i32immSExt8:$src2),
4644 addr:$dst),
4645 (implicit EFLAGS)),
4646 (AND32mi8 addr:$dst, i32immSExt8:$src2)>;
4647
44204648 // -disable-16bit support.
44214649 def : Pat<(truncstorei16 (i32 imm:$src), addr:$dst),
44224650 (MOV16mi addr:$dst, imm:$src)>;
None ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edx}
0 ; RUN: llc < %s -relocation-model=pic -disable-fp-elim -mtriple=i386-apple-darwin | grep {andl.*7.*edi}
11
22 %struct.XXDActiveTextureTargets = type { i64, i64, i64, i64, i64, i64 }
33 %struct.XXDAlphaTest = type { float, i16, i8, i8 }
0 ; RUN: llc < %s -march=x86 | FileCheck %s
1
2 ; LLVM should omit the testl and use the flags result from the orl.
3
4 ; CHECK: or:
5 define void @or(float* %A, i32 %IA, i32 %N) nounwind {
6 entry:
7 %0 = ptrtoint float* %A to i32 ; [#uses=1]
8 %1 = and i32 %0, 3 ; [#uses=1]
9 %2 = xor i32 %IA, 1 ; [#uses=1]
10 ; CHECK: orl %ecx, %edx
11 ; CHECK-NEXT: je .LBB1_2
12 %3 = or i32 %2, %1 ; [#uses=1]
13 %4 = icmp eq i32 %3, 0 ; [#uses=1]
14 br i1 %4, label %return, label %bb
15
16 bb: ; preds = %entry
17 store float 0.000000e+00, float* %A, align 4
18 ret void
19
20 return: ; preds = %entry
21 ret void
22 }
23 ; CHECK: xor:
24 define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
25 entry:
26 %0 = ptrtoint float* %A to i32 ; [#uses=1]
27 %1 = and i32 %0, 3 ; [#uses=1]
28 ; CHECK: xorl $1, %e
29 ; CHECK-NEXT: je .LBB2_2
30 %2 = xor i32 %IA, 1 ; [#uses=1]
31 %3 = xor i32 %2, %1 ; [#uses=1]
32 %4 = icmp eq i32 %3, 0 ; [#uses=1]
33 br i1 %4, label %return, label %bb
34
35 bb: ; preds = %entry
36 store float 0.000000e+00, float* %A, align 4
37 ret void
38
39 return: ; preds = %entry
40 ret void
41 }
42 ; CHECK: and:
43 define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
44 entry:
45 store i8 0, i8* %p
46 %0 = ptrtoint float* %A to i32 ; [#uses=1]
47 %1 = and i32 %0, 3 ; [#uses=1]
48 %2 = xor i32 %IA, 1 ; [#uses=1]
49 ; CHECK: andl $3, %
50 ; CHECK-NEXT: movb %
51 ; CHECK-NEXT: je .LBB3_2
52 %3 = and i32 %2, %1 ; [#uses=1]
53 %t = trunc i32 %3 to i8
54 store i8 %t, i8* %p
55 %4 = icmp eq i32 %3, 0 ; [#uses=1]
56 br i1 %4, label %return, label %bb
57
58 bb: ; preds = %entry
59 store float 0.000000e+00, float* null, align 4
60 ret void
61
62 return: ; preds = %entry
63 ret void
64 }
65
66 ; Just like @and, but without the trunc+store. This should use a testl
67 ; instead of an andl.
68 ; CHECK: test:
69 define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
70 entry:
71 store i8 0, i8* %p
72 %0 = ptrtoint float* %A to i32 ; [#uses=1]
73 %1 = and i32 %0, 3 ; [#uses=1]
74 %2 = xor i32 %IA, 1 ; [#uses=1]
75 ; CHECK: testb $3, %
76 ; CHECK-NEXT: je .LBB4_2
77 %3 = and i32 %2, %1 ; [#uses=1]
78 %4 = icmp eq i32 %3, 0 ; [#uses=1]
79 br i1 %4, label %return, label %bb
80
81 bb: ; preds = %entry
82 store float 0.000000e+00, float* null, align 4
83 ret void
84
85 return: ; preds = %entry
86 ret void
87 }
0 ; RUN: llc < %s -mtriple=x86_64-apple-darwin10 -relocation-model=pic -disable-fp-elim -color-ss-with-regs -stats -info-output-file - > %t
1 ; RUN: grep stackcoloring %t | grep "loads eliminated"
2 ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 5
3 ; RUN: grep asm-printer %t | grep 181
1 ; RUN: grep stackcoloring %t | grep "stack slot refs replaced with reg refs" | grep 8
2 ; RUN: grep asm-printer %t | grep 182
43
54 type { [62 x %struct.Bitvec*] } ; type %0
65 type { i8* } ; type %1