llvm.org GIT mirror llvm / e1d4a88
Make branch heavy code for generating marked up disassembly simpler and easier to read by adding a couple helper functions. Suggestion by Chandler Carruth and seconded by Meador Inge! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166515 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 7 years ago
4 changed file(s) with 185 addition(s) and 343 deletion(s). Raw diff Collapse all Expand all
6565
6666 bool getUseMarkup() const { return UseMarkup; }
6767 void setUseMarkup(bool Value) { UseMarkup = Value; }
68
69 /// Utility functions to make adding mark ups simpler.
70 StringRef markup(StringRef s) const;
71 StringRef markup(StringRef a, StringRef b) const;
6872 };
6973
7074 } // namespace llvm
3535 OS << " " << MAI.getCommentString() << " " << Annot;
3636 }
3737 }
38
39 /// Utility functions to make adding mark ups simpler.
40 StringRef MCInstPrinter::markup(StringRef s) const {
41 if (getUseMarkup())
42 return s;
43 else
44 return "";
45 }
46 StringRef MCInstPrinter::markup(StringRef a, StringRef b) const {
47 if (getUseMarkup())
48 return a;
49 else
50 return b;
51 }
4646 assert (!(ShOpc == ARM_AM::ror && !ShImm) && "Cannot have ror #0");
4747 O << getShiftOpcStr(ShOpc);
4848
49 if (ShOpc != ARM_AM::rrx){
49 if (ShOpc != ARM_AM::rrx) {
5050 O << " ";
5151 if (UseMarkup)
5252 O << "
6666 }
6767
6868 void ARMInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
69 if (UseMarkup)
70 OS << "
71 OS << getRegisterName(RegNo);
72 if (UseMarkup)
73 OS << ">";
69 OS << markup("
70 << getRegisterName(RegNo)
71 << markup(">");
7472 }
7573
7674 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
142140 return;
143141 }
144142
145 O << ", ";
146 if (UseMarkup)
147 O << "
148 O << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
149 if (UseMarkup)
150 O << ">";
143 O << ", "
144 << markup("
145 << "#" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()))
146 << markup(">");
151147 printAnnotation(O, Annot);
152148 return;
153149 }
266262 unsigned Reg = Op.getReg();
267263 printRegName(O, Reg);
268264 } else if (Op.isImm()) {
269 if (UseMarkup)
270 O << "
271 O << '#' << Op.getImm();
272 if (UseMarkup)
273 O << ">";
265 O << markup("
266 << '#' << Op.getImm()
267 << markup(">");
274268 } else {
275269 assert(Op.isExpr() && "unknown operand kind in printOperand");
276270 // If a symbolic branch target was added as a constant expression then print
294288 if (MO1.isExpr())
295289 O << *MO1.getExpr();
296290 else if (MO1.isImm()) {
297 if (UseMarkup)
298 O << "
299 O << "[pc, ";
300 if (UseMarkup)
301 O << "
302 O << "#";
303 O << MO1.getImm();
304 if (UseMarkup)
305 O << ">";
306 O << "]";
307 if (UseMarkup)
308 O << ">";
291 O << markup("
292 << markup("
293 << markup(">]>", "]");
309294 }
310295 else
311296 llvm_unreachable("Unknown LDR label operand?");
358343 const MCOperand &MO2 = MI->getOperand(Op+1);
359344 const MCOperand &MO3 = MI->getOperand(Op+2);
360345
361 if (UseMarkup)
362 O << "
363 O << "[";
346 O << markup(""[";
364347 printRegName(O, MO1.getReg());
365348
366349 if (!MO2.getReg()) {
367350 if (ARM_AM::getAM2Offset(MO3.getImm())) { // Don't print +0.
368 O << ", ";
369 if (UseMarkup)
370 O << "
371 O << "#";
372 O << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()));
373 O << ARM_AM::getAM2Offset(MO3.getImm());
374 if (UseMarkup)
375 O << ">";
351 O << ", "
352 << markup("
353 << "#"
354 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO3.getImm()))
355 << ARM_AM::getAM2Offset(MO3.getImm())
356 << markup(">");
376357 }
377 O << "]";
378 if (UseMarkup)
379 O << ">";
358 O << "]" << markup(">");
380359 return;
381360 }
382361
386365
387366 printRegImmShift(O, ARM_AM::getAM2ShiftOpc(MO3.getImm()),
388367 ARM_AM::getAM2Offset(MO3.getImm()), UseMarkup);
389 O << "]";
390 if (UseMarkup)
391 O << ">";
368 O << "]" << markup(">");
392369 }
393370
394371 void ARMInstPrinter::printAddrModeTBB(const MCInst *MI, unsigned Op,
395372 raw_ostream &O) {
396373 const MCOperand &MO1 = MI->getOperand(Op);
397374 const MCOperand &MO2 = MI->getOperand(Op+1);
398 if (UseMarkup)
399 O << "
400 O << "[";
375 O << markup(""[";
401376 printRegName(O, MO1.getReg());
402377 O << ", ";
403378 printRegName(O, MO2.getReg());
404 O << "]";
405 if (UseMarkup)
406 O << ">";
379 O << "]" << markup(">");
407380 }
408381
409382 void ARMInstPrinter::printAddrModeTBH(const MCInst *MI, unsigned Op,
410383 raw_ostream &O) {
411384 const MCOperand &MO1 = MI->getOperand(Op);
412385 const MCOperand &MO2 = MI->getOperand(Op+1);
413 if (UseMarkup)
414 O << "
415 O << "[";
386 O << markup(""[";
416387 printRegName(O, MO1.getReg());
417388 O << ", ";
418389 printRegName(O, MO2.getReg());
419 O << ", lsl ";
420 if (UseMarkup)
421 O << "
422 O << "#1";
423 if (UseMarkup)
424 O << ">";
425 O << "]";
426 if (UseMarkup)
427 O << ">";
390 O << ", lsl " << markup("") << "]" << markup(">");
428391 }
429392
430393 void ARMInstPrinter::printAddrMode2Operand(const MCInst *MI, unsigned Op,
454417
455418 if (!MO1.getReg()) {
456419 unsigned ImmOffs = ARM_AM::getAM2Offset(MO2.getImm());
457 if (UseMarkup)
458 O << "
459 O << '#'
460 << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
461 << ImmOffs;
462 if (UseMarkup)
463 O << ">";
420 O << markup("
421 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM2Op(MO2.getImm()))
422 << ImmOffs
423 << markup(">");
464424 return;
465425 }
466426
481441 const MCOperand &MO2 = MI->getOperand(Op+1);
482442 const MCOperand &MO3 = MI->getOperand(Op+2);
483443
484 if (UseMarkup)
485 O << "
486 O << "[";
487 printRegName(O, MO1.getReg());
488 O << "], ";
489 if (UseMarkup)
490 O << ">";
444 O << markup("";
445 printRegName(O, MO1.getReg());
446 O << "], " << markup(">");
491447
492448 if (MO2.getReg()) {
493449 O << (char)ARM_AM::getAM3Op(MO3.getImm());
496452 }
497453
498454 unsigned ImmOffs = ARM_AM::getAM3Offset(MO3.getImm());
499 if (UseMarkup)
500 O << "
501 O << '#'
455 O << markup("
456 << '#'
502457 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()))
503 << ImmOffs;
504 if (UseMarkup)
505 O << ">";
458 << ImmOffs
459 << markup(">");
506460 }
507461
508462 void ARMInstPrinter::printAM3PreOrOffsetIndexOp(const MCInst *MI, unsigned Op,
511465 const MCOperand &MO2 = MI->getOperand(Op+1);
512466 const MCOperand &MO3 = MI->getOperand(Op+2);
513467
514 if (UseMarkup)
515 O << "
516 O << '[';
468 O << markup("'[';
517469 printRegName(O, MO1.getReg());
518470
519471 if (MO2.getReg()) {
520 O << ", ";
521 O << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
472 O << ", " << getAddrOpcStr(ARM_AM::getAM3Op(MO3.getImm()));
522473 printRegName(O, MO2.getReg());
523 O << ']';
524 if (UseMarkup)
525 O << ">";
474 O << ']' << markup(">");
526475 return;
527476 }
528477
531480 ARM_AM::AddrOpc op = ARM_AM::getAM3Op(MO3.getImm());
532481
533482 if (ImmOffs || (op == ARM_AM::sub)) {
534 O << ", ";
535 if (UseMarkup)
536 O << "
537 O << "#"
483 O << ", "
484 << markup("
485 << "#"
538486 << ARM_AM::getAddrOpcStr(op)
539 << ImmOffs;
540 if (UseMarkup)
541 O << ">";
542 }
543 O << ']';
544 if (UseMarkup)
545 O << ">";
487 << ImmOffs
488 << markup(">");
489 }
490 O << ']' << markup(">");
546491 }
547492
548493 void ARMInstPrinter::printAddrMode3Operand(const MCInst *MI, unsigned Op,
576521 }
577522
578523 unsigned ImmOffs = ARM_AM::getAM3Offset(MO2.getImm());
579 if (UseMarkup)
580 O << "
581 O << '#'
582 << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm()))
583 << ImmOffs;
584 if (UseMarkup)
585 O << ">";
524 O << markup("
525 << '#' << ARM_AM::getAddrOpcStr(ARM_AM::getAM3Op(MO2.getImm())) << ImmOffs
526 << markup(">");
586527 }
587528
588529 void ARMInstPrinter::printPostIdxImm8Operand(const MCInst *MI,
590531 raw_ostream &O) {
591532 const MCOperand &MO = MI->getOperand(OpNum);
592533 unsigned Imm = MO.getImm();
593 if (UseMarkup)
594 O << "
595 O << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff);
596 if (UseMarkup)
597 O << ">";
534 O << markup("
535 << '#' << ((Imm & 256) ? "" : "-") << (Imm & 0xff)
536 << markup(">");
598537 }
599538
600539 void ARMInstPrinter::printPostIdxRegOperand(const MCInst *MI, unsigned OpNum,
611550 raw_ostream &O) {
612551 const MCOperand &MO = MI->getOperand(OpNum);
613552 unsigned Imm = MO.getImm();
614 if (UseMarkup)
615 O << "
616 O << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2);
617 if (UseMarkup)
618 O << ">";
553 O << markup("
554 << '#' << ((Imm & 256) ? "" : "-") << ((Imm & 0xff) << 2)
555 << markup(">");
619556 }
620557
621558
636573 return;
637574 }
638575
639 if (UseMarkup)
640 O << "
641 O << "[";
576 O << markup(""[";
642577 printRegName(O, MO1.getReg());
643578
644579 unsigned ImmOffs = ARM_AM::getAM5Offset(MO2.getImm());
645580 unsigned Op = ARM_AM::getAM5Op(MO2.getImm());
646581 if (ImmOffs || Op == ARM_AM::sub) {
647 O << ", ";
648 if (UseMarkup)
649 O << "
650 O << "#"
582 O << ", "
583 << markup("
584 << "#"
651585 << ARM_AM::getAddrOpcStr(ARM_AM::getAM5Op(MO2.getImm()))
652 << ImmOffs * 4;
653 if (UseMarkup)
654 O << ">";
655 }
656 O << "]";
657 if (UseMarkup)
658 O << ">";
586 << ImmOffs * 4
587 << markup(">");
588 }
589 O << "]" << markup(">");
659590 }
660591
661592 void ARMInstPrinter::printAddrMode6Operand(const MCInst *MI, unsigned OpNum,
663594 const MCOperand &MO1 = MI->getOperand(OpNum);
664595 const MCOperand &MO2 = MI->getOperand(OpNum+1);
665596
666 if (UseMarkup)
667 O << "
668 O << "[";
597 O << markup(""[";
669598 printRegName(O, MO1.getReg());
670599 if (MO2.getImm()) {
671600 // FIXME: Both darwin as and GNU as violate ARM docs here.
672601 O << ", :" << (MO2.getImm() << 3);
673602 }
674 O << "]";
675 if (UseMarkup)
676 O << ">";
603 O << "]" << markup(">");
677604 }
678605
679606 void ARMInstPrinter::printAddrMode7Operand(const MCInst *MI, unsigned OpNum,
680607 raw_ostream &O) {
681608 const MCOperand &MO1 = MI->getOperand(OpNum);
682 if (UseMarkup)
683 O << "
684 O << "[";
685 printRegName(O, MO1.getReg());
686 O << "]";
687 if (UseMarkup)
688 O << ">";
609 O << markup("";
610 printRegName(O, MO1.getReg());
611 O << "]" << markup(">");
689612 }
690613
691614 void ARMInstPrinter::printAddrMode6OffsetOperand(const MCInst *MI,
708631 int32_t lsb = CountTrailingZeros_32(v);
709632 int32_t width = (32 - CountLeadingZeros_32 (v)) - lsb;
710633 assert(MO.isImm() && "Not a valid bf_inv_mask_imm value!");
711 if (UseMarkup)
712 O << "
713 O << '#' << lsb;
714 if (UseMarkup)
715 O << ">";
716 O << ", ";
717 if (UseMarkup)
718 O << "
719 O << '#' << width;
720 if (UseMarkup)
721 O << ">";
634 O << markup("")
635 << ", "
636 << markup("");
722637 }
723638
724639 void ARMInstPrinter::printMemBOption(const MCInst *MI, unsigned OpNum,
733648 bool isASR = (ShiftOp & (1 << 5)) != 0;
734649 unsigned Amt = ShiftOp & 0x1f;
735650 if (isASR) {
736 O << ", asr ";
737 if (UseMarkup)
738 O << "
739 O << "#" << (Amt == 0 ? 32 : Amt);
740 if (UseMarkup)
741 O << ">";
651 O << ", asr "
652 << markup("
653 << "#" << (Amt == 0 ? 32 : Amt)
654 << markup(">");
742655 }
743656 else if (Amt) {
744 O << ", lsl ";
745 if (UseMarkup)
746 O << "
747 O << "#" << Amt;
748 if (UseMarkup)
749 O << ">";
657 O << ", lsl "
658 << markup("
659 << "#" << Amt
660 << markup(">");
750661 }
751662 }
752663
756667 if (Imm == 0)
757668 return;
758669 assert(Imm > 0 && Imm < 32 && "Invalid PKH shift immediate value!");
759 O << ", lsl ";
760 if (UseMarkup)
761 O << "
762 O << "#" << Imm;
763 if (UseMarkup)
764 O << ">";
670 O << ", lsl " << markup("");
765671 }
766672
767673 void ARMInstPrinter::printPKHASRShiftImm(const MCInst *MI, unsigned OpNum,
771677 if (Imm == 0)
772678 Imm = 32;
773679 assert(Imm > 0 && Imm <= 32 && "Invalid PKH shift immediate value!");
774 O << ", asr ";
775 if (UseMarkup)
776 O << "
777 O << "#" << Imm;
778 if (UseMarkup)
779 O << ">";
680 O << ", asr " << markup("");
780681 }
781682
782683 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
958859
959860 int32_t OffImm = (int32_t)MO.getImm();
960861
961 if (UseMarkup)
962 O << ";
862 O << markup(";
963863 if (OffImm == INT32_MIN)
964864 O << "#-0";
965865 else if (OffImm < 0)
966866 O << "#-" << -OffImm;
967867 else
968868 O << "#" << OffImm;
969 if (UseMarkup)
970 O << ">";
869 O << markup(">");
971870 }
972871
973872 void ARMInstPrinter::printThumbS4ImmOperand(const MCInst *MI, unsigned OpNum,
974873 raw_ostream &O) {
975 if (UseMarkup)
976 O << "
977 O << "#" << MI->getOperand(OpNum).getImm() * 4;
978 if (UseMarkup)
979 O << ">";
874 O << markup("
875 << "#" << MI->getOperand(OpNum).getImm() * 4
876 << markup(">");
980877 }
981878
982879 void ARMInstPrinter::printThumbSRImm(const MCInst *MI, unsigned OpNum,
983880 raw_ostream &O) {
984881 unsigned Imm = MI->getOperand(OpNum).getImm();
985 if (UseMarkup)
986 O << "
987 O << "#" << (Imm == 0 ? 32 : Imm);
988 if (UseMarkup)
989 O << ">";
882 O << markup("
883 << "#" << (Imm == 0 ? 32 : Imm)
884 << markup(">");
990885 }
991886
992887 void ARMInstPrinter::printThumbITMask(const MCInst *MI, unsigned OpNum,
1016911 return;
1017912 }
1018913
1019 if (UseMarkup)
1020 O << "
1021 O << "[";
914 O << markup(""[";
1022915 printRegName(O, MO1.getReg());
1023916 if (unsigned RegNum = MO2.getReg()) {
1024917 O << ", ";
1025918 printRegName(O, RegNum);
1026919 }
1027 O << "]";
1028 if (UseMarkup)
1029 O << ">";
920 O << "]" << markup(">");
1030921 }
1031922
1032923 void ARMInstPrinter::printThumbAddrModeImm5SOperand(const MCInst *MI,
1041932 return;
1042933 }
1043934
1044 if (UseMarkup)
1045 O << "
1046 O << "[";
935 O << markup(""[";
1047936 printRegName(O, MO1.getReg());
1048937 if (unsigned ImmOffs = MO2.getImm()) {
1049 O << ", ";
1050 if (UseMarkup)
1051 O << "
1052 O << "#" << ImmOffs * Scale;
1053 if (UseMarkup)
1054 O << ">";
1055 }
1056 O << "]";
1057 if (UseMarkup)
1058 O << ">";
938 O << ", "
939 << markup("
940 << "#" << ImmOffs * Scale
941 << markup(">");
942 }
943 O << "]" << markup(">");
1059944 }
1060945
1061946 void ARMInstPrinter::printThumbAddrModeImm5S1Operand(const MCInst *MI,
1109994 return;
1110995 }
1111996
1112 if (UseMarkup)
1113 O << "
1114 O << "[";
997 O << markup(""[";
1115998 printRegName(O, MO1.getReg());
1116999
11171000 int32_t OffImm = (int32_t)MO2.getImm();
11201003 if (OffImm == INT32_MIN)
11211004 OffImm = 0;
11221005 if (isSub) {
1123 O << ", ";
1124 if (UseMarkup)
1125 O << "
1126 O << "#-" << -OffImm;
1127 if (UseMarkup)
1128 O << ">";
1006 O << ", "
1007 << markup("
1008 << "#-" << -OffImm
1009 << markup(">");
11291010 }
11301011 else if (OffImm > 0) {
1131 O << ", ";
1132 if (UseMarkup)
1133 O << "
1134 O << "#" << OffImm;
1135 if (UseMarkup)
1136 O << ">";
1137 }
1138 O << "]";
1139 if (UseMarkup)
1140 O << ">";
1012 O << ", "
1013 << markup("
1014 << "#" << OffImm
1015 << markup(">");
1016 }
1017 O << "]" << markup(">");
11411018 }
11421019
11431020 void ARMInstPrinter::printT2AddrModeImm8Operand(const MCInst *MI,
11461023 const MCOperand &MO1 = MI->getOperand(OpNum);
11471024 const MCOperand &MO2 = MI->getOperand(OpNum+1);
11481025
1149 if (UseMarkup)
1150 O << "
1151 O << "[";
1026 O << markup(""[";
11521027 printRegName(O, MO1.getReg());
11531028
11541029 int32_t OffImm = (int32_t)MO2.getImm();
11651040 O << "#" << OffImm;
11661041 if (OffImm != 0 && UseMarkup)
11671042 O << ">";
1168 O << "]";
1169 if (UseMarkup)
1170 O << ">";
1043 O << "]" << markup(">");
11711044 }
11721045
11731046 void ARMInstPrinter::printT2AddrModeImm8s4Operand(const MCInst *MI,
11811054 return;
11821055 }
11831056
1184 if (UseMarkup)
1185 O << "
1186 O << "[";
1057 O << markup(""[";
11871058 printRegName(O, MO1.getReg());
11881059
11891060 int32_t OffImm = (int32_t)MO2.getImm();
12031074 O << "#" << OffImm;
12041075 if (OffImm != 0 && UseMarkup)
12051076 O << ">";
1206 O << "]";
1207 if (UseMarkup)
1208 O << ">";
1077 O << "]" << markup(">");
12091078 }
12101079
12111080 void ARMInstPrinter::printT2AddrModeImm0_1020s4Operand(const MCInst *MI,
12141083 const MCOperand &MO1 = MI->getOperand(OpNum);
12151084 const MCOperand &MO2 = MI->getOperand(OpNum+1);
12161085
1217 if (UseMarkup)
1218 O << "
1219 O << "[";
1086 O << markup(""[";
12201087 printRegName(O, MO1.getReg());
12211088 if (MO2.getImm()) {
1222 O << ", ";
1223 if (UseMarkup)
1224 O << "
1225 O << "#" << MO2.getImm() * 4;
1226 if (UseMarkup)
1227 O << ">";
1228 }
1229 O << "]";
1230 if (UseMarkup)
1231 O << ">";
1089 O << ", "
1090 << markup("
1091 << "#" << MO2.getImm() * 4
1092 << markup(">");
1093 }
1094 O << "]" << markup(">");
12321095 }
12331096
12341097 void ARMInstPrinter::printT2AddrModeImm8OffsetOperand(const MCInst *MI,
12361099 raw_ostream &O) {
12371100 const MCOperand &MO1 = MI->getOperand(OpNum);
12381101 int32_t OffImm = (int32_t)MO1.getImm();
1239 O << ", ";
1240 if (UseMarkup)
1241 O << ";
1102 O << ", " << markup(";
12421103 if (OffImm < 0)
12431104 O << "#-" << -OffImm;
12441105 else
12451106 O << "#" << OffImm;
1246 if (UseMarkup)
1247 O << ">";
1107 O << markup(">");
12481108 }
12491109
12501110 void ARMInstPrinter::printT2AddrModeImm8s4OffsetOperand(const MCInst *MI,
12771137 const MCOperand &MO2 = MI->getOperand(OpNum+1);
12781138 const MCOperand &MO3 = MI->getOperand(OpNum+2);
12791139
1280 if (UseMarkup)
1281 O << "
1282 O << "[";
1140 O << markup(""[";
12831141 printRegName(O, MO1.getReg());
12841142
12851143 assert(MO2.getReg() && "Invalid so_reg load / store address!");
12891147 unsigned ShAmt = MO3.getImm();
12901148 if (ShAmt) {
12911149 assert(ShAmt <= 3 && "Not a valid Thumb2 addressing mode!");
1292 O << ", lsl ";
1293 if (UseMarkup)
1294 O << "
1295 O << "#" << ShAmt;
1296 if (UseMarkup)
1297 O << ">";
1298 }
1299 O << "]";
1300 if (UseMarkup)
1301 O << ">";
1150 O << ", lsl "
1151 << markup("
1152 << "#" << ShAmt
1153 << markup(">");
1154 }
1155 O << "]" << markup(">");
13021156 }
13031157
13041158 void ARMInstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
13051159 raw_ostream &O) {
13061160 const MCOperand &MO = MI->getOperand(OpNum);
1307 if (UseMarkup)
1308 O << "
1309 O << '#' << ARM_AM::getFPImmFloat(MO.getImm());
1310 if (UseMarkup)
1311 O << ">";
1161 O << markup("
1162 << '#' << ARM_AM::getFPImmFloat(MO.getImm())
1163 << markup(">");
13121164 }
13131165
13141166 void ARMInstPrinter::printNEONModImmOperand(const MCInst *MI, unsigned OpNum,
13161168 unsigned EncodedImm = MI->getOperand(OpNum).getImm();
13171169 unsigned EltBits;
13181170 uint64_t Val = ARM_AM::decodeNEONModImm(EncodedImm, EltBits);
1319 if (UseMarkup)
1320 O << "
1321 O << "#0x";
1171 O << markup("
1172 << "#0x";
13221173 O.write_hex(Val);
1323 if (UseMarkup)
1324 O << ">";
1174 O << markup(">");
13251175 }
13261176
13271177 void ARMInstPrinter::printImmPlusOneOperand(const MCInst *MI, unsigned OpNum,
13281178 raw_ostream &O) {
13291179 unsigned Imm = MI->getOperand(OpNum).getImm();
1330 if (UseMarkup)
1331 O << "
1332 O << "#" << Imm + 1;
1333 if (UseMarkup)
1334 O << ">";
1180 O << markup("
1181 << "#" << Imm + 1
1182 << markup(">");
13351183 }
13361184
13371185 void ARMInstPrinter::printRotImmOperand(const MCInst *MI, unsigned OpNum,
13391187 unsigned Imm = MI->getOperand(OpNum).getImm();
13401188 if (Imm == 0)
13411189 return;
1342 O << ", ror ";
1343 if (UseMarkup)
1344 O << "
1345 O << "#";
1190 O << ", ror "
1191 << markup("
1192 << "#";
13461193 switch (Imm) {
13471194 default: assert (0 && "illegal ror immediate!");
13481195 case 1: O << "8"; break;
13491196 case 2: O << "16"; break;
13501197 case 3: O << "24"; break;
13511198 }
1352 if (UseMarkup)
1353 O << ">";
1199 O << markup(">");
13541200 }
13551201
13561202 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
13571203 raw_ostream &O) {
1358 if (UseMarkup)
1359 O << "
1360 O << "#" << 16 - MI->getOperand(OpNum).getImm();
1361 if (UseMarkup)
1362 O << ">";
1204 O << markup("
1205 << "#" << 16 - MI->getOperand(OpNum).getImm()
1206 << markup(">");
13631207 }
13641208
13651209 void ARMInstPrinter::printFBits32(const MCInst *MI, unsigned OpNum,
13661210 raw_ostream &O) {
1367 if (UseMarkup)
1368 O << "
1369 O << "#" << 32 - MI->getOperand(OpNum).getImm();
1370 if (UseMarkup)
1371 O << ">";
1211 O << markup("
1212 << "#" << 32 - MI->getOperand(OpNum).getImm()
1213 << markup(">");
13721214 }
13731215
13741216 void ARMInstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
13751217 raw_ostream &O) {
1376 if (UseMarkup)
1377 O << "
13781218 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1379 if (UseMarkup)
1380 O << ">";
13811219 }
13821220
13831221 void ARMInstPrinter::printVectorListOne(const MCInst *MI, unsigned OpNum,
3333
3434 void X86ATTInstPrinter::printRegName(raw_ostream &OS,
3535 unsigned RegNo) const {
36 if (UseMarkup)
37 OS << "
38 OS << '%' << getRegisterName(RegNo);
39 if (UseMarkup)
40 OS << ">";
36 OS << markup("
37 << '%' << getRegisterName(RegNo)
38 << markup(">");
4139 }
4240
4341 void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
154152 raw_ostream &O) {
155153 const MCOperand &Op = MI->getOperand(OpNo);
156154 if (Op.isReg()) {
157 if (UseMarkup)
158 O << "
159 O << '%' << getRegisterName(Op.getReg());
160 if (UseMarkup)
161 O << ">";
155 printRegName(O, Op.getReg());
162156 } else if (Op.isImm()) {
163 if (UseMarkup)
164 O << "
165157 // Print X86 immediates as signed values.
166 O << '$' << (int64_t)Op.getImm();
167 if (UseMarkup)
168 O << ">";
158 O << markup("
159 << '$' << (int64_t)Op.getImm()
160 << markup(">");
169161
170162 if (CommentStream && (Op.getImm() > 255 || Op.getImm() < -256))
171163 *CommentStream << format("imm = 0x%" PRIX64 "\n", (uint64_t)Op.getImm());
172164
173165 } else {
174166 assert(Op.isExpr() && "unknown operand kind in printOperand");
175 if (UseMarkup)
176 O << "
177 O << '$' << *Op.getExpr();
178 if (UseMarkup)
179 O << ">";
167 O << markup("
168 << '$' << *Op.getExpr()
169 << markup(">");
180170 }
181171 }
182172
187177 const MCOperand &DispSpec = MI->getOperand(Op+3);
188178 const MCOperand &SegReg = MI->getOperand(Op+4);
189179
190 if (UseMarkup)
191 O << ";
180 O << markup(";
192181
193182 // If this has a segment register, print it.
194183 if (SegReg.getReg()) {
215204 printOperand(MI, Op+2, O);
216205 unsigned ScaleVal = MI->getOperand(Op+1).getImm();
217206 if (ScaleVal != 1) {
218 O << ',';
219 if (UseMarkup)
220 O << "
221 O << ScaleVal;
222 if (UseMarkup)
223 O << ">";
207 O << ','
208 << markup("
209 << ScaleVal
210 << markup(">");
224211 }
225212 }
226213 O << ')';
227214 }
228215
229 if (UseMarkup)
230 O << ">";
231 }
216 O << markup(">");
217 }