llvm.org GIT mirror llvm / e1ad087
CMake: Builds all targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56641 91177308-0d34-0410-b5e6-96231b3b80d8 Oscar Fuentes 10 years ago
17 changed file(s) with 274 addition(s) and 48 deletion(s). Raw diff Collapse all Expand all
1212 set(LLVM_TOOLS_BINARY_DIR ${LLVM_BINARY_DIR}/bin)
1313 set(LLVM_EXAMPLES_BINARY_DIR ${LLVM_BINARY_DIR}/examples)
1414
15 # TODO: Support user-specified targets:
16 set(LLVM_TARGETS_TO_BUILD X86)
15 if( MSVC )
16 set(LLVM_TARGETS_TO_BUILD X86
17 CACHE STRING "Semicolon-separated list of targets to build")
18 else( MSVC )
19 set(LLVM_TARGETS_TO_BUILD
20 Alpha ARM CBackend CellSPU CppBackend IA64 Mips MSIL PIC16 PowerPC Sparc X86
21 CACHE STRING "Semicolon-separated list of targets to build")
22 endif( MSVC )
1723
1824 if( NOT MSVC )
1925 set(CMAKE_CXX_LINK_EXECUTABLE "sh -c \"${CMAKE_CXX_LINK_EXECUTABLE}\"")
95101
96102 include(AddLLVM)
97103 include(AddPartiallyLinkedObject)
104 include(TableGen)
98105
99106 add_subdirectory(lib/Support)
100107 add_subdirectory(lib/System)
128135 add_subdirectory(lib/Linker)
129136 add_subdirectory(lib/Analysis)
130137 add_subdirectory(lib/Analysis/IPA)
131 add_subdirectory(lib/Target/X86)
132 add_subdirectory(lib/Target/X86/AsmPrinter)
138
139 foreach(t ${LLVM_TARGETS_TO_BUILD})
140 message(STATUS "Targeting ${t}")
141 add_subdirectory(lib/Target/${t})
142 if( EXISTS ${CMAKE_SOURCE_DIR}/lib/Target/${t}/AsmPrinter/CMakeLists.txt )
143 add_subdirectory(lib/Target/${t}/AsmPrinter)
144 endif( EXISTS ${CMAKE_SOURCE_DIR}/lib/Target/${t}/AsmPrinter/CMakeLists.txt )
145 endforeach(t)
146
133147 add_subdirectory(lib/ExecutionEngine)
134148 add_subdirectory(lib/ExecutionEngine/Interpreter)
135149 add_subdirectory(lib/ExecutionEngine/JIT)
136150 add_subdirectory(lib/Target)
137151 add_subdirectory(lib/AsmParser)
138152 add_subdirectory(lib/Debugger)
139 # TODO: lib/Target/CBackEnd
140153 add_subdirectory(lib/Archive)
141154
142155 add_subdirectory(tools)
4040 # set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_EXAMPLES_BINARY_DIR})
4141 add_llvm_executable(${name} ${ARGN})
4242 endmacro(add_llvm_example name)
43
44
45 macro(add_llvm_target target_name)
46 if( TABLEGEN_OUTPUT )
47 add_custom_target(${target_name}Table_gen
48 DEPENDS ${TABLEGEN_OUTPUT})
49 add_dependencies(${target_name}Table_gen ${LLVM_COMMON_DEPENDS})
50 endif( TABLEGEN_OUTPUT )
51 include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR})
52 add_partially_linked_object(LLVM${target_name} ${ARGN})
53 if( TABLEGEN_OUTPUT )
54 add_dependencies(LLVM${target_name} ${target_name}Table_gen)
55 endif( TABLEGEN_OUTPUT )
56 endmacro(add_llvm_target)
0 # LLVM_TARGET_DEFINITIONS must contain the name of the .td file to process.
1 # Extra parameters for `tblgen' may come after `ofn' parameter.
2 # Adds the name of the generated file to TABLEGEN_OUTPUT.
3
4 macro(tablegen ofn)
5 add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn}
6 COMMAND tblgen ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR} -I ${CMAKE_SOURCE_DIR}/lib/Target -I ${llvm_include_path} ${CMAKE_CURRENT_SOURCE_DIR}/${LLVM_TARGET_DEFINITIONS} -o ${ofn}
7 DEPENDS tblgen ${CMAKE_CURRENT_SOURCE_DIR}/${LLVM_TARGET_DEFINITIONS}
8 COMMENT "Building ${ofn}..."
9 )
10 set(TABLEGEN_OUTPUT ${TABLEGEN_OUTPUT} ${CMAKE_CURRENT_BINARY_DIR}/${ofn})
11 endmacro(tablegen)
0 set(LLVM_TARGET_DEFINITIONS ARM.td)
1
2 tablegen(ARMGenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(ARMGenRegisterNames.inc -gen-register-enums)
4 tablegen(ARMGenRegisterInfo.inc -gen-register-desc)
5 tablegen(ARMGenInstrNames.inc -gen-instr-enums)
6 tablegen(ARMGenInstrInfo.inc -gen-instr-desc)
7 tablegen(ARMGenCodeEmitter.inc -gen-emitter)
8 tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
9 tablegen(ARMGenDAGISel.inc -gen-dag-isel)
10 tablegen(ARMGenSubtarget.inc -gen-subtarget)
11
12 add_llvm_target(ARM
13 ARMCodeEmitter.cpp
14 ARMConstantIslandPass.cpp
15 ARMConstantPoolValue.cpp
16 ARMInstrInfo.cpp
17 ARMISelDAGToDAG.cpp
18 ARMISelLowering.cpp
19 ARMJITInfo.cpp
20 ARMLoadStoreOptimizer.cpp
21 ARMRegisterInfo.cpp
22 ARMSubtarget.cpp
23 ARMTargetAsmInfo.cpp
24 ARMTargetMachine.cpp
25 )
0 set(LLVM_TARGET_DEFINITIONS Alpha.td)
1
2 tablegen(AlphaGenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(AlphaGenRegisterNames.inc -gen-register-enums)
4 tablegen(AlphaGenRegisterInfo.inc -gen-register-desc)
5 tablegen(AlphaGenInstrNames.inc -gen-instr-enums)
6 tablegen(AlphaGenInstrInfo.inc -gen-instr-desc)
7 tablegen(AlphaGenCodeEmitter.inc -gen-emitter)
8 tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
9 tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
10 tablegen(AlphaGenSubtarget.inc -gen-subtarget)
11
12 add_llvm_target(Alpha
13 AlphaAsmPrinter.cpp
14 AlphaBranchSelector.cpp
15 AlphaCodeEmitter.cpp
16 AlphaInstrInfo.cpp
17 AlphaISelDAGToDAG.cpp
18 AlphaISelLowering.cpp
19 AlphaJITInfo.cpp
20 AlphaLLRP.cpp
21 AlphaRegisterInfo.cpp
22 AlphaSubtarget.cpp
23 AlphaTargetAsmInfo.cpp
24 AlphaTargetMachine.cpp
25 )
0 add_llvm_target(CBackEnd
1 CBackend.cpp
2 )
0 set(LLVM_TARGET_DEFINITIONS SPU.td)
1
2 tablegen(SPUGenInstrNames.inc -gen-instr-enums)
3 tablegen(SPUGenRegisterNames.inc -gen-register-enums)
4 tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
5 tablegen(SPUGenCodeEmitter.inc -gen-emitter)
6 tablegen(SPUGenRegisterInfo.h.inc -gen-register-desc-header)
7 tablegen(SPUGenRegisterInfo.inc -gen-register-desc)
8 tablegen(SPUGenInstrInfo.inc -gen-instr-desc)
9 tablegen(SPUGenDAGISel.inc -gen-dag-isel)
10 tablegen(SPUGenSubtarget.inc -gen-subtarget)
11 tablegen(SPUGenCallingConv.inc -gen-callingconv)
12
13 add_llvm_target(CellSPU
14 SPUAsmPrinter.cpp
15 SPUFrameInfo.cpp
16 SPUHazardRecognizers.cpp
17 SPUInstrInfo.cpp
18 SPUISelDAGToDAG.cpp
19 SPUISelLowering.cpp
20 SPURegisterInfo.cpp
21 SPUSubtarget.cpp
22 SPUTargetAsmInfo.cpp
23 SPUTargetMachine.cpp
24 )
0 add_llvm_target(CppBackend
1 CPPBackend.cpp
2 )
0 set(LLVM_TARGET_DEFINITIONS IA64.td)
1
2 tablegen(IA64GenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(IA64GenRegisterNames.inc -gen-register-enums)
4 tablegen(IA64GenRegisterInfo.inc -gen-register-desc)
5 tablegen(IA64GenInstrNames.inc -gen-instr-enums)
6 tablegen(IA64GenInstrInfo.inc -gen-instr-desc)
7 tablegen(IA64GenAsmWriter.inc -gen-asm-writer)
8 tablegen(IA64GenDAGISel.inc -gen-dag-isel)
9
10 add_llvm_target(IA64
11 IA64AsmPrinter.cpp
12 IA64Bundling.cpp
13 IA64InstrInfo.cpp
14 IA64ISelDAGToDAG.cpp
15 IA64ISelLowering.cpp
16 IA64RegisterInfo.cpp
17 IA64TargetAsmInfo.cpp
18 IA64TargetMachine.cpp
19 )
0 add_llvm_target(MSIL
1 MSILWriter.cpp
2 )
0 set(LLVM_TARGET_DEFINITIONS Mips.td)
1
2 tablegen(MipsGenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(MipsGenRegisterNames.inc -gen-register-enums)
4 tablegen(MipsGenRegisterInfo.inc -gen-register-desc)
5 tablegen(MipsGenInstrNames.inc -gen-instr-enums)
6 tablegen(MipsGenInstrInfo.inc -gen-instr-desc)
7 tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
8 tablegen(MipsGenDAGISel.inc -gen-dag-isel)
9 tablegen(MipsGenCallingConv.inc -gen-callingconv)
10 tablegen(MipsGenSubtarget.inc -gen-subtarget)
11
12 add_llvm_target(Mips
13 MipsAsmPrinter.cpp
14 MipsDelaySlotFiller.cpp
15 MipsInstrInfo.cpp
16 MipsISelDAGToDAG.cpp
17 MipsISelLowering.cpp
18 MipsRegisterInfo.cpp
19 MipsSubtarget.cpp
20 MipsTargetAsmInfo.cpp
21 MipsTargetMachine.cpp
22 )
0 set(LLVM_TARGET_DEFINITIONS PIC16.td)
1
2 tablegen(PIC16GenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(PIC16GenRegisterNames.inc -gen-register-enums)
4 tablegen(PIC16GenRegisterInfo.inc -gen-register-desc)
5 tablegen(PIC16GenInstrNames.inc -gen-instr-enums)
6 tablegen(PIC16GenInstrInfo.inc -gen-instr-desc)
7 tablegen(PIC16GenAsmWriter.inc -gen-asm-writer)
8 tablegen(PIC16GenDAGISel.inc -gen-dag-isel)
9 tablegen(PIC16GenCallingConv.inc -gen-callingconv)
10 tablegen(PIC16GenSubtarget.inc -gen-subtarget)
11
12 add_llvm_target(PIC16
13 PIC16AsmPrinter.cpp
14 PIC16ConstantPoolValue.cpp
15 PIC16InstrInfo.cpp
16 PIC16ISelDAGToDAG.cpp
17 PIC16ISelLowering.cpp
18 PIC16RegisterInfo.cpp
19 PIC16Subtarget.cpp
20 PIC16TargetAsmInfo.cpp
21 PIC16TargetMachine.cpp
22 )
0 include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
1
2 add_llvm_library(LLVMPowerPCAsmPrinter
3 PPCAsmPrinter.cpp
4 )
5
6 target_name_of_partially_linked_object(LLVMPowerPCCodeGen n)
7
8 add_dependencies(LLVMPowerPCAsmPrinter ${n})
0 set(LLVM_TARGET_DEFINITIONS PPC.td)
1
2 tablegen(PPCGenInstrNames.inc -gen-instr-enums)
3 tablegen(PPCGenRegisterNames.inc -gen-register-enums)
4 tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
5 tablegen(PPCGenCodeEmitter.inc -gen-emitter)
6 tablegen(PPCGenRegisterInfo.h.inc -gen-register-desc-header)
7 tablegen(PPCGenRegisterInfo.inc -gen-register-desc)
8 tablegen(PPCGenInstrInfo.inc -gen-instr-desc)
9 tablegen(PPCGenDAGISel.inc -gen-dag-isel)
10 tablegen(PPCGenCallingConv.inc -gen-callingconv)
11 tablegen(PPCGenSubtarget.inc -gen-subtarget)
12
13 add_llvm_target(PowerPCCodeGen
14 PPCBranchSelector.cpp
15 PPCCodeEmitter.cpp
16 PPCHazardRecognizers.cpp
17 PPCInstrInfo.cpp
18 PPCISelDAGToDAG.cpp
19 PPCISelLowering.cpp
20 PPCJITInfo.cpp
21 PPCMachOWriterInfo.cpp
22 PPCPredicates.cpp
23 PPCRegisterInfo.cpp
24 PPCSubtarget.cpp
25 PPCTargetAsmInfo.cpp
26 PPCTargetMachine.cpp
27 )
0 set(LLVM_TARGET_DEFINITIONS Sparc.td)
1
2 tablegen(SparcGenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(SparcGenRegisterNames.inc -gen-register-enums)
4 tablegen(SparcGenRegisterInfo.inc -gen-register-desc)
5 tablegen(SparcGenInstrNames.inc -gen-instr-enums)
6 tablegen(SparcGenInstrInfo.inc -gen-instr-desc)
7 tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
8 tablegen(SparcGenDAGISel.inc -gen-dag-isel)
9 tablegen(SparcGenSubtarget.inc -gen-subtarget)
10 tablegen(SparcGenCallingConv.inc -gen-callingconv)
11
12 add_llvm_target(Sparc
13 DelaySlotFiller.cpp
14 FPMover.cpp
15 SparcAsmPrinter.cpp
16 SparcInstrInfo.cpp
17 SparcISelDAGToDAG.cpp
18 SparcISelLowering.cpp
19 SparcRegisterInfo.cpp
20 SparcSubtarget.cpp
21 SparcTargetAsmInfo.cpp
22 SparcTargetMachine.cpp
23 )
None macro(x86tgen ofn)
1 add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn}
2 COMMAND tblgen ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR} -I ${CMAKE_SOURCE_DIR}/lib/Target -I ${llvm_include_path} ${CMAKE_CURRENT_SOURCE_DIR}/X86.td -o ${ofn}
3 DEPENDS tblgen ${CMAKE_CURRENT_SOURCE_DIR}/X86.td
4 COMMENT "Building ${ofn}..."
5 )
6 endmacro(x86tgen)
0 set(LLVM_TARGET_DEFINITIONS X86.td)
71
8 x86tgen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
9 x86tgen(X86GenRegisterNames.inc -gen-register-enums)
10 x86tgen(X86GenRegisterInfo.inc -gen-register-desc)
11 x86tgen(X86GenInstrNames.inc -gen-instr-enums)
12 x86tgen(X86GenInstrInfo.inc -gen-instr-desc)
13 x86tgen(X86GenAsmWriter.inc -gen-asm-writer)
14 x86tgen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
15 x86tgen(X86GenDAGISel.inc -gen-dag-isel)
16 x86tgen(X86GenFastISel.inc -gen-fast-isel)
17 x86tgen(X86GenCallingConv.inc -gen-callingconv)
18 x86tgen(X86GenSubtarget.inc -gen-subtarget)
2 tablegen(X86GenRegisterInfo.h.inc -gen-register-desc-header)
3 tablegen(X86GenRegisterNames.inc -gen-register-enums)
4 tablegen(X86GenRegisterInfo.inc -gen-register-desc)
5 tablegen(X86GenInstrNames.inc -gen-instr-enums)
6 tablegen(X86GenInstrInfo.inc -gen-instr-desc)
7 tablegen(X86GenAsmWriter.inc -gen-asm-writer)
8 tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
9 tablegen(X86GenDAGISel.inc -gen-dag-isel)
10 tablegen(X86GenFastISel.inc -gen-fast-isel)
11 tablegen(X86GenCallingConv.inc -gen-callingconv)
12 tablegen(X86GenSubtarget.inc -gen-subtarget)
1913
20 add_custom_target(X86Table_gen echo Tablegenning
21 DEPENDS
22 ${CMAKE_CURRENT_BINARY_DIR}/X86GenRegisterInfo.h.inc
23 ${CMAKE_CURRENT_BINARY_DIR}/X86GenRegisterNames.inc
24 ${CMAKE_CURRENT_BINARY_DIR}/X86GenRegisterInfo.inc
25 ${CMAKE_CURRENT_BINARY_DIR}/X86GenInstrNames.inc
26 ${CMAKE_CURRENT_BINARY_DIR}/X86GenInstrInfo.inc
27 ${CMAKE_CURRENT_BINARY_DIR}/X86GenAsmWriter.inc
28 ${CMAKE_CURRENT_BINARY_DIR}/X86GenAsmWriter1.inc
29 ${CMAKE_CURRENT_BINARY_DIR}/X86GenDAGISel.inc
30 ${CMAKE_CURRENT_BINARY_DIR}/X86GenFastISel.inc
31 ${CMAKE_CURRENT_BINARY_DIR}/X86GenCallingConv.inc
32 ${CMAKE_CURRENT_BINARY_DIR}/X86GenSubtarget.inc
33 )
34
35 add_dependencies(X86Table_gen ${LLVM_COMMON_DEPENDS})
36
37 include_directories(BEFORE ${CMAKE_CURRENT_BINARY_DIR})
38
39 add_partially_linked_object(LLVMX86CodeGen
14 add_llvm_target(X86CodeGen
4015 X86CodeEmitter.cpp
4116 X86ELFWriterInfo.cpp
4217 X86FloatingPoint.cpp
5025 X86TargetMachine.cpp
5126 X86FastISel.cpp
5227 )
53
54 add_dependencies(LLVMX86CodeGen
55 X86Table_gen
56 )
3939 message(FATAL_ERROR "Failed to execute ${config_guess}")
4040 endif( NOT TT_RV EQUAL 0 )
4141 set(target ${LLVM_TARGET_TRIPLET})
42 set(TARGETS_TO_BUILD "X86") # TODO
42 foreach(c ${LLVM_TARGETS_TO_BUILD})
43 set(TARGETS_BUILT "${TARGETS_BUILT} ${c}")
44 endforeach(c)
45 set(TARGETS_TO_BUILD ${TARGETS_BUILT})
4346 set(TARGET_HAS_JIT "1") # TODO
4447
4548 # Avoids replacement at config-time: