llvm.org GIT mirror llvm / e132a1a
[Pass Pipeline][NFC] Add a test prior to committing D61726 This patch just adds a test case to show the differences in code emitted by opt before and after https://reviews.llvm.org/D61726. Previous attempt to commit this did not include the registered target requirement so it caused buildbot breaks. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360620 91177308-0d34-0410-b5e6-96231b3b80d8 Nemanja Ivanovic 4 months ago
1 changed file(s) with 155 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; REQUIRES: powerpc-registered-target
2 ; RUN: opt -mtriple=powerpc64le-unknown-unknown -O2 -S < %s | FileCheck %s
3 ; RUN: opt -mtriple=powerpc64le-unknown-unknown -passes='default' -S < %s \
4 ; RUN: | FileCheck %s --check-prefix=NPM
5
6 target datalayout = "e-m:e-i64:64-n32:64"
7 target triple = "powerpc64le-unknown-linux-gnu"
8
9 define dso_local i64 @func(i64 %blah, i64 %limit) #0 {
10 ; CHECK-LABEL: @func(
11 ; CHECK-NEXT: entry:
12 ; CHECK-NEXT: [[CMP4:%.*]] = icmp eq i64 [[LIMIT:%.*]], 0
13 ; CHECK-NEXT: br i1 [[CMP4]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]]
14 ; CHECK: for.body.lr.ph:
15 ; CHECK-NEXT: [[CONV:%.*]] = and i64 [[BLAH:%.*]], 4294967295
16 ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[LIMIT]], -1
17 ; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[LIMIT]], 7
18 ; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 7
19 ; CHECK-NEXT: br i1 [[TMP1]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY_LR_PH_NEW:%.*]]
20 ; CHECK: for.body.lr.ph.new:
21 ; CHECK-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[LIMIT]], [[XTRAITER]]
22 ; CHECK-NEXT: br label [[FOR_BODY:%.*]]
23 ; CHECK: for.cond.cleanup.loopexit.unr-lcssa:
24 ; CHECK-NEXT: [[ADD_LCSSA_PH:%.*]] = phi i64 [ undef, [[FOR_BODY_LR_PH]] ], [ [[ADD_7:%.*]], [[FOR_BODY]] ]
25 ; CHECK-NEXT: [[K_05_UNR:%.*]] = phi i64 [ 1, [[FOR_BODY_LR_PH]] ], [ [[AND:%.*]], [[FOR_BODY]] ]
26 ; CHECK-NEXT: [[LCMP_MOD:%.*]] = icmp eq i64 [[XTRAITER]], 0
27 ; CHECK-NEXT: br i1 [[LCMP_MOD]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL:%.*]]
28 ; CHECK: for.body.epil:
29 ; CHECK-NEXT: [[G_06_EPIL:%.*]] = phi i64 [ [[ADD_EPIL:%.*]], [[FOR_BODY_EPIL]] ], [ [[ADD_LCSSA_PH]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
30 ; CHECK-NEXT: [[K_05_EPIL:%.*]] = phi i64 [ [[AND_EPIL:%.*]], [[FOR_BODY_EPIL]] ], [ [[K_05_UNR]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
31 ; CHECK-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ [[EPIL_ITER_SUB:%.*]], [[FOR_BODY_EPIL]] ], [ [[XTRAITER]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
32 ; CHECK-NEXT: [[AND_EPIL]] = and i64 [[CONV]], [[K_05_EPIL]]
33 ; CHECK-NEXT: [[ADD_EPIL]] = add i64 [[AND_EPIL]], [[G_06_EPIL]]
34 ; CHECK-NEXT: [[EPIL_ITER_SUB]] = add i64 [[EPIL_ITER]], -1
35 ; CHECK-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp eq i64 [[EPIL_ITER_SUB]], 0
36 ; CHECK-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL]], !llvm.loop !0
37 ; CHECK: for.cond.cleanup:
38 ; CHECK-NEXT: [[G_0_LCSSA:%.*]] = phi i64 [ undef, [[ENTRY:%.*]] ], [ [[ADD_LCSSA_PH]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ], [ [[ADD_EPIL]], [[FOR_BODY_EPIL]] ]
39 ; CHECK-NEXT: ret i64 [[G_0_LCSSA]]
40 ; CHECK: for.body:
41 ; CHECK-NEXT: [[G_06:%.*]] = phi i64 [ undef, [[FOR_BODY_LR_PH_NEW]] ], [ [[ADD_7]], [[FOR_BODY]] ]
42 ; CHECK-NEXT: [[K_05:%.*]] = phi i64 [ 1, [[FOR_BODY_LR_PH_NEW]] ], [ [[AND]], [[FOR_BODY]] ]
43 ; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ [[UNROLL_ITER]], [[FOR_BODY_LR_PH_NEW]] ], [ [[NITER_NSUB_7:%.*]], [[FOR_BODY]] ]
44 ; CHECK-NEXT: [[AND]] = and i64 [[CONV]], [[K_05]]
45 ; CHECK-NEXT: [[ADD:%.*]] = add i64 [[AND]], [[G_06]]
46 ; CHECK-NEXT: [[ADD_1:%.*]] = add i64 [[AND]], [[ADD]]
47 ; CHECK-NEXT: [[ADD_2:%.*]] = add i64 [[AND]], [[ADD_1]]
48 ; CHECK-NEXT: [[ADD_3:%.*]] = add i64 [[AND]], [[ADD_2]]
49 ; CHECK-NEXT: [[ADD_4:%.*]] = add i64 [[AND]], [[ADD_3]]
50 ; CHECK-NEXT: [[ADD_5:%.*]] = add i64 [[AND]], [[ADD_4]]
51 ; CHECK-NEXT: [[ADD_6:%.*]] = add i64 [[AND]], [[ADD_5]]
52 ; CHECK-NEXT: [[ADD_7]] = add i64 [[AND]], [[ADD_6]]
53 ; CHECK-NEXT: [[NITER_NSUB_7]] = add i64 [[NITER]], -8
54 ; CHECK-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NSUB_7]], 0
55 ; CHECK-NEXT: br i1 [[NITER_NCMP_7]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY]]
56 ;
57 ; NPM-LABEL: @func(
58 ; NPM-NEXT: entry:
59 ; NPM-NEXT: [[CMP4:%.*]] = icmp eq i64 [[LIMIT:%.*]], 0
60 ; NPM-NEXT: br i1 [[CMP4]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_BODY_LR_PH:%.*]]
61 ; NPM: for.body.lr.ph:
62 ; NPM-NEXT: [[CONV:%.*]] = and i64 [[BLAH:%.*]], 4294967295
63 ; NPM-NEXT: [[TMP0:%.*]] = add i64 [[LIMIT]], -1
64 ; NPM-NEXT: [[XTRAITER:%.*]] = and i64 [[LIMIT]], 7
65 ; NPM-NEXT: [[TMP1:%.*]] = icmp ult i64 [[TMP0]], 7
66 ; NPM-NEXT: br i1 [[TMP1]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA:%.*]], label [[FOR_BODY_LR_PH_NEW:%.*]]
67 ; NPM: for.body.lr.ph.new:
68 ; NPM-NEXT: [[UNROLL_ITER:%.*]] = sub i64 [[LIMIT]], [[XTRAITER]]
69 ; NPM-NEXT: [[AND_0:%.*]] = and i64 [[CONV]], 1
70 ; NPM-NEXT: br label [[FOR_BODY:%.*]]
71 ; NPM: for.cond.cleanup.loopexit.unr-lcssa:
72 ; NPM-NEXT: [[ADD_LCSSA_PH:%.*]] = phi i64 [ undef, [[FOR_BODY_LR_PH]] ], [ [[ADD_7:%.*]], [[FOR_BODY]] ]
73 ; NPM-NEXT: [[K_05_UNR:%.*]] = phi i64 [ 1, [[FOR_BODY_LR_PH]] ], [ [[AND_PHI:%.*]], [[FOR_BODY]] ]
74 ; NPM-NEXT: [[LCMP_MOD:%.*]] = icmp eq i64 [[XTRAITER]], 0
75 ; NPM-NEXT: br i1 [[LCMP_MOD]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL:%.*]]
76 ; NPM: for.body.epil:
77 ; NPM-NEXT: [[G_06_EPIL:%.*]] = phi i64 [ [[ADD_EPIL:%.*]], [[FOR_BODY_EPIL]] ], [ [[ADD_LCSSA_PH]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
78 ; NPM-NEXT: [[K_05_EPIL:%.*]] = phi i64 [ [[AND_EPIL:%.*]], [[FOR_BODY_EPIL]] ], [ [[K_05_UNR]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
79 ; NPM-NEXT: [[EPIL_ITER:%.*]] = phi i64 [ [[EPIL_ITER_SUB:%.*]], [[FOR_BODY_EPIL]] ], [ [[XTRAITER]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ]
80 ; NPM-NEXT: [[AND_EPIL]] = and i64 [[CONV]], [[K_05_EPIL]]
81 ; NPM-NEXT: [[ADD_EPIL]] = add i64 [[AND_EPIL]], [[G_06_EPIL]]
82 ; NPM-NEXT: [[EPIL_ITER_SUB]] = add i64 [[EPIL_ITER]], -1
83 ; NPM-NEXT: [[EPIL_ITER_CMP:%.*]] = icmp eq i64 [[EPIL_ITER_SUB]], 0
84 ; NPM-NEXT: br i1 [[EPIL_ITER_CMP]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_EPIL]], !llvm.loop !0
85 ; NPM: for.cond.cleanup:
86 ; NPM-NEXT: [[G_0_LCSSA:%.*]] = phi i64 [ undef, [[ENTRY:%.*]] ], [ [[ADD_LCSSA_PH]], [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]] ], [ [[ADD_EPIL]], [[FOR_BODY_EPIL]] ]
87 ; NPM-NEXT: ret i64 [[G_0_LCSSA]]
88 ; NPM: for.body:
89 ; NPM-NEXT: [[G_06:%.*]] = phi i64 [ undef, [[FOR_BODY_LR_PH_NEW]] ], [ [[ADD_7]], [[FOR_BODY_FOR_BODY_CRIT_EDGE:%.*]] ]
90 ; NPM-NEXT: [[AND_PHI]] = phi i64 [ [[AND_0]], [[FOR_BODY_LR_PH_NEW]] ], [ [[AND_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ]
91 ; NPM-NEXT: [[NITER:%.*]] = phi i64 [ [[UNROLL_ITER]], [[FOR_BODY_LR_PH_NEW]] ], [ [[NITER_NSUB_7:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ]
92 ; NPM-NEXT: [[ADD:%.*]] = add i64 [[AND_PHI]], [[G_06]]
93 ; NPM-NEXT: [[ADD_1:%.*]] = add i64 [[AND_PHI]], [[ADD]]
94 ; NPM-NEXT: [[ADD_2:%.*]] = add i64 [[AND_PHI]], [[ADD_1]]
95 ; NPM-NEXT: [[ADD_3:%.*]] = add i64 [[AND_PHI]], [[ADD_2]]
96 ; NPM-NEXT: [[ADD_4:%.*]] = add i64 [[AND_PHI]], [[ADD_3]]
97 ; NPM-NEXT: [[ADD_5:%.*]] = add i64 [[AND_PHI]], [[ADD_4]]
98 ; NPM-NEXT: [[ADD_6:%.*]] = add i64 [[AND_PHI]], [[ADD_5]]
99 ; NPM-NEXT: [[ADD_7]] = add i64 [[AND_PHI]], [[ADD_6]]
100 ; NPM-NEXT: [[NITER_NSUB_7]] = add i64 [[NITER]], -8
101 ; NPM-NEXT: [[NITER_NCMP_7:%.*]] = icmp eq i64 [[NITER_NSUB_7]], 0
102 ; NPM-NEXT: br i1 [[NITER_NCMP_7]], label [[FOR_COND_CLEANUP_LOOPEXIT_UNR_LCSSA]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE]]
103 ; NPM: for.body.for.body_crit_edge:
104 ; NPM-NEXT: [[AND_1]] = and i64 [[CONV]], [[AND_PHI]]
105 ; NPM-NEXT: br label [[FOR_BODY]]
106 ;
107 entry:
108 %blah.addr = alloca i64, align 8
109 %limit.addr = alloca i64, align 8
110 %k = alloca i32, align 4
111 %g = alloca i64, align 8
112 %i = alloca i64, align 8
113 store i64 %blah, i64* %blah.addr, align 8
114 store i64 %limit, i64* %limit.addr, align 8
115 store i32 1, i32* %k, align 4
116 store i64 0, i64* %i, align 8
117 br label %for.cond
118
119 for.cond: ; preds = %for.body, %entry
120 %0 = load i64, i64* %i, align 8
121 %1 = load i64, i64* %limit.addr, align 8
122 %cmp = icmp ult i64 %0, %1
123 br i1 %cmp, label %for.body, label %for.cond.cleanup
124
125 for.cond.cleanup: ; preds = %for.cond
126 %2 = load i64, i64* %g, align 8
127 ret i64 %2
128
129 for.body: ; preds = %for.cond
130 %3 = load i64, i64* %blah.addr, align 8
131 %4 = load i32, i32* %k, align 4
132 %conv = zext i32 %4 to i64
133 %and = and i64 %conv, %3
134 %conv1 = trunc i64 %and to i32
135 store i32 %conv1, i32* %k, align 4
136 %5 = load i32, i32* %k, align 4
137 %conv2 = zext i32 %5 to i64
138 %6 = load i64, i64* %g, align 8
139 %add = add i64 %6, %conv2
140 store i64 %add, i64* %g, align 8
141 %7 = load i64, i64* %i, align 8
142 %inc = add i64 %7, 1
143 store i64 %inc, i64* %i, align 8
144 br label %for.cond
145 }
146
147 ; Function Attrs: argmemonly nounwind
148 declare void @llvm.lifetime.start.p0i8(i64 immarg, i8* nocapture) #1
149
150 ; Function Attrs: argmemonly nounwind
151 declare void @llvm.lifetime.end.p0i8(i64 immarg, i8* nocapture) #1
152
153 attributes #0 = { "use-soft-float"="false" }
154 attributes #1 = { argmemonly nounwind }