llvm.org GIT mirror llvm / e0eff38
AMDGPU/GlobalISel: InstrMapping for G_MERGE_VALUES git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@327268 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 2 years ago
3 changed file(s) with 57 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
314314 OpdsMapping[0] = AMDGPU::getValueMapping(BankID, DstSize);
315315 OpdsMapping[1] = AMDGPU::getValueMapping(BankID, SrcSize);
316316 OpdsMapping[2] = nullptr;
317 break;
318 }
319 case AMDGPU::G_MERGE_VALUES: {
320 unsigned Bank = isSALUMapping(MI) ?
321 AMDGPU::SGPRRegBankID : AMDGPU::VGPRRegBankID;
322 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
323 unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
324
325 OpdsMapping[0] = AMDGPU::getValueMapping(Bank, DstSize);
326 // Op1 and Dst should use the same register bank.
327 for (unsigned i = 1, e = MI.getNumOperands(); i != e; ++i)
328 OpdsMapping[i] = AMDGPU::getValueMapping(Bank, SrcSize);
317329 break;
318330 }
319331 case AMDGPU::G_BITCAST: {
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -global-isel %s | FileCheck %s
1 # RUN: llc -mtriple=amdgcn-- -O0 -run-pass=legalizer -global-isel -o - %s | FileCheck %s
22
33 ---
44 name: test_merge_s32_s32_s64
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
2 # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s
3
4 ---
5 name: merge_s32_s32_s64_s
6 legalized: true
7
8 body: |
9 bb.0:
10 liveins: $sgpr0, $sgpr1
11 ; CHECK-LABEL: name: merge_s32_s32_s64_s
12 ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
13 ; CHECK: [[EXTRACT:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 0
14 ; CHECK: [[EXTRACT1:%[0-9]+]]:sgpr(s32) = G_EXTRACT [[COPY]](s64), 32
15 ; CHECK: [[MV:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
16 ; CHECK: S_ENDPGM implicit [[MV]](s64)
17 %0:_(s64) = COPY $sgpr0_sgpr1
18 %1:_(s32) = G_EXTRACT %0, 0
19 %2:_(s32) = G_EXTRACT %0, 32
20 %3:_(s64) = G_MERGE_VALUES %1, %2
21 S_ENDPGM implicit %3
22 ...
23
24 ---
25 name: merge_s32_s32_s64_v
26 legalized: true
27
28 body: |
29 bb.0:
30 liveins: $vgpr0, $vgpr1
31 ; CHECK-LABEL: name: merge_s32_s32_s64_v
32 ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
33 ; CHECK: [[EXTRACT:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 0
34 ; CHECK: [[EXTRACT1:%[0-9]+]]:vgpr(s32) = G_EXTRACT [[COPY]](s64), 32
35 ; CHECK: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[EXTRACT]](s32), [[EXTRACT1]](s32)
36 ; CHECK: S_ENDPGM implicit [[MV]](s64)
37 %0:_(s64) = COPY $vgpr0_vgpr1
38 %1:_(s32) = G_EXTRACT %0, 0
39 %2:_(s32) = G_EXTRACT %0, 32
40 %3:_(s64) = G_MERGE_VALUES %1, %2
41 S_ENDPGM implicit %3
42 ...
43