llvm.org GIT mirror llvm / e0e811c
[AMDGPU] Emit constant address space data in .rodata section and use relocations instead of fixups (amdhsa only) Differential Revision: https://reviews.llvm.org/D25693 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@284759 91177308-0d34-0410-b5e6-96231b3b80d8 Konstantin Zhuravlyov 3 years ago
8 changed file(s) with 94 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
88
99 #include "AMDGPUTargetObjectFile.h"
1010 #include "AMDGPU.h"
11 #include "Utils/AMDGPUBaseInfo.h"
1211 #include "llvm/MC/MCContext.h"
1312 #include "llvm/MC/MCSectionELF.h"
1413 #include "llvm/Support/ELF.h"
14 #include "Utils/AMDGPUBaseInfo.h"
1515
1616 using namespace llvm;
1717
2121
2222 MCSection *AMDGPUTargetObjectFile::SelectSectionForGlobal(
2323 const GlobalValue *GV, SectionKind Kind, const TargetMachine &TM) const {
24 if (Kind.isReadOnly() && AMDGPU::isReadOnlySegment(GV))
24 if (Kind.isReadOnly() && AMDGPU::isReadOnlySegment(GV) &&
25 AMDGPU::shouldEmitConstantsToTextSection(TM.getTargetTriple()))
2526 return TextSection;
2627
2728 return TargetLoweringObjectFileELF::SelectSectionForGlobal(GV, Kind, TM);
18121812 }
18131813 }
18141814
1815 bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
1816 const Triple &TT = getTargetMachine().getTargetTriple();
1817 return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1818 AMDGPU::shouldEmitConstantsToTextSection(TT);
1819 }
1820
1821 bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
1822 return (GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
1823 GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) &&
1824 !shouldEmitFixup(GV) &&
1825 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1826 }
1827
1828 bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
1829 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
1830 }
1831
18151832 /// This transforms the control flow intrinsics to get the branch destination as
18161833 /// last parameter, also switches branch target with BR if the need arise
18171834 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
19962013 return DAG.getUNDEF(ASC->getValueType(0));
19972014 }
19982015
1999 static bool shouldEmitFixup(const GlobalValue *GV,
2000 const TargetMachine &TM) {
2001 // FIXME: We need to emit global variables in constant address space in a
2002 // separate section, and use relocations.
2003 return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
2004 }
2005
2006 static bool shouldEmitGOTReloc(const GlobalValue *GV,
2007 const TargetMachine &TM) {
2008 return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
2009 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
2010 }
2011
2012 static bool shouldEmitPCReloc(const GlobalValue *GV,
2013 const TargetMachine &TM) {
2014 return !shouldEmitFixup(GV, TM) && !shouldEmitGOTReloc(GV, TM);
2015 }
2016
20172016 bool
20182017 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
20192018 // We can fold offsets for anything that doesn't require a GOT relocation.
2020 return GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
2021 !shouldEmitGOTReloc(GA->getGlobal(), getTargetMachine());
2019 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
2020 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) &&
2021 !shouldEmitGOTReloc(GA->getGlobal());
20222022 }
20232023
20242024 static SDValue buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
20752075 const GlobalValue *GV = GSD->getGlobal();
20762076 EVT PtrVT = Op.getValueType();
20772077
2078 if (shouldEmitFixup(GV, getTargetMachine()))
2078 if (shouldEmitFixup(GV))
20792079 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
2080 else if (shouldEmitPCReloc(GV, getTargetMachine()))
2080 else if (shouldEmitPCReloc(GV))
20812081 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
20822082 SIInstrInfo::MO_REL32);
20832083
7777 bool isCFIntrinsic(const SDNode *Intr) const;
7878
7979 void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
80
81 /// \returns True if fixup needs to be emitted for given global value \p GV,
82 /// false otherwise.
83 bool shouldEmitFixup(const GlobalValue *GV) const;
84
85 /// \returns True if GOT relocation needs to be emitted for given global value
86 /// \p GV, false otherwise.
87 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
88
89 /// \returns True if PC-relative relocation needs to be emitted for given
90 /// global value \p GV, false otherwise.
91 bool shouldEmitPCReloc(const GlobalValue *GV) const;
92
8093 public:
8194 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
8295
161161
162162 bool isReadOnlySegment(const GlobalValue *GV) {
163163 return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS;
164 }
165
166 bool shouldEmitConstantsToTextSection(const Triple &TT) {
167 return TT.getOS() != Triple::AMDHSA;
164168 }
165169
166170 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
5353 bool isGroupSegment(const GlobalValue *GV);
5454 bool isGlobalSegment(const GlobalValue *GV);
5555 bool isReadOnlySegment(const GlobalValue *GV);
56
57 /// \returns True if constants should be emitted to .text section for given
58 /// target triple \p TT, false otherwise.
59 bool shouldEmitConstantsToTextSection(const Triple &TT);
5660
5761 /// \returns Integer value requested using \p F's \p Name attribute.
5862 ///
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s
11 ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s
22
3 @readonly = private unnamed_addr addrspace(2) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
4 @readonly2 = private unnamed_addr addrspace(2) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
3 @private1 = private unnamed_addr addrspace(2) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
4 @private2 = private unnamed_addr addrspace(2) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
5 @available_externally = available_externally addrspace(2) global [256 x i32] zeroinitializer
56
6 ; GCN-LABEL: {{^}}main:
7 ; GCN-LABEL: {{^}}private_test:
78 ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
8 ; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], readonly
9 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
9
10 ; Non-HSA OSes use fixup into .text section.
11 ; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
12 ; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
13
14 ; HSA OSes use relocations.
15 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
16 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4
17
1018 ; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
11 ; GCN-NEXT: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], readonly
12 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
13 ; NOHSA: .text
14 ; HSA: .text
15 ; GCN: readonly:
16 ; GCN: readonly2:
17 define void @main(i32 %index, float addrspace(1)* %out) {
18 %ptr = getelementptr [4 x float], [4 x float] addrspace(2) * @readonly, i32 0, i32 %index
19
20 ; Non-HSA OSes use fixup into .text section.
21 ; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
22 ; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
23
24 ; HSA OSes use relocations.
25 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
26 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4
27
28 define void @private_test(i32 %index, float addrspace(1)* %out) {
29 %ptr = getelementptr [4 x float], [4 x float] addrspace(2) * @private1, i32 0, i32 %index
1930 %val = load float, float addrspace(2)* %ptr
2031 store float %val, float addrspace(1)* %out
21 %ptr2 = getelementptr [4 x float], [4 x float] addrspace(2) * @readonly2, i32 0, i32 %index
32 %ptr2 = getelementptr [4 x float], [4 x float] addrspace(2) * @private2, i32 0, i32 %index
2233 %val2 = load float, float addrspace(2)* %ptr2
2334 store float %val2, float addrspace(1)* %out
2435 ret void
2536 }
2637
38 ; HSA-LABEL: {{^}}available_externally_test:
39 ; HSA: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
40 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4
41 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+4
42 define void @available_externally_test(i32 addrspace(1)* %out) {
43 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(2)* @available_externally, i32 0, i32 1
44 %val = load i32, i32 addrspace(2)* %ptr
45 store i32 %val, i32 addrspace(1)* %out
46 ret void
47 }
48
49 ; NOHSA: .text
50 ; HSA: .section .rodata
51
52 ; GCN: private1:
53 ; GCN: private2:
3737 ; ASM: .size external_global_program, 4
3838
3939 ; ASM: .type internal_readonly,@object
40 ; ASM: .text
40 ; ASM: .section .rodata.cst4,"aM",@progbits,4
4141 ; ASM: internal_readonly:
4242 ; ASM: .long 0
4343 ; ASM: .size internal_readonly, 4
332332
333333 ; FUNC-LABEL: {{^}}test_memcpy_const_string_align4:
334334 ; SI: s_getpc_b64
335 ; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, hello.align4+4
335 ; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, hello.align4+20
336336 ; SI: s_addc_u32
337 ; SI: s_load_dwordx4
338 ; SI: s_load_dwordx4
339 ; SI: s_load_dwordx2
340 ; SI: buffer_store_dwordx4
341 ; SI: buffer_store_dwordx4
337 ; SI-DAG: s_load_dwordx4
338 ; SI-DAG: s_load_dwordx4
339 ; SI-DAG: s_load_dwordx2
340 ; SI-DAG: buffer_store_dwordx4
341 ; SI-DAG: buffer_store_dwordx4
342342 define void @test_memcpy_const_string_align4(i8 addrspace(1)* noalias %out) nounwind {
343343 %str = bitcast [16 x i8] addrspace(2)* @hello.align4 to i8 addrspace(2)*
344344 call void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* %out, i8 addrspace(2)* %str, i64 32, i32 4, i1 false)