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[ARM] Add .w aliases of MOV with shifted operand These appear to have been simply missing. Differential Revision: https://reviews.llvm.org/D34461 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305993 91177308-0d34-0410-b5e6-96231b3b80d8 John Brawn 3 years ago
3 changed file(s) with 30 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
47554755 def t2MOVSsr: t2AsmPseudo<"movs${p} $Rd, $shift",
47564756 (ins rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
47574757
4758 // Aliases for the above with the .w qualifier
4759 def : t2InstAlias<"mov${p}.w $Rd, $shift",
4760 (t2MOVsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4761 def : t2InstAlias<"movs${p}.w $Rd, $shift",
4762 (t2MOVSsi rGPR:$Rd, t2_so_reg:$shift, pred:$p)>;
4763 def : t2InstAlias<"mov${p}.w $Rd, $shift",
4764 (t2MOVsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4765 def : t2InstAlias<"movs${p}.w $Rd, $shift",
4766 (t2MOVSsr rGPR:$Rd, so_reg_reg:$shift, pred:$p)>;
4767
47584768 // ADR w/o the .w suffix
47594769 def : t2InstAlias<"adr${p} $Rd, $addr",
47604770 (t2ADR rGPR:$Rd, t2adrlabel:$addr, pred:$p)>;
81598159 isARMLowRegister(Inst.getOperand(1).getReg()) &&
81608160 isARMLowRegister(Inst.getOperand(2).getReg()) &&
81618161 Inst.getOperand(0).getReg() == Inst.getOperand(1).getReg() &&
8162 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr))
8162 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
8163 !HasWideQualifier)
81638164 isNarrow = true;
81648165 MCInst TmpInst;
81658166 unsigned newOpc;
81938194 bool isNarrow = false;
81948195 if (isARMLowRegister(Inst.getOperand(0).getReg()) &&
81958196 isARMLowRegister(Inst.getOperand(1).getReg()) &&
8196 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi))
8197 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
8198 !HasWideQualifier)
81978199 isNarrow = true;
81988200 MCInst TmpInst;
81998201 unsigned newOpc;
14961496 @ MOV(shifted register)
14971497 @------------------------------------------------------------------------------
14981498 mov r6, r2, lsl #16
1499 mov.w r6, r2, lsl #16
14991500 mov r6, r2, lsr #16
1501 mov.w r6, r2, lsr #16
15001502 movs r6, r2, asr #32
1503 movs.w r6, r2, asr #32
15011504 movs r6, r2, ror #5
1505 movs.w r6, r2, ror #5
15021506 movs r4, r4, lsl r5
1507 movs.w r4, r4, lsl r5
15031508 movs r4, r4, lsr r5
1509 movs.w r4, r4, lsr r5
15041510 movs r4, r4, asr r5
1511 movs.w r4, r4, asr r5
15051512 movs r4, r4, ror r5
1513 movs.w r4, r4, ror r5
15061514 mov r4, r4, lsl r5
15071515 movs r4, r4, ror r8
15081516 movs r4, r5, lsr r6
15141522 mov r4, r4, rrx
15151523
15161524 @ CHECK: lsl.w r6, r2, #16 @ encoding: [0x4f,0xea,0x02,0x46]
1525 @ CHECK: lsl.w r6, r2, #16 @ encoding: [0x4f,0xea,0x02,0x46]
1526 @ CHECK: lsr.w r6, r2, #16 @ encoding: [0x4f,0xea,0x12,0x46]
15171527 @ CHECK: lsr.w r6, r2, #16 @ encoding: [0x4f,0xea,0x12,0x46]
15181528 @ CHECK: asrs r6, r2, #32 @ encoding: [0x16,0x10]
1529 @ CHECK: asrs.w r6, r2, #32 @ encoding: [0x5f,0xea,0x22,0x06]
1530 @ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16]
15191531 @ CHECK: rors.w r6, r2, #5 @ encoding: [0x5f,0xea,0x72,0x16]
15201532 @ CHECK: lsls r4, r5 @ encoding: [0xac,0x40]
1533 @ CHECK: lsls.w r4, r4, r5 @ encoding: [0x14,0xfa,0x05,0xf4]
15211534 @ CHECK: lsrs r4, r5 @ encoding: [0xec,0x40]
1535 @ CHECK: lsrs.w r4, r4, r5 @ encoding: [0x34,0xfa,0x05,0xf4]
15221536 @ CHECK: asrs r4, r5 @ encoding: [0x2c,0x41]
1537 @ CHECK: asrs.w r4, r4, r5 @ encoding: [0x54,0xfa,0x05,0xf4]
15231538 @ CHECK: rors r4, r5 @ encoding: [0xec,0x41]
1539 @ CHECK: rors.w r4, r4, r5 @ encoding: [0x74,0xfa,0x05,0xf4]
15241540 @ CHECK: lsl.w r4, r4, r5 @ encoding: [0x04,0xfa,0x05,0xf4]
15251541 @ CHECK: rors.w r4, r4, r8 @ encoding: [0x74,0xfa,0x08,0xf4]
15261542 @ CHECK: lsrs.w r4, r5, r6 @ encoding: [0x35,0xfa,0x06,0xf4]