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[WebAssembly] Add except_ref as a first-class type Summary: Add except_ref as a first-class type, according to the [[https://github.com/WebAssembly/exception-handling/blob/master/proposals/Level-1.md | Level 1 exception handling proposal ]]. Reviewers: dschuff Subscribers: jfb, sbc100, llvm-commits Differential Revision: https://reviews.llvm.org/D43706 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@326985 91177308-0d34-0410-b5e6-96231b3b80d8 Heejin Ahn 2 years ago
15 changed file(s) with 97 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
184184 WASM_TYPE_F32 = 0x7D,
185185 WASM_TYPE_F64 = 0x7C,
186186 WASM_TYPE_ANYFUNC = 0x70,
187 WASM_TYPE_EXCEPT_REF = 0x68,
187188 WASM_TYPE_FUNC = 0x60,
188189 WASM_TYPE_NORESULT = 0x40, // for blocks with no result values
189190 };
216217 I64 = WASM_TYPE_I64,
217218 F32 = WASM_TYPE_F32,
218219 F64 = WASM_TYPE_F64,
220 EXCEPT_REF = WASM_TYPE_EXCEPT_REF,
219221 };
220222
221223 // Kind codes used in the custom "name" section
190190 // unspecified type. The register class
191191 // will be determined by the opcode.
192192
193 ExceptRef = 113, // WebAssembly's except_ref type
194
193195 FIRST_VALUETYPE = 1, // This is always the beginning of the list.
194 LAST_VALUETYPE = 113, // This always remains at the end of the list.
196 LAST_VALUETYPE = 114, // This always remains at the end of the list.
195197
196198 // This is the current maximum for LAST_VALUETYPE.
197199 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
745747 case v64i32:
746748 case v32i64:
747749 case nxv32i64: return 2048;
750 case ExceptRef: return 0; // opaque type
748751 }
749752 }
750753
144144 def FlagVT : ValueType<0 , 110>; // Pre-RA sched glue
145145 def isVoid : ValueType<0 , 111>; // Produces no value
146146 def untyped: ValueType<8 , 112>; // Produces an untyped value
147 def ExceptRef: ValueType<0, 113>; // WebAssembly's except_ref type
147148 def token : ValueType<0 , 248>; // TokenTy
148149 def MetadataVT: ValueType<0, 249>; // Metadata
149150
219219 case WebAssembly::ExprType::B8x16: O << "b8x16"; break;
220220 case WebAssembly::ExprType::B16x8: O << "b16x8"; break;
221221 case WebAssembly::ExprType::B32x4: O << "b32x4"; break;
222 case WebAssembly::ExprType::ExceptRef: O << "except_ref"; break;
222223 }
223224 }
224225
237238 case MVT::v4i32:
238239 case MVT::v4f32:
239240 return "v128";
241 case MVT::ExceptRef:
242 return "except_ref";
240243 default:
241244 llvm_unreachable("unsupported type");
242245 }
252255 return "f32";
253256 case wasm::ValType::F64:
254257 return "f64";
258 case wasm::ValType::EXCEPT_REF:
259 return "except_ref";
255260 }
256261 llvm_unreachable("unsupported type");
257262 }
134134 case MVT::i64: return wasm::ValType::I64;
135135 case MVT::f32: return wasm::ValType::F32;
136136 case MVT::f64: return wasm::ValType::F64;
137 case MVT::ExceptRef: return wasm::ValType::EXCEPT_REF;
137138 default: llvm_unreachable("unexpected type");
138139 }
139140 }
158158
159159 /// This is used to indicate block signatures.
160160 enum class ExprType : unsigned {
161 Void = 0x40,
162 I32 = 0x7F,
163 I64 = 0x7E,
164 F32 = 0x7D,
165 F64 = 0x7C,
166 I8x16 = 0x7B,
167 I16x8 = 0x7A,
168 I32x4 = 0x79,
169 F32x4 = 0x78,
170 B8x16 = 0x77,
171 B16x8 = 0x76,
172 B32x4 = 0x75
161 Void = 0x40,
162 I32 = 0x7F,
163 I64 = 0x7E,
164 F32 = 0x7D,
165 F64 = 0x7C,
166 I8x16 = 0x7B,
167 I16x8 = 0x7A,
168 I32x4 = 0x79,
169 F32x4 = 0x78,
170 B8x16 = 0x77,
171 B16x8 = 0x76,
172 B32x4 = 0x75,
173 ExceptRef = 0x68
173174 };
174175
175176 /// Instruction opcodes emitted via means other than CodeGen.
248248 case MVT::v8i16: retType = WebAssembly::ExprType::I16x8; break;
249249 case MVT::v4i32: retType = WebAssembly::ExprType::I32x4; break;
250250 case MVT::v4f32: retType = WebAssembly::ExprType::F32x4; break;
251 case MVT::ExceptRef: retType = WebAssembly::ExprType::ExceptRef; break;
251252 default: llvm_unreachable("unexpected return type");
252253 }
253254
8585 return WebAssembly::DROP_F64;
8686 if (RC == &WebAssembly::V128RegClass)
8787 return WebAssembly::DROP_V128;
88 if (RC == &WebAssembly::EXCEPT_REFRegClass)
89 return WebAssembly::DROP_EXCEPT_REF;
8890 llvm_unreachable("Unexpected register class");
8991 }
9092
100102 return WebAssembly::GET_LOCAL_F64;
101103 if (RC == &WebAssembly::V128RegClass)
102104 return WebAssembly::GET_LOCAL_V128;
105 if (RC == &WebAssembly::EXCEPT_REFRegClass)
106 return WebAssembly::GET_LOCAL_EXCEPT_REF;
103107 llvm_unreachable("Unexpected register class");
104108 }
105109
115119 return WebAssembly::SET_LOCAL_F64;
116120 if (RC == &WebAssembly::V128RegClass)
117121 return WebAssembly::SET_LOCAL_V128;
122 if (RC == &WebAssembly::EXCEPT_REFRegClass)
123 return WebAssembly::SET_LOCAL_EXCEPT_REF;
118124 llvm_unreachable("Unexpected register class");
119125 }
120126
130136 return WebAssembly::TEE_LOCAL_F64;
131137 if (RC == &WebAssembly::V128RegClass)
132138 return WebAssembly::TEE_LOCAL_V128;
139 if (RC == &WebAssembly::EXCEPT_REFRegClass)
140 return WebAssembly::TEE_LOCAL_EXCEPT_REF;
133141 llvm_unreachable("Unexpected register class");
134142 }
135143
143151 return MVT::f32;
144152 if (RC == &WebAssembly::F64RegClass)
145153 return MVT::f64;
154 if (RC == &WebAssembly::EXCEPT_REFRegClass)
155 return MVT::ExceptRef;
146156 llvm_unreachable("unrecognized register class");
147157 }
148158
126126 case MVT::i64:
127127 case MVT::f32:
128128 case MVT::f64:
129 case MVT::ExceptRef:
129130 return VT;
130131 case MVT::f16:
131132 return MVT::f32;
680681 Opc = WebAssembly::ARGUMENT_v4f32;
681682 RC = &WebAssembly::V128RegClass;
682683 break;
684 case MVT::ExceptRef:
685 Opc = WebAssembly::ARGUMENT_EXCEPT_REF;
686 RC = &WebAssembly::EXCEPT_REFRegClass;
687 break;
683688 default:
684689 return false;
685690 }
769774 IsDirect ? WebAssembly::CALL_v4f32 : WebAssembly::PCALL_INDIRECT_v4f32;
770775 ResultReg = createResultReg(&WebAssembly::V128RegClass);
771776 break;
777 case MVT::ExceptRef:
778 Opc = IsDirect ? WebAssembly::CALL_EXCEPT_REF
779 : WebAssembly::PCALL_INDIRECT_EXCEPT_REF;
780 ResultReg = createResultReg(&WebAssembly::EXCEPT_REFRegClass);
781 break;
772782 default:
773783 return false;
774784 }
867877 Opc = WebAssembly::SELECT_F64;
868878 RC = &WebAssembly::F64RegClass;
869879 break;
880 case MVT::ExceptRef:
881 Opc = WebAssembly::SELECT_EXCEPT_REF;
882 RC = &WebAssembly::EXCEPT_REFRegClass;
883 break;
870884 default:
871885 return false;
872886 }
12721286 break;
12731287 case MVT::v4f32:
12741288 Opc = WebAssembly::RETURN_v4f32;
1289 break;
1290 case MVT::ExceptRef:
1291 Opc = WebAssembly::RETURN_EXCEPT_REF;
12751292 break;
12761293 default: return false;
12771294 }
7171 defm : CALL;
7272 defm : CALL;
7373 defm : CALL;
74 defm : CALL;
7475 defm : SIMD_CALL;
7576 defm : SIMD_CALL;
7677 defm : SIMD_CALL;
111112 (CALL_v4i32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
112113 def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
113114 (CALL_v4f32 tglobaladdr:$callee)>, Requires<[HasSIMD128]>;
115 def : Pat<(ExceptRef
116 (WebAssemblycall1 (WebAssemblywrapper tglobaladdr:$callee))),
117 (CALL_EXCEPT_REF tglobaladdr:$callee)>;
114118 def : Pat<(WebAssemblycall0 (WebAssemblywrapper tglobaladdr:$callee)),
115119 (CALL_VOID tglobaladdr:$callee)>;
116120
131135 (CALL_v4i32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
132136 def : Pat<(v4f32 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
133137 (CALL_v4f32 texternalsym:$callee)>, Requires<[HasSIMD128]>;
138 def : Pat<(ExceptRef
139 (WebAssemblycall1 (WebAssemblywrapper texternalsym:$callee))),
140 (CALL_EXCEPT_REF texternalsym:$callee)>;
134141 def : Pat<(WebAssemblycall0 (WebAssemblywrapper texternalsym:$callee)),
135142 (CALL_VOID texternalsym:$callee)>;
9797 defm : RETURN;
9898 defm : RETURN;
9999 defm : RETURN;
100 defm : RETURN;
100101 defm : SIMD_RETURN;
101102 defm : SIMD_RETURN;
102103 defm : SIMD_RETURN;
0 // WebAssemblyInstrExceptRef.td-WebAssembly except_ref codegen --*- tablegen -*-
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 ///
9 /// \file
10 /// \brief WebAssembly except_ref operand code-gen constructs.
11 ///
12 //===----------------------------------------------------------------------===//
13
14 let Defs = [ARGUMENTS] in {
15
16 def SELECT_EXCEPT_REF : I<(outs EXCEPT_REF:$dst),
17 (ins EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond),
18 [(set EXCEPT_REF:$dst,
19 (select I32:$cond, EXCEPT_REF:$lhs,
20 EXCEPT_REF:$rhs))],
21 "except_ref.select\t$dst, $lhs, $rhs, $cond", 0x1b>;
22
23 } // Defs = [ARGUMENTS]
24
25 def : Pat<(select (i32 (setne I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
26 (SELECT_EXCEPT_REF EXCEPT_REF:$lhs, EXCEPT_REF:$rhs, I32:$cond)>;
27 def : Pat<(select (i32 (seteq I32:$cond, 0)), EXCEPT_REF:$lhs, EXCEPT_REF:$rhs),
28 (SELECT_EXCEPT_REF EXCEPT_REF:$rhs, EXCEPT_REF:$lhs, I32:$cond)>;
165165 defm : ARGUMENT;
166166 defm : ARGUMENT;
167167 defm : ARGUMENT;
168 defm : ARGUMENT;
168169 defm : SIMD_ARGUMENT;
169170 defm : SIMD_ARGUMENT;
170171 defm : SIMD_ARGUMENT;
231232 defm : LOCAL;
232233 defm : LOCAL;
233234 defm : LOCAL, Requires<[HasSIMD128]>;
235 defm : LOCAL, Requires<[HasExceptionHandling]>;
234236
235237 let isMoveImm = 1, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
236238 def CONST_I32 : I<(outs I32:$res), (ins i32imm_op:$imm),
266268 include "WebAssemblyInstrFloat.td"
267269 include "WebAssemblyInstrAtomics.td"
268270 include "WebAssemblyInstrSIMD.td"
271 include "WebAssemblyInstrExceptRef.td"
3737 // since we otherwise don't need a physical register in those classes.
3838 def F32_0 : WebAssemblyReg<"%f32.0">;
3939 def F64_0 : WebAssemblyReg<"%f64.0">;
40
4140 def V128_0: WebAssemblyReg<"%v128">;
41 def EXCEPT_REF_0 : WebAssemblyReg<"%except_ref.0">;
4242
4343 // The value stack "register". This is an opaque entity which serves to order
4444 // uses and defs that must remain in LIFO order.
5858 def F32 : WebAssemblyRegClass<[f32], 32, (add F32_0)>;
5959 def F64 : WebAssemblyRegClass<[f64], 64, (add F64_0)>;
6060 def V128 : WebAssemblyRegClass<[v4f32, v4i32, v16i8, v8i16], 128, (add V128_0)>;
61
61 def EXCEPT_REF : WebAssemblyRegClass<[ExceptRef], 0, (add EXCEPT_REF_0)>;
173173 case MVT::iPTR: return "MVT::iPTR";
174174 case MVT::iPTRAny: return "MVT::iPTRAny";
175175 case MVT::Untyped: return "MVT::Untyped";
176 case MVT::ExceptRef: return "MVT::ExceptRef";
176177 default: llvm_unreachable("ILLEGAL VALUE TYPE!");
177178 }
178179 }