llvm.org GIT mirror llvm / df1c637
Remove getARMRegisterNumbering and replace with calls into the register info for getEncodingValue. This builds on the small patch of yesterday to set HWEncoding in the register file. One (deprecated) use was turned into a hard number to avoid needing register info in the old JIT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161628 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 8 years ago
7 changed file(s) with 90 addition(s) and 154 deletion(s). Raw diff Collapse all Expand all
253253 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
254254 return 0;
255255 }
256 unsigned Reg = getARMRegisterNumbering(MO.getReg());
256 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
257257 int32_t Imm12 = MO1.getImm();
258258 uint32_t Binary;
259259 Binary = Imm12 & 0xfff;
295295 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
296296 return 0;
297297 }
298 unsigned Reg = getARMRegisterNumbering(MO.getReg());
298 unsigned Reg = II->getRegisterInfo().getEncodingValue(MO.getReg());
299299 int32_t Imm12 = MO1.getImm();
300300
301301 // Special value for #-0
351351 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
352352 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
353353 intptr_t JTBase = 0) const;
354 unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) const;
355 unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) const;
356 unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) const;
357 unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) const;
358 unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) const;
359 unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) const;
354360 };
355361 }
356362
439445 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
440446 const MachineOperand &MO) const {
441447 if (MO.isReg())
442 return getARMRegisterNumbering(MO.getReg());
448 return II->getRegisterInfo().getEncodingValue(MO.getReg());
443449 else if (MO.isImm())
444450 return static_cast(MO.getImm());
445451 else if (MO.isGlobal())
775781 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
776782
777783 // Encode Rn which is PC.
778 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
784 Binary |= II->getRegisterInfo().getEncodingValue(ARM::PC) << ARMII::RegRnShift;
779785
780786 // Encode the displacement.
781787 Binary |= 1 << ARMII::I_BitShift;
962968 if (Rs) {
963969 // Encode Rs bit[11:8].
964970 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
965 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
971 return Binary | (II->getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
966972 }
967973
968974 // Encode shift_imm bit[11:7].
10131019 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
10141020 else if (ImplicitRd)
10151021 // Special handling for implicit use (e.g. PC).
1016 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1022 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
10171023
10181024 if (MCID.Opcode == ARM::MOVi16) {
10191025 // Get immediate from MI.
10631069 if (!isUnary) {
10641070 if (ImplicitRn)
10651071 // Special handling for implicit use (e.g. PC).
1066 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1072 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
10671073 else {
10681074 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
10691075 ++OpIdx;
10801086
10811087 if (MO.isReg()) {
10821088 // Encode register Rm.
1083 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
1089 emitWordLE(Binary | II->getRegisterInfo().getEncodingValue(MO.getReg()));
10841090 return;
10851091 }
10861092
11231129 // Set first operand
11241130 if (ImplicitRd)
11251131 // Special handling for implicit use (e.g. PC).
1126 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
1132 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRd) << ARMII::RegRdShift);
11271133 else
11281134 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
11291135
11301136 // Set second operand
11311137 if (ImplicitRn)
11321138 // Special handling for implicit use (e.g. PC).
1133 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1139 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
11341140 else
11351141 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
11361142
11571163 Binary |= 1 << ARMII::I_BitShift;
11581164 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
11591165 // Set bit[3:0] to the corresponding Rm register
1160 Binary |= getARMRegisterNumbering(MO2.getReg());
1166 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
11611167
11621168 // If this instr is in scaled register offset/index instruction, set
11631169 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
12011207 // Set second operand
12021208 if (ImplicitRn)
12031209 // Special handling for implicit use (e.g. PC).
1204 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
1210 Binary |= (II->getRegisterInfo().getEncodingValue(ImplicitRn) << ARMII::RegRnShift);
12051211 else
12061212 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
12071213
12201226 // If this instr is in register offset/index encoding, set bit[3:0]
12211227 // to the corresponding Rm register.
12221228 if (MO2.getReg()) {
1223 Binary |= getARMRegisterNumbering(MO2.getReg());
1229 Binary |= II->getRegisterInfo().getEncodingValue(MO2.getReg());
12241230 emitWordLE(Binary);
12251231 return;
12261232 }
12861292 const MachineOperand &MO = MI.getOperand(i);
12871293 if (!MO.isReg() || MO.isImplicit())
12881294 break;
1289 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
1295 unsigned RegNum = II->getRegisterInfo().getEncodingValue(MO.getReg());
12901296 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
12911297 RegNum < 16);
12921298 Binary |= 0x1 << RegNum;
15291535
15301536 if (MCID.Opcode == ARM::BX_RET || MCID.Opcode == ARM::MOVPCLR)
15311537 // The return register is LR.
1532 Binary |= getARMRegisterNumbering(ARM::LR);
1538 Binary |= II->getRegisterInfo().getEncodingValue(ARM::LR);
15331539 else
15341540 // otherwise, set the return register
15351541 Binary |= getMachineOpValue(MI, 0);
15371543 emitWordLE(Binary);
15381544 }
15391545
1540 static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
1546 unsigned ARMCodeEmitter::encodeVFPRd(const MachineInstr &MI,
1547 unsigned OpIdx) const {
15411548 unsigned RegD = MI.getOperand(OpIdx).getReg();
15421549 unsigned Binary = 0;
15431550 bool isSPVFP = ARM::SPRRegClass.contains(RegD);
1544 RegD = getARMRegisterNumbering(RegD);
1551 RegD = II->getRegisterInfo().getEncodingValue(RegD);
15451552 if (!isSPVFP)
15461553 Binary |= RegD << ARMII::RegRdShift;
15471554 else {
15511558 return Binary;
15521559 }
15531560
1554 static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
1561 unsigned ARMCodeEmitter::encodeVFPRn(const MachineInstr &MI,
1562 unsigned OpIdx) const {
15551563 unsigned RegN = MI.getOperand(OpIdx).getReg();
15561564 unsigned Binary = 0;
15571565 bool isSPVFP = ARM::SPRRegClass.contains(RegN);
1558 RegN = getARMRegisterNumbering(RegN);
1566 RegN = II->getRegisterInfo().getEncodingValue(RegN);
15591567 if (!isSPVFP)
15601568 Binary |= RegN << ARMII::RegRnShift;
15611569 else {
15651573 return Binary;
15661574 }
15671575
1568 static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1576 unsigned ARMCodeEmitter::encodeVFPRm(const MachineInstr &MI,
1577 unsigned OpIdx) const {
15691578 unsigned RegM = MI.getOperand(OpIdx).getReg();
15701579 unsigned Binary = 0;
15711580 bool isSPVFP = ARM::SPRRegClass.contains(RegM);
1572 RegM = getARMRegisterNumbering(RegM);
1581 RegM = II->getRegisterInfo().getEncodingValue(RegM);
15731582 if (!isSPVFP)
15741583 Binary |= RegM;
15751584 else {
17561765 emitWordLE(Binary);
17571766 }
17581767
1759 static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1768 unsigned ARMCodeEmitter::encodeNEONRd(const MachineInstr &MI,
1769 unsigned OpIdx) const {
17601770 unsigned RegD = MI.getOperand(OpIdx).getReg();
17611771 unsigned Binary = 0;
1762 RegD = getARMRegisterNumbering(RegD);
1772 RegD = II->getRegisterInfo().getEncodingValue(RegD);
17631773 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
17641774 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
17651775 return Binary;
17661776 }
17671777
1768 static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1778 unsigned ARMCodeEmitter::encodeNEONRn(const MachineInstr &MI,
1779 unsigned OpIdx) const {
17691780 unsigned RegN = MI.getOperand(OpIdx).getReg();
17701781 unsigned Binary = 0;
1771 RegN = getARMRegisterNumbering(RegN);
1782 RegN = II->getRegisterInfo().getEncodingValue(RegN);
17721783 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
17731784 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
17741785 return Binary;
17751786 }
17761787
1777 static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1788 unsigned ARMCodeEmitter::encodeNEONRm(const MachineInstr &MI,
1789 unsigned OpIdx) const {
17781790 unsigned RegM = MI.getOperand(OpIdx).getReg();
17791791 unsigned Binary = 0;
1780 RegM = getARMRegisterNumbering(RegM);
1792 RegM = II->getRegisterInfo().getEncodingValue(RegM);
17811793 Binary |= (RegM & 0xf);
17821794 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
17831795 return Binary;
18111823 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
18121824
18131825 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
1814 RegT = getARMRegisterNumbering(RegT);
1826 RegT = II->getRegisterInfo().getEncodingValue(RegT);
18151827 Binary |= (RegT << ARMII::RegRdShift);
18161828 Binary |= encodeNEONRn(MI, RegNOpIdx);
18171829
18401852 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
18411853
18421854 unsigned RegT = MI.getOperand(1).getReg();
1843 RegT = getARMRegisterNumbering(RegT);
1855 RegT = II->getRegisterInfo().getEncodingValue(RegT);
18441856 Binary |= (RegT << ARMII::RegRdShift);
18451857 Binary |= encodeNEONRn(MI, 0);
18461858 emitWordLE(Binary);
10081008 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
10091009 unsigned OpIdx = 0;
10101010 unsigned SrcReg = MI.getOperand(1).getReg();
1011 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1;
1011 unsigned Lane = TRI->getEncodingValue(SrcReg) & 1;
10121012 unsigned DReg = TRI->getMatchingSuperReg(SrcReg,
10131013 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0,
10141014 &ARM::DPR_VFP2RegClass);
288288 if (MR->getRelocationType() == ARM::reloc_arm_vfp_cp_entry)
289289 ResultPtr = ResultPtr >> 2;
290290 *((intptr_t*)RelocPos) |= ResultPtr;
291 // Set register Rn to PC.
292 *((intptr_t*)RelocPos) |=
293 getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
291 // Set register Rn to PC (which is register 15 on all architectures).
292 // FIXME: This avoids the need for register info in the JIT class.
293 *((intptr_t*)RelocPos) |= 15 << ARMII::RegRnShift;
294294 break;
295295 }
296296 case ARM::reloc_arm_pic_jt:
455455 DebugLoc dl = Loc->getDebugLoc();
456456 const MachineOperand &PMO = Loc->getOperand(0);
457457 unsigned PReg = PMO.getReg();
458 unsigned PRegNum = PMO.isUndef() ? UINT_MAX
459 : getARMRegisterNumbering(PReg);
458 unsigned PRegNum = PMO.isUndef() ? UINT_MAX : TRI->getEncodingValue(PReg);
460459 unsigned Count = 1;
461460 unsigned Limit = ~0U;
462461
482481 int NewOffset = MemOps[i].Offset;
483482 const MachineOperand &MO = MemOps[i].MBBI->getOperand(0);
484483 unsigned Reg = MO.getReg();
485 unsigned RegNum = MO.isUndef() ? UINT_MAX
486 : getARMRegisterNumbering(Reg);
484 unsigned RegNum = MO.isUndef() ? UINT_MAX : TRI->getEncodingValue(Reg);
487485 // Register numbers must be in ascending order. For VFP / NEON load and
488486 // store multiples, the registers must also be consecutive and within the
489487 // limit on the number of registers per instruction.
29072907 if (!RC->contains(EndReg))
29082908 return Error(EndLoc, "invalid register in register list");
29092909 // Ranges must go from low to high.
2910 if (getARMRegisterNumbering(Reg) > getARMRegisterNumbering(EndReg))
2910 if (MRI->getEncodingValue(Reg) > MRI->getEncodingValue(EndReg))
29112911 return Error(EndLoc, "bad range in register list");
29122912
29132913 // Add all the registers in the range to the register list.
29342934 if (!RC->contains(Reg))
29352935 return Error(RegLoc, "invalid register in register list");
29362936 // List must be monotonically increasing.
2937 if (getARMRegisterNumbering(Reg) < getARMRegisterNumbering(OldReg)) {
2937 if (MRI->getEncodingValue(Reg) < MRI->getEncodingValue(OldReg)) {
29382938 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg))
29392939 Warning(RegLoc, "register list not in ascending order");
29402940 else
29412941 return Error(RegLoc, "register list not in ascending order");
29422942 }
2943 if (getARMRegisterNumbering(Reg) == getARMRegisterNumbering(OldReg)) {
2943 if (MRI->getEncodingValue(Reg) == MRI->getEncodingValue(OldReg)) {
29442944 Warning(RegLoc, "duplicated register (" + RegTok.getString() +
29452945 ") in register list");
29462946 continue;
53035303 case ARM::LDRD_POST:
53045304 case ARM::LDREXD: {
53055305 // Rt2 must be Rt + 1.
5306 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5307 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5306 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5307 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
53085308 if (Rt2 != Rt + 1)
53095309 return Error(Operands[3]->getStartLoc(),
53105310 "destination operands must be sequential");
53125312 }
53135313 case ARM::STRD: {
53145314 // Rt2 must be Rt + 1.
5315 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(0).getReg());
5316 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5315 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg());
5316 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg());
53175317 if (Rt2 != Rt + 1)
53185318 return Error(Operands[3]->getStartLoc(),
53195319 "source operands must be sequential");
53235323 case ARM::STRD_POST:
53245324 case ARM::STREXD: {
53255325 // Rt2 must be Rt + 1.
5326 unsigned Rt = getARMRegisterNumbering(Inst.getOperand(1).getReg());
5327 unsigned Rt2 = getARMRegisterNumbering(Inst.getOperand(2).getReg());
5326 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(1).getReg());
5327 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(2).getReg());
53285328 if (Rt2 != Rt + 1)
53295329 return Error(Operands[3]->getStartLoc(),
53305330 "source operands must be sequential");
160160 }
161161 } // namespace ARM_MB
162162
163 /// getARMRegisterNumbering - Given the enum value for some register, e.g.
164 /// ARM::LR, return the number that it corresponds to (e.g. 14).
165 inline static unsigned getARMRegisterNumbering(unsigned Reg) {
166 using namespace ARM;
167 switch (Reg) {
168 default:
169 llvm_unreachable("Unknown ARM register!");
170 case R0: case S0: case D0: case Q0: return 0;
171 case R1: case S1: case D1: case Q1: return 1;
172 case R2: case S2: case D2: case Q2: return 2;
173 case R3: case S3: case D3: case Q3: return 3;
174 case R4: case S4: case D4: case Q4: return 4;
175 case R5: case S5: case D5: case Q5: return 5;
176 case R6: case S6: case D6: case Q6: return 6;
177 case R7: case S7: case D7: case Q7: return 7;
178 case R8: case S8: case D8: case Q8: return 8;
179 case R9: case S9: case D9: case Q9: return 9;
180 case R10: case S10: case D10: case Q10: return 10;
181 case R11: case S11: case D11: case Q11: return 11;
182 case R12: case S12: case D12: case Q12: return 12;
183 case SP: case S13: case D13: case Q13: return 13;
184 case LR: case S14: case D14: case Q14: return 14;
185 case PC: case S15: case D15: case Q15: return 15;
186
187 case S16: case D16: return 16;
188 case S17: case D17: return 17;
189 case S18: case D18: return 18;
190 case S19: case D19: return 19;
191 case S20: case D20: return 20;
192 case S21: case D21: return 21;
193 case S22: case D22: return 22;
194 case S23: case D23: return 23;
195 case S24: case D24: return 24;
196 case S25: case D25: return 25;
197 case S26: case D26: return 26;
198 case S27: case D27: return 27;
199 case S28: case D28: return 28;
200 case S29: case D29: return 29;
201 case S30: case D30: return 30;
202 case S31: case D31: return 31;
203
204 // Composite registers use the regnum of the first register in the list.
205 /* Q0 */ case D0_D2: return 0;
206 case D1_D2: case D1_D3: return 1;
207 /* Q1 */ case D2_D4: return 2;
208 case D3_D4: case D3_D5: return 3;
209 /* Q2 */ case D4_D6: return 4;
210 case D5_D6: case D5_D7: return 5;
211 /* Q3 */ case D6_D8: return 6;
212 case D7_D8: case D7_D9: return 7;
213 /* Q4 */ case D8_D10: return 8;
214 case D9_D10: case D9_D11: return 9;
215 /* Q5 */ case D10_D12: return 10;
216 case D11_D12: case D11_D13: return 11;
217 /* Q6 */ case D12_D14: return 12;
218 case D13_D14: case D13_D15: return 13;
219 /* Q7 */ case D14_D16: return 14;
220 case D15_D16: case D15_D17: return 15;
221 /* Q8 */ case D16_D18: return 16;
222 case D17_D18: case D17_D19: return 17;
223 /* Q9 */ case D18_D20: return 18;
224 case D19_D20: case D19_D21: return 19;
225 /* Q10 */ case D20_D22: return 20;
226 case D21_D22: case D21_D23: return 21;
227 /* Q11 */ case D22_D24: return 22;
228 case D23_D24: case D23_D25: return 23;
229 /* Q12 */ case D24_D26: return 24;
230 case D25_D26: case D25_D27: return 25;
231 /* Q13 */ case D26_D28: return 26;
232 case D27_D28: case D27_D29: return 27;
233 /* Q14 */ case D28_D30: return 28;
234 case D29_D30: case D29_D31: return 29;
235 /* Q15 */
236 }
237 }
238
239163 /// isARMLowRegister - Returns true if the register is a low register (r0-r7).
240164 ///
241165 static inline bool isARMLowRegister(unsigned Reg) {
1717 #include "MCTargetDesc/ARMMCExpr.h"
1818 #include "MCTargetDesc/ARMMCTargetDesc.h"
1919 #include "llvm/MC/MCCodeEmitter.h"
20 #include "llvm/MC/MCContext.h"
2021 #include "llvm/MC/MCExpr.h"
2122 #include "llvm/MC/MCInst.h"
2223 #include "llvm/MC/MCInstrInfo.h"
3738 void operator=(const ARMMCCodeEmitter &); // DO NOT IMPLEMENT
3839 const MCInstrInfo &MCII;
3940 const MCSubtargetInfo &STI;
41 const MCContext &CTX;
4042
4143 public:
4244 ARMMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
4345 MCContext &ctx)
44 : MCII(mcii), STI(sti) {
46 : MCII(mcii), STI(sti), CTX(ctx) {
4547 }
4648
4749 ~ARMMCCodeEmitter() {}
404406 SmallVectorImpl &Fixups) const {
405407 if (MO.isReg()) {
406408 unsigned Reg = MO.getReg();
407 unsigned RegNo = getARMRegisterNumbering(Reg);
409 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
408410
409411 // Q registers are encoded as 2x their register number.
410412 switch (Reg) {
433435 const MCOperand &MO = MI.getOperand(OpIdx);
434436 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
435437
436 Reg = getARMRegisterNumbering(MO.getReg());
438 Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
437439
438440 int32_t SImm = MO1.getImm();
439441 bool isAdd = true;
708710 // {2-0} = Rn
709711 const MCOperand &MO1 = MI.getOperand(OpIdx);
710712 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
711 unsigned Rn = getARMRegisterNumbering(MO1.getReg());
712 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
713 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
714 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
713715 return (Rm << 3) | Rn;
714716 }
715717
725727 // If The first operand isn't a register, we have a label reference.
726728 const MCOperand &MO = MI.getOperand(OpIdx);
727729 if (!MO.isReg()) {
728 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
730 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
729731 Imm12 = 0;
730732 isAdd = false ; // 'U' bit is set as part of the fixup.
731733
805807 // If The first operand isn't a register, we have a label reference.
806808 const MCOperand &MO = MI.getOperand(OpIdx);
807809 if (!MO.isReg()) {
808 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
810 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
809811 Imm8 = 0;
810812 isAdd = false ; // 'U' bit is set as part of the fixup.
811813
841843 // {7-0} = imm8
842844 const MCOperand &MO = MI.getOperand(OpIdx);
843845 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
844 unsigned Reg = getARMRegisterNumbering(MO.getReg());
846 unsigned Reg = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
845847 unsigned Imm8 = MO1.getImm();
846848 return (Reg << 8) | Imm8;
847849 }
924926 const MCOperand &MO = MI.getOperand(OpIdx);
925927 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
926928 const MCOperand &MO2 = MI.getOperand(OpIdx+2);
927 unsigned Rn = getARMRegisterNumbering(MO.getReg());
928 unsigned Rm = getARMRegisterNumbering(MO1.getReg());
929 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
930 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
929931 unsigned ShImm = ARM_AM::getAM2Offset(MO2.getImm());
930932 bool isAdd = ARM_AM::getAM2Op(MO2.getImm()) == ARM_AM::add;
931933 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(MO2.getImm());
955957 // {12} isAdd
956958 // {11-0} imm12/Rm
957959 const MCOperand &MO = MI.getOperand(OpIdx);
958 unsigned Rn = getARMRegisterNumbering(MO.getReg());
960 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
959961 uint32_t Binary = getAddrMode2OffsetOpValue(MI, OpIdx + 1, Fixups);
960962 Binary |= Rn << 14;
961963 return Binary;
978980 ARM_AM::ShiftOpc ShOp = ARM_AM::getAM2ShiftOpc(Imm);
979981 Binary <<= 7; // Shift amount is bits [11:7]
980982 Binary |= getShiftOp(ShOp) << 5; // Shift type is bits [6:5]
981 Binary |= getARMRegisterNumbering(MO.getReg()); // Rm is bits [3:0]
983 Binary |= CTX.getRegisterInfo().getEncodingValue(MO.getReg()); // Rm is bits [3:0]
982984 }
983985 return Binary | (isAdd << 12) | (isReg << 13);
984986 }
991993 const MCOperand &MO = MI.getOperand(OpIdx);
992994 const MCOperand &MO1 = MI.getOperand(OpIdx+1);
993995 bool isAdd = MO1.getImm() != 0;
994 return getARMRegisterNumbering(MO.getReg()) | (isAdd << 4);
996 return CTX.getRegisterInfo().getEncodingValue(MO.getReg()) | (isAdd << 4);
995997 }
996998
997999 uint32_t ARMMCCodeEmitter::
10091011 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
10101012 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
10111013 if (!isImm)
1012 Imm8 = getARMRegisterNumbering(MO.getReg());
1014 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
10131015 return Imm8 | (isAdd << 8) | (isImm << 9);
10141016 }
10151017
10271029
10281030 // If The first operand isn't a register, we have a label reference.
10291031 if (!MO.isReg()) {
1030 unsigned Rn = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1032 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
10311033
10321034 assert(MO.isExpr() && "Unexpected machine operand type!");
10331035 const MCExpr *Expr = MO.getExpr();
10371039 ++MCNumCPRelocations;
10381040 return (Rn << 9) | (1 << 13);
10391041 }
1040 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1042 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
10411043 unsigned Imm = MO2.getImm();
10421044 bool isAdd = ARM_AM::getAM3Op(Imm) == ARM_AM::add;
10431045 bool isImm = MO1.getReg() == 0;
10441046 uint32_t Imm8 = ARM_AM::getAM3Offset(Imm);
10451047 // if reg +/- reg, Rm will be non-zero. Otherwise, we have reg +/- imm8
10461048 if (!isImm)
1047 Imm8 = getARMRegisterNumbering(MO1.getReg());
1049 Imm8 = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
10481050 return (Rn << 9) | Imm8 | (isAdd << 8) | (isImm << 13);
10491051 }
10501052
10721074 // {2-0} = Rn
10731075 const MCOperand &MO = MI.getOperand(OpIdx);
10741076 const MCOperand &MO1 = MI.getOperand(OpIdx + 1);
1075 unsigned Rn = getARMRegisterNumbering(MO.getReg());
1077 unsigned Rn = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
10761078 unsigned Imm5 = MO1.getImm();
10771079 return ((Imm5 & 0x1f) << 3) | Rn;
10781080 }
10991101 // If The first operand isn't a register, we have a label reference.
11001102 const MCOperand &MO = MI.getOperand(OpIdx);
11011103 if (!MO.isReg()) {
1102 Reg = getARMRegisterNumbering(ARM::PC); // Rn is PC.
1104 Reg = CTX.getRegisterInfo().getEncodingValue(ARM::PC); // Rn is PC.
11031105 Imm8 = 0;
11041106 isAdd = false; // 'U' bit is handled as part of the fixup.
11051107
11451147 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
11461148
11471149 // Encode Rm.
1148 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1150 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
11491151
11501152 // Encode the shift opcode.
11511153 unsigned SBits = 0;
11701172 // Encode the shift operation Rs.
11711173 // Encode Rs bit[11:8].
11721174 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
1173 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
1175 return Binary | (CTX.getRegisterInfo().getEncodingValue(Rs) << ARMII::RegRsShift);
11741176 }
11751177
11761178 unsigned ARMMCCodeEmitter::
11891191 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
11901192
11911193 // Encode Rm.
1192 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1194 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
11931195
11941196 // Encode the shift opcode.
11951197 unsigned SBits = 0;
12281230
12291231 // Encoded as [Rn, Rm, imm].
12301232 // FIXME: Needs fixup support.
1231 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1233 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
12321234 Value <<= 4;
1233 Value |= getARMRegisterNumbering(MO2.getReg());
1235 Value |= CTX.getRegisterInfo().getEncodingValue(MO2.getReg());
12341236 Value <<= 2;
12351237 Value |= MO3.getImm();
12361238
12441246 const MCOperand &MO2 = MI.getOperand(OpNum+1);
12451247
12461248 // FIXME: Needs fixup support.
1247 unsigned Value = getARMRegisterNumbering(MO1.getReg());
1249 unsigned Value = CTX.getRegisterInfo().getEncodingValue(MO1.getReg());
12481250
12491251 // Even though the immediate is 8 bits long, we need 9 bits in order
12501252 // to represent the (inverse of the) sign bit.
13061308 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO1.getImm());
13071309
13081310 // Encode Rm.
1309 unsigned Binary = getARMRegisterNumbering(MO.getReg());
1311 unsigned Binary = CTX.getRegisterInfo().getEncodingValue(MO.getReg());
13101312
13111313 // Encode the shift opcode.
13121314 unsigned SBits = 0;
13621364
13631365 if (SPRRegs || DPRRegs) {
13641366 // VLDM/VSTM
1365 unsigned RegNo = getARMRegisterNumbering(Reg);
1367 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg);
13661368 unsigned NumRegs = (MI.getNumOperands() - Op) & 0xff;
13671369 Binary |= (RegNo & 0x1f) << 8;
13681370 if (SPRRegs)
13711373 Binary |= NumRegs * 2;
13721374 } else {
13731375 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1374 unsigned RegNo = getARMRegisterNumbering(MI.getOperand(I).getReg());
1376 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(MI.getOperand(I).getReg());
13751377 Binary |= 1 << RegNo;
13761378 }
13771379 }
13871389 const MCOperand &Reg = MI.getOperand(Op);
13881390 const MCOperand &Imm = MI.getOperand(Op + 1);
13891391
1390 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1392 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
13911393 unsigned Align = 0;
13921394
13931395 switch (Imm.getImm()) {
14101412 const MCOperand &Reg = MI.getOperand(Op);
14111413 const MCOperand &Imm = MI.getOperand(Op + 1);
14121414
1413 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1415 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
14141416 unsigned Align = 0;
14151417
14161418 switch (Imm.getImm()) {
14361438 const MCOperand &Reg = MI.getOperand(Op);
14371439 const MCOperand &Imm = MI.getOperand(Op + 1);
14381440
1439 unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
1441 unsigned RegNo = CTX.getRegisterInfo().getEncodingValue(Reg.getReg());
14401442 unsigned Align = 0;
14411443
14421444 switch (Imm.getImm()) {
14551457 SmallVectorImpl &Fixups) const {
14561458 const MCOperand &MO = MI.getOperand(Op);
14571459 if (MO.getReg() == 0) return 0x0D;
1458 return getARMRegisterNumbering(MO.getReg());
1460 return CTX.getRegisterInfo().getEncodingValue(MO.getReg());
14591461 }
14601462
14611463 unsigned ARMMCCodeEmitter::