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[RISCV] Don't evaluatePCRelLo if a relocation will be forced (e.g. due to linker relaxation) A pcrel_lo will point to the associated pcrel_hi fixup which in turn points to the real target. RISCVMCExpr::evaluatePCRelLo will work around this indirection in order to allow the fixup to be evaluate properly. However, if relocations are forced (e.g. due to linker relaxation is enabled) then its evaluation is undesired and will result in a relocation with the wrong target. This patch modifies evaluatePCRelLo so it will not try to evaluate if the fixup will be forced as a relocation. A new helper method is added to RISCVAsmBackend to query this. Differential Revision: https://reviews.llvm.org/D59686 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357374 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 1 year, 8 months ago
4 changed file(s) with 29 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
4141
4242 void setForceRelocs() { ForceRelocs = true; }
4343
44 // Returns true if relocations will be forced for shouldForceRelocation by
45 // default. This will be true if relaxation is enabled or had previously
46 // been enabled.
47 bool willForceRelocations() const {
48 return ForceRelocs || STI.getFeatureBits()[RISCV::FeatureRelax];
49 }
50
4451 // Generate diff expression relocations if the relax feature is enabled or had
4552 // previously been enabled, otherwise it is safe for the assembler to
4653 // calculate these internally.
4754 bool requiresDiffExpressionRelocations() const override {
48 return STI.getFeatureBits()[RISCV::FeatureRelax] || ForceRelocs;
55 return willForceRelocations();
4956 }
5057
5158 // Return Size with extra Nop Bytes for alignment directive in code section.
1010 //
1111 //===----------------------------------------------------------------------===//
1212
13 #include "RISCVMCExpr.h"
14 #include "MCTargetDesc/RISCVAsmBackend.h"
1315 #include "RISCV.h"
14 #include "RISCVMCExpr.h"
1516 #include "RISCVFixupKinds.h"
17 #include "llvm/MC/MCAsmLayout.h"
1618 #include "llvm/MC/MCAssembler.h"
1719 #include "llvm/MC/MCContext.h"
1820 #include "llvm/MC/MCStreamer.h"
8688 // ( + ). The Fixup
8789 // is pcrel relative to the VK_RISCV_PCREL_LO fixup, so we need to add the
8890 // offset to the VK_RISCV_PCREL_HI Fixup from VK_RISCV_PCREL_LO to correct.
91
92 // Don't try to evaluate if the fixup will be forced as a relocation (e.g.
93 // as linker relaxation is enabled). If we evaluated pcrel_lo in this case,
94 // the modified fixup will be converted into a relocation that no longer
95 // points to the pcrel_hi as the linker requires.
96 auto &RAB =
97 static_cast(Layout->getAssembler().getBackend());
98 if (RAB.willForceRelocations())
99 return false;
100
89101 MCValue AUIPCLoc;
90102 if (!getSubExpr()->evaluateAsValue(AUIPCLoc, *Layout))
91103 return false;
120120 # RELAX-FIXUP: fixup A - offset: 0, value: %pcrel_hi(bar), kind: fixup_riscv_pcrel_hi20
121121 # RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
122122
123 # TODO/FIXME: The generated PCREL_LO relocations are incorrect.
124 # RISCVMCExpr::evaluatePCRelLo should not be evaluating the fixup when linker
125 # relaxation is enabled.
126
127123 addi t1, t1, %pcrel_lo(2b)
128124 # NORELAX-RELOC-NOT: R_RISCV_PCREL_LO12_I
129125 # NORELAX-RELOC-NOT: R_RISCV_RELAX
130 # RELAX-RELOC: R_RISCV_PCREL_LO12_I bar 0x4
126 # RELAX-RELOC: R_RISCV_PCREL_LO12_I .Ltmp1 0x0
131127 # RELAX-RELOC: R_RISCV_RELAX - 0x0
132128 # RELAX-FIXUP: fixup A - offset: 0, value: %pcrel_lo(.Ltmp1), kind: fixup_riscv_pcrel_lo12_i
133129 # RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
135131 sb t1, %pcrel_lo(2b)(a2)
136132 # NORELAX-RELOC-NOT: R_RISCV_PCREL_LO12_S
137133 # NORELAX-RELOC-NOT: R_RISCV_RELAX
138 # RELAX-RELOC: R_RISCV_PCREL_LO12_S bar 0x8
134 # RELAX-RELOC: R_RISCV_PCREL_LO12_S .Ltmp1 0x0
139135 # RELAX-RELOC: R_RISCV_RELAX - 0x0
140136 # RELAX-FIXUP: fixup A - offset: 0, value: %pcrel_lo(.Ltmp1), kind: fixup_riscv_pcrel_lo12_s
141137 # RELAX-FIXUP: fixup B - offset: 0, value: 0, kind: fixup_riscv_relax
6363 jal zero, .L1
6464 # CHECK-RELOC-NEXT: R_RISCV_BRANCH
6565 beq s1, s1, .L1
66
67 1:
68 # CHECK-RELOC-NEXT: R_RISCV_PCREL_HI20 .L1
69 auipc t1, %pcrel_hi(.L1)
70 # CHECK-RELOC-NEXT: R_RISCV_PCREL_LO12_I .Ltmp0
71 addi t1, t1, %pcrel_lo(1b)