llvm.org GIT mirror llvm / dee46d7
Clean up formatting, remove trailing whitespace, fix comment typos and punctuation. No functional changes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@69378 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 11 years ago
4 changed file(s) with 37 addition(s) and 50 deletion(s). Raw diff Collapse all Expand all
3232 SExt, // The value is sign extended in the location.
3333 ZExt, // The value is zero extended in the location.
3434 AExt, // The value is extended with undefined upper bits.
35 BCvt // The value is bit-converted in the location
35 BCvt // The value is bit-converted in the location.
3636 // TODO: a subset of the value is in the location.
3737 };
3838 private:
4545 /// isMem - True if this is a memory loc, false if it is a register loc.
4646 bool isMem : 1;
4747
48 /// isCustom - True if this arg/retval requires special handling
48 /// isCustom - True if this arg/retval requires special handling.
4949 bool isCustom : 1;
50
50
5151 /// Information about how the value is assigned.
5252 LocInfo HTP : 6;
5353
7171 Ret.LocVT = LocVT;
7272 return Ret;
7373 }
74
74
7575 static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
7676 unsigned RegNo, MVT LocVT,
7777 LocInfo HTP) {
103103 Ret.isCustom = true;
104104 return Ret;
105105 }
106
106
107107 unsigned getValNo() const { return ValNo; }
108108 MVT getValVT() const { return ValVT; }
109109
111111 bool isMemLoc() const { return isMem; }
112112
113113 bool needsCustom() const { return isCustom; }
114
114
115115 unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
116116 unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
117117 MVT getLocVT() const { return LocVT; }
0 //===- ARMCallingConv.td - Calling Conventions for ARM ----------*- C++ -*-===//
1 //
1 //
22 // The LLVM Compiler Infrastructure
33 //
44 // This file is distributed under the University of Illinois Open Source
55 // License. See LICENSE.TXT for details.
6 //
6 //
77 //===----------------------------------------------------------------------===//
88 // This describes the calling conventions for ARM architecture.
99 //===----------------------------------------------------------------------===//
1010
1111 /// CCIfSubtarget - Match if the current subtarget has a feature F.
12 class CCIfSubtarget:
12 class CCIfSubtarget:
1313 CCIf().", F), A>;
1414
1515 /// CCIfAlign - Match of the original alignment of the arg
3838 #include "llvm/Support/MathExtras.h"
3939 using namespace llvm;
4040
41 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
42 MVT &LocVT,
41 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
4342 CCValAssign::LocInfo &LocInfo,
4443 ISD::ArgFlagsTy &ArgFlags,
4544 CCState &State);
46 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
47 MVT &LocVT,
45 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
4846 CCValAssign::LocInfo &LocInfo,
4947 ISD::ArgFlagsTy &ArgFlags,
5048 CCState &State);
51 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
52 MVT &LocVT,
49 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
5350 CCValAssign::LocInfo &LocInfo,
5451 ISD::ArgFlagsTy &ArgFlags,
5552 CCState &State);
56 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
57 MVT &LocVT,
53 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
5854 CCValAssign::LocInfo &LocInfo,
5955 ISD::ArgFlagsTy &ArgFlags,
6056 CCState &State);
398394 #include "ARMGenCallingConv.inc"
399395
400396 // APCS f64 is in register pairs, possibly split to stack
401 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
402 MVT &LocVT,
397 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
403398 CCValAssign::LocInfo &LocInfo,
404399 ISD::ArgFlagsTy &ArgFlags,
405400 CCState &State) {
431426 }
432427
433428 // AAPCS f64 is in aligned register pairs
434 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
435 MVT &LocVT,
429 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
436430 CCValAssign::LocInfo &LocInfo,
437431 ISD::ArgFlagsTy &ArgFlags,
438432 CCState &State) {
455449 return false; // we didn't handle it
456450 }
457451
458 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
459 MVT &LocVT,
452 static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
460453 CCValAssign::LocInfo &LocInfo,
461454 ISD::ArgFlagsTy &ArgFlags,
462455 CCState &State) {
479472 return false; // we didn't handle it
480473 }
481474
482 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT,
483 MVT &LocVT,
475 static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
484476 CCValAssign::LocInfo &LocInfo,
485477 ISD::ArgFlagsTy &ArgFlags,
486478 CCState &State) {
557549
558550 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
559551 /// by "Src" to address "Dst" of size "Size". Alignment information is
560 /// specified by the specific parameter attribute. The copy will be passed as
552 /// specified by the specific parameter attribute. The copy will be passed as
561553 /// a byval function parameter.
562554 /// Sometimes what we are copying is the end of a larger object, the part that
563555 /// does not fit in registers.
570562 /*AlwaysInline=*/false, NULL, 0, NULL, 0);
571563 }
572564
573 /// LowerMemOpCallTo - Store the argument to the stack
565 /// LowerMemOpCallTo - Store the argument to the stack.
574566 SDValue
575567 ARMTargetLowering::LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
576568 const SDValue &StackPtr,
577 const CCValAssign &VA,
578 SDValue Chain,
569 const CCValAssign &VA, SDValue Chain,
579570 SDValue Arg, ISD::ArgFlagsTy Flags) {
580571 DebugLoc dl = TheCall->getDebugLoc();
581572 unsigned LocMemOffset = VA.getLocMemOffset();
620611 SmallVector MemOpChains;
621612
622613 // Walk the register/memloc assignments, inserting copies/loads. In the case
623 // of tail call optimization arguments are handle later.
614 // of tail call optimization, arguments are handled later.
624615 for (unsigned i = 0, realArgIdx = 0, e = ArgLocs.size();
625616 i != e;
626617 ++i, ++realArgIdx) {
653644 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd));
654645 VA = ArgLocs[++i]; // skip ahead to next loc
655646 if (VA.isRegLoc())
656 RegsToPass.push_back(std::make_pair(VA.getLocReg(),
657 fmrrd.getValue(1)));
647 RegsToPass.push_back(std::make_pair(VA.getLocReg(), fmrrd.getValue(1)));
658648 else {
659649 assert(VA.isMemLoc());
660650 if (StackPtr.getNode() == 0)
790780 SDValue Chain = Op.getOperand(0);
791781 DebugLoc dl = Op.getDebugLoc();
792782
793 // CCValAssign - represent the assignment of
794 // the return value to a location
783 // CCValAssign - represent the assignment of the return value to a location.
795784 SmallVector RVLocs;
796785 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
797786 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
798787
799 // CCState - Info about the registers and stack slot.
788 // CCState - Info about the registers and stack slots.
800789 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
801790
802 // Analize return values of ISD::RET
791 // Analyze return values of ISD::RET.
803792 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_ARM);
804793
805794 // If this is the first return lowered for this function, add
843832 } else
844833 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
845834
846 // guarantee that all emitted copies are
847 // stuck together, avoiding something bad
835 // Guarantee that all emitted copies are
836 // stuck together, avoiding something bad.
848837 Flag = Chain.getValue(1);
849838 }
850839
10981087 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
10991088 CCValAssign &VA = ArgLocs[i];
11001089
1101 // Arguments stored on registers
1090 // Arguments stored in registers.
11021091 if (VA.isRegLoc()) {
11031092 MVT RegVT = VA.getLocVT();
11041093 TargetRegisterClass *RC;
11081097 RC = ARM::GPRRegisterClass;
11091098
11101099 if (RegVT == MVT::f64) {
1111 // f64 is passed in pairs of GPRs and must be combined
1100 // f64 is passed in pairs of GPRs and must be combined.
11121101 RegVT = MVT::i32;
11131102 } else if (!((RegVT == MVT::i32) || (RegVT == MVT::f32)))
11141103 assert(0 && "RegVT not supported by FORMAL_ARGUMENTS Lowering");
11151104
1116 // Transform the arguments stored on
1117 // physical registers into virtual ones
1105 // Transform the arguments stored in physical registers into virtual ones.
11181106 unsigned Reg = AddLiveIn(MF, VA.getLocReg(), RC);
11191107 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, RegVT);
11201108
1121 // f64 is passed in i32 pairs and must be combined
1109 // f64 is passed in i32 pairs and must be combined.
11221110 if (VA.needsCustom()) {
11231111 SDValue ArgValue2;
11241112
11281116 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
11291117 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
11301118
1131 // Create load node to retrieve arguments from the stack
1119 // Create load node to retrieve arguments from the stack.
11321120 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
11331121 ArgValue2 = DAG.getLoad(MVT::i32, dl, Root, FIN, NULL, 0);
11341122 } else {
11721160 unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
11731161 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset());
11741162
1175 // Create load nodes to retrieve arguments from the stack
1163 // Create load nodes to retrieve arguments from the stack.
11761164 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
11771165 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN, NULL, 0));
11781166 }
11841172 ARM::R0, ARM::R1, ARM::R2, ARM::R3
11851173 };
11861174
1187 unsigned NumGPRs = CCInfo.getFirstUnallocated(GPRArgRegs,
1188 sizeof(GPRArgRegs)/sizeof(GPRArgRegs[0]));
1175 unsigned NumGPRs = CCInfo.getFirstUnallocated
1176 (GPRArgRegs, sizeof(GPRArgRegs) / sizeof(GPRArgRegs[0]));
11891177
11901178 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
11911179 unsigned VARegSize = (4 - NumGPRs) * 4;
149149
150150 SDValue LowerMemOpCallTo(CallSDNode *TheCall, SelectionDAG &DAG,
151151 const SDValue &StackPtr, const CCValAssign &VA,
152 SDValue Chain,
153 SDValue Arg, ISD::ArgFlagsTy Flags);
154 SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
152 SDValue Chain, SDValue Arg, ISD::ArgFlagsTy Flags);
153 SDNode *LowerCallResult(SDValue Chain, SDValue InFlag, CallSDNode *TheCall,
155154 unsigned CallingConv, SelectionDAG &DAG);
156155 SDValue LowerCALL(SDValue Op, SelectionDAG &DAG);
157156 SDValue LowerRET(SDValue Op, SelectionDAG &DAG);