llvm.org GIT mirror llvm / debf7d3
Fix PR15630: Replace faulty stdcx. with stwcx. When doing a partword atomic operation, a lwarx was being paired with a stdcx. instead of a stwcx. when compiling for a 64-bit target. The target has nothing to do with it in this case; we always need a stwcx. Thanks to Kai Nacke for reporting the problem. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178559 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Schmidt 7 years ago
2 changed file(s) with 17 addition(s) and 1 deletion(s). Raw diff Collapse all Expand all
59595959 .addReg(TmpReg).addReg(MaskReg);
59605960 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
59615961 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5962 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5962 BuildMI(BB, dl, TII->get(PPC::STWCX))
59635963 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
59645964 BuildMI(BB, dl, TII->get(PPC::BCC))
59655965 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
0 ; RUN: llc -mcpu=pwr7 -O0 < %s | FileCheck %s
1
2 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
3 target triple = "powerpc64-unknown-linux-gnu"
4
5 define weak_odr void @_D4core6atomic49__T11atomicStoreVE4core6atomic11MemoryOrder3ThThZ11atomicStoreFNaNbKOhhZv(i8* %val_arg, i8 zeroext %newval_arg) {
6 entry:
7 %newval = alloca i8
8 %ordering = alloca i32, align 4
9 store i8 %newval_arg, i8* %newval
10 %tmp = load i8* %newval
11 store atomic volatile i8 %tmp, i8* %val_arg seq_cst, align 1
12 ret void
13 }
14
15 ; CHECK: stwcx.