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Thumb disassembler was erroneously rejecting "blx sp" instruction. rdar://problem/9267838 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129320 91177308-0d34-0410-b5e6-96231b3b80d8 Johnny Chen 9 years ago
4 changed file(s) with 27 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
365365 T1Special<{1,1,0,?}> {
366366 // A6.2.3 & A8.6.25
367367 let Inst{6-3} = 0b1110; // Rm = lr
368 let Inst{2-0} = 0b000;
369 }
370
371 def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm",
372 [/* for disassembly only */]>,
373 T1Special<{1,1,0,?}> {
374 // A6.2.3 & A8.6.25
375 bits<4> Rm;
376 let Inst{6-3} = Rm;
368377 let Inst{2-0} = 0b000;
369378 }
370379
484484 return true;
485485
486486 // BX/BLX has 1 reg operand: Rm.
487 if (NumOps == 1) {
487 if (Opcode == ARM::tBLXr_r9 || Opcode == ARM::tBX_Rm) {
488 // Handling the two predicate operands before the reg operand.
489 if (!B->DoPredicateOperands(MI, Opcode, insn, NumOps))
490 return false;
488491 MI.addOperand(MCOperand::CreateReg(getRegisterEnum(B, ARM::GPRRegClassID,
489492 getT1Rm(insn))));
490 NumOpsAdded = 1;
493 NumOpsAdded = 3;
491494 return true;
492495 }
493496
213213
214214 # CHECK: lsr.w r10, r0, #32
215215 0x4f 0xea 0x10 0x0a
216
217 # CHECK: blx sp
218 0xe8 0x47
219
220 # CHECK: bx lr
221 0x70 0x47
222
223 # CHECK: bx pc
224 0x78 0x47
16231623 if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr")
16241624 return false;
16251625
1626 // A8.6.25 BX. Use the generic tBX_Rm, ignore tBX_RET and tBX_RET_vararg.
1627 if (Name == "tBX_RET" || Name == "tBX_RET_vararg")
1628 return false;
1629
16261630 // Ignore the TPsoft (TLS) instructions, which conflict with tBLr9.
16271631 if (Name == "tTPsoft" || Name == "t2TPsoft")
16281632 return false;