llvm.org GIT mirror llvm / ddfd137
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function to finalize MI bundles (i.e. add BUNDLE instruction and computing register def and use lists of the BUNDLE instruction) and a pass to unpack bundles. - Teach more of MachineBasic and MachineInstr methods to be bundle aware. - Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to prevent IT blocks from being broken apart. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146542 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
28 changed file(s) with 658 addition(s) and 174 deletion(s). Raw diff Collapse all Expand all
193193 return tmp;
194194 }
195195
196 IterTy getInsnIterator() const {
196 IterTy getInstrIterator() const {
197197 return MII;
198198 }
199199 };
200200
201 typedef Instructions::iterator insn_iterator;
202 typedef Instructions::const_iterator const_insn_iterator;
203 typedef std::reverse_iterator reverse_insn_iterator;
201 typedef Instructions::iterator instr_iterator;
202 typedef Instructions::const_iterator const_instr_iterator;
203 typedef std::reverse_iterator reverse_instr_iterator;
204204 typedef
205 std::reverse_iteratorn_iterator> const_reverse_insn_iterator;
205 std::reverse_iteratortr_iterator> const_reverse_instr_iterator;
206206
207207 typedef
208 bundle_iteratorn_iterator> iterator;
208 bundle_iteratortr_iterator> iterator;
209209 typedef
210 bundle_iteratorn_iterator> const_iterator;
210 bundle_iteratortr_iterator> const_iterator;
211211 typedef std::reverse_iterator const_reverse_iterator;
212212 typedef std::reverse_iterator reverse_iterator;
213213
220220 const MachineInstr& front() const { return Insts.front(); }
221221 const MachineInstr& back() const { return Insts.back(); }
222222
223 insn_iterator insn_begin() { return Insts.begin(); }
224 const_insn_iterator insn_begin() const { return Insts.begin(); }
225 insn_iterator insn_end() { return Insts.end(); }
226 const_insn_iterator insn_end() const { return Insts.end(); }
227 reverse_insn_iterator insn_rbegin() { return Insts.rbegin(); }
228 const_reverse_insn_iterator insn_rbegin() const { return Insts.rbegin(); }
229 reverse_insn_iterator insn_rend () { return Insts.rend(); }
230 const_reverse_insn_iterator insn_rend () const { return Insts.rend(); }
223 instr_iterator instr_begin() { return Insts.begin(); }
224 const_instr_iterator instr_begin() const { return Insts.begin(); }
225 instr_iterator instr_end() { return Insts.end(); }
226 const_instr_iterator instr_end() const { return Insts.end(); }
227 reverse_instr_iterator instr_rbegin() { return Insts.rbegin(); }
228 const_reverse_instr_iterator instr_rbegin() const { return Insts.rbegin(); }
229 reverse_instr_iterator instr_rend () { return Insts.rend(); }
230 const_reverse_instr_iterator instr_rend () const { return Insts.rend(); }
231231
232232 iterator begin() { return Insts.begin(); }
233233 const_iterator begin() const { return Insts.begin(); }
234234 iterator end() {
235 insn_iterator II = insn_end();
236 if (II != insn_begin()) {
235 instr_iterator II = instr_end();
236 if (II != instr_begin()) {
237237 while (II->isInsideBundle())
238238 --II;
239239 }
240240 return II;
241241 }
242242 const_iterator end() const {
243 const_insn_iterator II = insn_end();
244 if (II != insn_begin()) {
243 const_instr_iterator II = instr_end();
244 if (II != instr_begin()) {
245245 while (II->isInsideBundle())
246246 --II;
247247 }
248248 return II;
249249 }
250250 reverse_iterator rbegin() {
251 reverse_insn_iterator II = insn_rbegin();
252 if (II != insn_rend()) {
251 reverse_instr_iterator II = instr_rbegin();
252 if (II != instr_rend()) {
253253 while (II->isInsideBundle())
254254 ++II;
255255 }
256256 return II;
257257 }
258258 const_reverse_iterator rbegin() const {
259 const_reverse_insn_iterator II = insn_rbegin();
260 if (II != insn_rend()) {
259 const_reverse_instr_iterator II = instr_rbegin();
260 if (II != instr_rend()) {
261261 while (II->isInsideBundle())
262262 ++II;
263263 }
441441 iterator getFirstTerminator();
442442 const_iterator getFirstTerminator() const;
443443
444 /// getFirstInsnTerminator - Same getFirstTerminator but it ignores bundles
445 /// and return an insn_iterator instead.
446 insn_iterator getFirstInsnTerminator();
444 /// getFirstInstrTerminator - Same getFirstTerminator but it ignores bundles
445 /// and return an instr_iterator instead.
446 instr_iterator getFirstInstrTerminator();
447447
448448 /// getLastNonDebugInstr - returns an iterator to the last non-debug
449449 /// instruction in the basic block, or end()
463463 void push_back(MachineInstr *MI) { Insts.push_back(MI); }
464464
465465 template
466 void insert(insn_iterator I, IT S, IT E) {
466 void insert(instr_iterator I, IT S, IT E) {
467467 Insts.insert(I, S, E);
468468 }
469 insn_iterator insert(insn_iterator I, MachineInstr *M) {
469 instr_iterator insert(instr_iterator I, MachineInstr *M) {
470470 return Insts.insert(I, M);
471471 }
472 insn_iterator insertAfter(insn_iterator I, MachineInstr *M) {
472 instr_iterator insertAfter(instr_iterator I, MachineInstr *M) {
473473 return Insts.insertAfter(I, M);
474474 }
475475
476476 template
477477 void insert(iterator I, IT S, IT E) {
478 Insts.insert(I.getInsnIterator(), S, E);
478 Insts.insert(I.getInstrIterator(), S, E);
479479 }
480480 iterator insert(iterator I, MachineInstr *M) {
481 return Insts.insert(I.getInsnIterator(), M);
481 return Insts.insert(I.getInstrIterator(), M);
482482 }
483483 iterator insertAfter(iterator I, MachineInstr *M) {
484 return Insts.insertAfter(I.getInsnIterator(), M);
485 }
486
487 // erase - Remove the specified element or range from the instruction list.
488 // These functions delete any instructions removed.
489 //
490 insn_iterator erase(insn_iterator I) {
484 return Insts.insertAfter(I.getInstrIterator(), M);
485 }
486
487 /// erase - Remove the specified element or range from the instruction list.
488 /// These functions delete any instructions removed.
489 ///
490 instr_iterator erase(instr_iterator I) {
491491 return Insts.erase(I);
492492 }
493 insn_iterator erase(insn_iterator I, insn_iterator E) {
493 instr_iterator erase(instr_iterator I, instr_iterator E) {
494494 return Insts.erase(I, E);
495495 }
496
497 iterator erase(iterator I) {
498 return Insts.erase(I.getInsnIterator());
499 }
496 instr_iterator erase_instr(MachineInstr *I) {
497 instr_iterator MII(I);
498 return erase(MII);
499 }
500
501 iterator erase(iterator I);
500502 iterator erase(iterator I, iterator E) {
501 return Insts.erase(I.getInsnIterator(), E.getInsnIterator());
502 }
503
504 iterator erase(MachineInstr *I) { iterator MII(I); return erase(MII); }
505 MachineInstr *remove(MachineInstr *I) { return Insts.remove(I); }
506 void clear() { Insts.clear(); }
503 return Insts.erase(I.getInstrIterator(), E.getInstrIterator());
504 }
505 iterator erase(MachineInstr *I) {
506 iterator MII(I);
507 return erase(MII);
508 }
509
510 /// remove - Remove the instruction from the instruction list. This function
511 /// does not delete the instruction. WARNING: Note, if the specified
512 /// instruction is a bundle this function will remove all the bundled
513 /// instructions as well. It is up to the caller to keep a list of the
514 /// bundled instructions and re-insert them if desired. This function is
515 /// *not recommended* for manipulating instructions with bundled. Use
516 /// splice instead.
517 MachineInstr *remove(MachineInstr *I);
518 void clear() {
519 Insts.clear();
520 }
507521
508522 /// splice - Take an instruction from MBB 'Other' at the position From,
509523 /// and insert it into this MBB right before 'where'.
510 void splice(insn_iterator where, MachineBasicBlock *Other,
511 insn_iterator From) {
524 void splice(instr_iterator where, MachineBasicBlock *Other,
525 instr_iterator From) {
512526 Insts.splice(where, Other->Insts, From);
513527 }
514 void splice(iterator where, MachineBasicBlock *Other, iterator From) {
515 Insts.splice(where.getInsnIterator(), Other->Insts, From.getInsnIterator());
516 }
528 void splice(iterator where, MachineBasicBlock *Other, iterator From);
517529
518530 /// splice - Take a block of instructions from MBB 'Other' in the range [From,
519531 /// To), and insert them into this MBB right before 'where'.
520 void splice(insn_iterator where, MachineBasicBlock *Other, insn_iterator From,
521 insn_iterator To) {
532 void splice(instr_iterator where, MachineBasicBlock *Other, instr_iterator From,
533 instr_iterator To) {
522534 Insts.splice(where, Other->Insts, From, To);
523535 }
524536 void splice(iterator where, MachineBasicBlock *Other, iterator From,
525537 iterator To) {
526 Insts.splice(where.getInsnIterator(), Other->Insts,
527 From.getInsnIterator(), To.getInsnIterator());
538 Insts.splice(where.getInstrIterator(), Other->Insts,
539 From.getInstrIterator(), To.getInstrIterator());
528540 }
529541
530542 /// removeFromParent - This method unlinks 'this' from the containing
551563
552564 /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
553565 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
554 DebugLoc findDebugLoc(insn_iterator MBBI);
566 DebugLoc findDebugLoc(instr_iterator MBBI);
555567 DebugLoc findDebugLoc(iterator MBBI) {
556 return findDebugLoc(MBBI.getInsnIterator());
568 return findDebugLoc(MBBI.getInstrIterator());
557569 }
558570
559571 // Debugging methods.
174174 Flags = flags;
175175 }
176176
177 /// clearFlag - Clear a MI flag.
178 void clearFlag(MIFlag Flag) {
179 Flags &= ~((uint8_t)Flag);
180 }
181
177182 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
178183 /// in a bundle).
179184 ///
212217 /// a bundle, but the next three MIs are.
213218 bool isInsideBundle() const {
214219 return getFlag(InsideBundle);
220 }
221
222 /// setIsInsideBundle - Set InsideBundle bit.
223 ///
224 void setIsInsideBundle(bool Val = true) {
225 if (Val)
226 setFlag(InsideBundle);
227 else
228 clearFlag(InsideBundle);
215229 }
216230
217231 /// getDebugLoc - Returns the debug location id of this MachineInstr.
588602 bool isRegSequence() const {
589603 return getOpcode() == TargetOpcode::REG_SEQUENCE;
590604 }
605 bool isBundle() const {
606 return getOpcode() == TargetOpcode::BUNDLE;
607 }
591608 bool isCopy() const {
592609 return getOpcode() == TargetOpcode::COPY;
593610 }
606623 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
607624 getOperand(0).getSubReg() == getOperand(1).getSubReg();
608625 }
626
627 /// getBundleSize - Return the number of instructions inside the MI bundle.
628 unsigned getBundleSize() const;
609629
610630 /// readsRegister - Return true if the MachineInstr reads the specified
611631 /// register. If TargetRegisterInfo is passed, then it also checks if there
208208 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
209209 }
210210
211 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
212 MachineBasicBlock::instr_iterator I,
213 DebugLoc DL,
214 const MCInstrDesc &MCID,
215 unsigned DestReg) {
216 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
217 BB.insert(I, MI);
218 return MachineInstrBuilder(MI).addReg(DestReg, RegState::Define);
219 }
220
221 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
222 MachineInstr *I,
223 DebugLoc DL,
224 const MCInstrDesc &MCID,
225 unsigned DestReg) {
226 if (I->isInsideBundle()) {
227 MachineBasicBlock::instr_iterator MII = I;
228 return BuildMI(BB, MII, DL, MCID, DestReg);
229 }
230
231 MachineBasicBlock::iterator MII = I;
232 return BuildMI(BB, MII, DL, MCID, DestReg);
233 }
234
211235 /// BuildMI - This version of the builder inserts the newly-built
212236 /// instruction before the given position in the given MachineBasicBlock, and
213237 /// does NOT take a destination register.
221245 return MachineInstrBuilder(MI);
222246 }
223247
248 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
249 MachineBasicBlock::instr_iterator I,
250 DebugLoc DL,
251 const MCInstrDesc &MCID) {
252 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL);
253 BB.insert(I, MI);
254 return MachineInstrBuilder(MI);
255 }
256
257 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
258 MachineInstr *I,
259 DebugLoc DL,
260 const MCInstrDesc &MCID) {
261 if (I->isInsideBundle()) {
262 MachineBasicBlock::instr_iterator MII = I;
263 return BuildMI(BB, MII, DL, MCID);
264 }
265
266 MachineBasicBlock::iterator MII = I;
267 return BuildMI(BB, MII, DL, MCID);
268 }
269
224270 /// BuildMI - This version of the builder inserts the newly-built
225271 /// instruction at the end of the given MachineBasicBlock, and does NOT take a
226272 /// destination register.
0 //===-- CodeGen/MachineInstBundle.h - MI bundle utilities -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file provide utility functions to manipulate machine instruction
10 // bundles.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef LLVM_CODEGEN_MACHINEINSTRBUNDLE_H
15 #define LLVM_CODEGEN_MACHINEINSTRBUNDLE_H
16
17 #include "llvm/CodeGen/MachineBasicBlock.h"
18
19 namespace llvm {
20
21 /// FinalizeBundle - Finalize a machine instruction bundle which includes
22 /// a sequence of instructions starting from FirstMI to LastMI (inclusive).
23 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
24 /// IsInternalRead markers to MachineOperands which are defined inside the
25 /// bundle, and it copies externally visible defs and uses to the BUNDLE
26 /// instruction.
27 void FinalizeBundle(MachineBasicBlock &MBB,
28 MachineBasicBlock::instr_iterator FirstMI,
29 MachineBasicBlock::instr_iterator LastMI);
30
31 } // End llvm namespace
32
33 #endif
237237 ///
238238 FunctionPass *createExecutionDependencyFixPass(const TargetRegisterClass *RC);
239239
240 /// createUnpackMachineBundles - This pass unpack machine instruction bundles.
241 ///
242 FunctionPass *createUnpackMachineBundlesPass();
243
240244 } // End llvm namespace
241245
242246 #endif
230230 void initializeVerifierPass(PassRegistry&);
231231 void initializeVirtRegMapPass(PassRegistry&);
232232 void initializeInstSimplifierPass(PassRegistry&);
233 void initializeUnpackMachineBundlesPass(PassRegistry&);
233234
234235 }
235236
925925 if (MergePotentials.size() >= 2)
926926 MadeChange |= TryTailMergeBlocks(IBB, PredBB);
927927 // Reinsert an unconditional branch if needed.
928 // The 1 below can occur as a result of removing blocks in TryTailMergeBlocks.
929 PredBB = prior(I); // this may have been changed in TryTailMergeBlocks
928 // The 1 below can occur as a result of removing blocks in
929 // TryTailMergeBlocks.
930 PredBB = prior(I); // this may have been changed in TryTailMergeBlocks
930931 if (MergePotentials.size() == 1 &&
931932 MergePotentials.begin()->getBlock() != PredBB)
932933 FixTail(MergePotentials.begin()->getBlock(), IBB, TII);
7272
7373 // Make sure the instructions have their operands in the reginfo lists.
7474 MachineRegisterInfo &RegInfo = MF.getRegInfo();
75 for (MachineBasicBlock::insn_iterator I = N->insn_begin(), E = N->insn_end();
76 I != E; ++I)
75 for (MachineBasicBlock::instr_iterator
76 I = N->instr_begin(), E = N->instr_end(); I != E; ++I)
7777 I->AddRegOperandsToUseLists(RegInfo);
7878
7979 LeakDetector::removeGarbageObject(N);
140140 }
141141
142142 MachineBasicBlock::iterator MachineBasicBlock::getFirstNonPHI() {
143 insn_iterator I = insn_begin();
143 instr_iterator I = instr_begin();
144144 while (I != end() && I->isPHI())
145145 ++I;
146146 assert(!I->isInsideBundle() && "First non-phi MI cannot be inside a bundle!");
177177 return I;
178178 }
179179
180 MachineBasicBlock::insn_iterator MachineBasicBlock::getFirstInsnTerminator() {
181 insn_iterator I = insn_end();
182 while (I != insn_begin() && ((--I)->isTerminator() || I->isDebugValue()))
180 MachineBasicBlock::instr_iterator MachineBasicBlock::getFirstInstrTerminator() {
181 instr_iterator I = instr_end();
182 while (I != instr_begin() && ((--I)->isTerminator() || I->isDebugValue()))
183183 ; /*noop */
184 while (I != insn_end() && !I->isTerminator())
184 while (I != instr_end() && !I->isTerminator())
185185 ++I;
186186 return I;
187187 }
188188
189189 MachineBasicBlock::iterator MachineBasicBlock::getLastNonDebugInstr() {
190190 // Skip over end-of-block dbg_value instructions.
191 insn_iterator B = insn_begin(), I = insn_end();
191 instr_iterator B = instr_begin(), I = instr_end();
192192 while (I != B) {
193193 --I;
194194 // Return instruction that starts a bundle.
203203 MachineBasicBlock::const_iterator
204204 MachineBasicBlock::getLastNonDebugInstr() const {
205205 // Skip over end-of-block dbg_value instructions.
206 const_insn_iterator B = insn_begin(), I = insn_end();
206 const_instr_iterator B = instr_begin(), I = instr_end();
207207 while (I != B) {
208208 --I;
209209 // Return instruction that starts a bundle.
282282 OS << '\n';
283283 }
284284
285 for (const_iterator I = begin(); I != end(); ++I) {
285 for (const_instr_iterator I = instr_begin(); I != instr_end(); ++I) {
286286 if (Indexes) {
287287 if (Indexes->hasIndex(I))
288288 OS << Indexes->getInstructionIndex(I);
289289 OS << '\t';
290290 }
291291 OS << '\t';
292 if (I->isInsideBundle())
293 OS << " * ";
292294 I->print(OS, &getParent()->getTarget());
293295 }
294296
494496 fromMBB->removeSuccessor(Succ);
495497
496498 // Fix up any PHI nodes in the successor.
497 for (MachineBasicBlock::insn_iterator MI = Succ->insn_begin(),
498 ME = Succ->insn_end(); MI != ME && MI->isPHI(); ++MI)
499 for (MachineBasicBlock::instr_iterator MI = Succ->instr_begin(),
500 ME = Succ->instr_end(); MI != ME && MI->isPHI(); ++MI)
499501 for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
500502 MachineOperand &MO = MI->getOperand(i);
501503 if (MO.getMBB() == fromMBB)
597599 // Collect a list of virtual registers killed by the terminators.
598600 SmallVector KilledRegs;
599601 if (LV)
600 for (insn_iterator I = getFirstInsnTerminator(), E = insn_end();
602 for (instr_iterator I = getFirstInstrTerminator(), E = instr_end();
601603 I != E; ++I) {
602604 MachineInstr *MI = I;
603605 for (MachineInstr::mop_iterator OI = MI->operands_begin(),
625627 }
626628
627629 // Fix PHI nodes in Succ so they refer to NMBB instead of this
628 for (MachineBasicBlock::insn_iterator
629 i = Succ->insn_begin(),e = Succ->insn_end(); i != e && i->isPHI(); ++i)
630 for (MachineBasicBlock::instr_iterator
631 i = Succ->instr_begin(),e = Succ->instr_end();
632 i != e && i->isPHI(); ++i)
630633 for (unsigned ni = 1, ne = i->getNumOperands(); ni != ne; ni += 2)
631634 if (i->getOperand(ni+1).getMBB() == this)
632635 i->getOperand(ni+1).setMBB(NMBB);
641644 // Restore kills of virtual registers that were killed by the terminators.
642645 while (!KilledRegs.empty()) {
643646 unsigned Reg = KilledRegs.pop_back_val();
644 for (insn_iterator I = insn_end(), E = insn_begin(); I != E;) {
647 for (instr_iterator I = instr_end(), E = instr_begin(); I != E;) {
645648 if (!(--I)->addRegisterKilled(Reg, NULL, /* addIfNotFound= */ false))
646649 continue;
647650 LV->getVarInfo(Reg).Kills.push_back(I);
710713 return NMBB;
711714 }
712715
716 MachineBasicBlock::iterator
717 MachineBasicBlock::erase(MachineBasicBlock::iterator I) {
718 if (I->isBundle()) {
719 MachineBasicBlock::iterator E = llvm::next(I);
720 return Insts.erase(I.getInstrIterator(), E.getInstrIterator());
721 }
722
723 return Insts.erase(I.getInstrIterator());
724 }
725
726 MachineInstr *MachineBasicBlock::remove(MachineInstr *I) {
727 if (I->isBundle()) {
728 MachineBasicBlock::instr_iterator MII = I; ++MII;
729 while (MII != end() && MII->isInsideBundle()) {
730 MachineInstr *MI = &*MII++;
731 Insts.remove(MI);
732 }
733 }
734
735 return Insts.remove(I);
736 }
737
738 void MachineBasicBlock::splice(MachineBasicBlock::iterator where,
739 MachineBasicBlock *Other,
740 MachineBasicBlock::iterator From) {
741 if (From->isBundle()) {
742 MachineBasicBlock::iterator To = llvm::next(From);
743 Insts.splice(where.getInstrIterator(), Other->Insts,
744 From.getInstrIterator(), To.getInstrIterator());
745 return;
746 }
747
748 Insts.splice(where.getInstrIterator(), Other->Insts, From.getInstrIterator());
749 }
750
713751 /// removeFromParent - This method unlinks 'this' from the containing function,
714752 /// and returns it, but does not delete it.
715753 MachineBasicBlock *MachineBasicBlock::removeFromParent() {
733771 MachineBasicBlock *New) {
734772 assert(Old != New && "Cannot replace self with self!");
735773
736 MachineBasicBlock::insn_iterator I = insn_end();
737 while (I != insn_begin()) {
774 MachineBasicBlock::instr_iterator I = instr_end();
775 while (I != instr_begin()) {
738776 --I;
739777 if (!I->isTerminator()) break;
740778
815853 /// findDebugLoc - find the next valid DebugLoc starting at MBBI, skipping
816854 /// any DBG_VALUE instructions. Return UnknownLoc if there is none.
817855 DebugLoc
818 MachineBasicBlock::findDebugLoc(insn_iterator MBBI) {
856 MachineBasicBlock::findDebugLoc(instr_iterator MBBI) {
819857 DebugLoc DL;
820 insn_iterator E = insn_end();
858 instr_iterator E = instr_end();
821859 if (MBBI == E)
822860 return DL;
823861
749749
750750 bool
751751 MachineInstr::hasProperty(unsigned MCFlag, QueryType Type) const {
752 if (Type == IgnoreBundle || getOpcode() != TargetOpcode::BUNDLE)
752 if (Type == IgnoreBundle || !isBundle())
753753 return getDesc().getFlags() & (1 << MCFlag);
754754
755755 const MachineBasicBlock *MBB = getParent();
756 MachineBasicBlock::const_insn_iterator MII = *this; ++MII;
756 MachineBasicBlock::const_instr_iterator MII = *this; ++MII;
757757 while (MII != MBB->end() && MII->isInsideBundle()) {
758758 if (MII->getDesc().getFlags() & (1 << MCFlag)) {
759759 if (Type == AnyInBundle)
775775 if (Other->getOpcode() != getOpcode() ||
776776 Other->getNumOperands() != getNumOperands())
777777 return false;
778
779 if (isBundle()) {
780 // Both instructions are bundles, compare MIs inside the bundle.
781 MachineBasicBlock::const_instr_iterator I1 = *this;
782 MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end();
783 MachineBasicBlock::const_instr_iterator I2 = *Other;
784 MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end();
785 while (++I1 != E1 && I1->isInsideBundle()) {
786 ++I2;
787 if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(I2, Check))
788 return false;
789 }
790 }
778791
779792 // Check operands to make sure they match.
780793 for (unsigned i = 0, e = getNumOperands(); i != e; ++i) {
824837 assert(getParent() && "Not embedded in a basic block!");
825838
826839 // If it's a bundle then remove the MIs inside the bundle as well.
827 if (getOpcode() == TargetOpcode::BUNDLE) {
840 if (isBundle()) {
828841 MachineBasicBlock *MBB = getParent();
829 MachineBasicBlock::insn_iterator MII = *this; ++MII;
830 while (MII != MBB->end() && MII->isInsideBundle()) {
842 MachineBasicBlock::instr_iterator MII = *this; ++MII;
843 MachineBasicBlock::instr_iterator E = MBB->instr_end();
844 while (MII != E && MII->isInsideBundle()) {
831845 MachineInstr *MI = &*MII;
832846 ++MII;
833847 MBB->remove(MI);
843857 void MachineInstr::eraseFromParent() {
844858 assert(getParent() && "Not embedded in a basic block!");
845859 // If it's a bundle then remove the MIs inside the bundle as well.
846 if (getOpcode() == TargetOpcode::BUNDLE) {
860 if (isBundle()) {
847861 MachineBasicBlock *MBB = getParent();
848 MachineBasicBlock::insn_iterator MII = *this; ++MII;
849 while (MII != MBB->end() && MII->isInsideBundle()) {
862 MachineBasicBlock::instr_iterator MII = *this; ++MII;
863 MachineBasicBlock::instr_iterator E = MBB->instr_end();
864 while (MII != E && MII->isInsideBundle()) {
850865 MachineInstr *MI = &*MII;
851866 ++MII;
852867 MBB->erase(MI);
939954 return TRI->getPointerRegClass();
940955
941956 return NULL;
957 }
958
959 /// getBundleSize - Return the number of instructions inside the MI bundle.
960 unsigned MachineInstr::getBundleSize() const {
961 assert(isBundle() && "Expecting a bundle");
962
963 MachineBasicBlock::const_instr_iterator I = *this;
964 unsigned Size = 0;
965 while ((++I)->isInsideBundle()) {
966 ++Size;
967 }
968 assert(Size > 1 && "Malformed bundle");
969
970 return Size;
942971 }
943972
944973 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
10231052 /// operand list that is used to represent the predicate. It returns -1 if
10241053 /// none is found.
10251054 int MachineInstr::findFirstPredOperandIdx() const {
1026 assert(getOpcode() != TargetOpcode::BUNDLE &&
1027 "MachineInstr::findFirstPredOperandIdx() can't handle bundles");
1028
10291055 // Don't call MCID.findFirstPredOperandIdx() because this variant
10301056 // is sometimes called on an instruction that's not yet complete, and
10311057 // so the number of operands is less than the MCID indicates. In
11751201
11761202 /// copyPredicates - Copies predicate operand(s) from MI.
11771203 void MachineInstr::copyPredicates(const MachineInstr *MI) {
1178 assert(getOpcode() != TargetOpcode::BUNDLE &&
1179 "MachineInstr::copyPredicates() can't handle bundles");
1204 assert(!isBundle() && "MachineInstr::copyPredicates() can't handle bundles");
11801205
11811206 const MCInstrDesc &MCID = MI->getDesc();
11821207 if (!MCID.isPredicable())
0 //===-- lib/CodeGen/MachineInstrBundle.cpp --------------------------------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8
9 #include "llvm/CodeGen/MachineInstrBundle.h"
10 #include "llvm/CodeGen/MachineInstrBuilder.h"
11 #include "llvm/CodeGen/Passes.h"
12 #include "llvm/CodeGen/MachineFunctionPass.h"
13 #include "llvm/Target/TargetInstrInfo.h"
14 #include "llvm/Target/TargetMachine.h"
15 #include "llvm/Target/TargetRegisterInfo.h"
16 #include "llvm/ADT/SmallSet.h"
17 #include "llvm/ADT/SmallVector.h"
18 using namespace llvm;
19
20 namespace {
21 class UnpackMachineBundles : public MachineFunctionPass {
22 public:
23 static char ID; // Pass identification
24 UnpackMachineBundles() : MachineFunctionPass(ID) {
25 initializeUnpackMachineBundlesPass(*PassRegistry::getPassRegistry());
26 }
27
28 virtual bool runOnMachineFunction(MachineFunction &MF);
29 };
30 } // end anonymous namespace
31
32 char UnpackMachineBundles::ID = 0;
33 INITIALIZE_PASS(UnpackMachineBundles, "unpack-mi-bundle",
34 "Unpack machine instruction bundles", false, false)
35
36 FunctionPass *llvm::createUnpackMachineBundlesPass() {
37 return new UnpackMachineBundles();
38 }
39
40 bool UnpackMachineBundles::runOnMachineFunction(MachineFunction &MF) {
41 bool Changed = false;
42 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) {
43 MachineBasicBlock *MBB = &*I;
44
45 for (MachineBasicBlock::instr_iterator MII = MBB->instr_begin(),
46 MIE = MBB->instr_end(); MII != MIE; ) {
47 MachineInstr *MI = &*MII;
48
49 // Remove BUNDLE instruction and the InsideBundle flags from bundled
50 // instructions.
51 if (MI->isBundle()) {
52 while (++MII != MIE && MII->isInsideBundle()) {
53 MII->setIsInsideBundle(false);
54 for (unsigned i = 0, e = MII->getNumOperands(); i != e; ++i) {
55 MachineOperand &MO = MII->getOperand(i);
56 if (MO.isReg() && MO.isInternalRead())
57 MO.setIsInternalRead(false);
58 }
59 }
60 MI->eraseFromParent();
61
62 Changed = true;
63 continue;
64 }
65
66 ++MII;
67 }
68 }
69
70 return Changed;
71 }
72
73 /// FinalizeBundle - Finalize a machine instruction bundle which includes
74 /// a sequence of instructions starting from FirstMI to LastMI (inclusive).
75 /// This routine adds a BUNDLE instruction to represent the bundle, it adds
76 /// IsInternalRead markers to MachineOperands which are defined inside the
77 /// bundle, and it copies externally visible defs and uses to the BUNDLE
78 /// instruction.
79 void llvm::FinalizeBundle(MachineBasicBlock &MBB,
80 MachineBasicBlock::instr_iterator FirstMI,
81 MachineBasicBlock::instr_iterator LastMI) {
82 const TargetMachine &TM = MBB.getParent()->getTarget();
83 const TargetInstrInfo *TII = TM.getInstrInfo();
84 const TargetRegisterInfo *TRI = TM.getRegisterInfo();
85
86 MachineInstrBuilder MIB = BuildMI(MBB, FirstMI, FirstMI->getDebugLoc(),
87 TII->get(TargetOpcode::BUNDLE));
88
89 SmallVector LocalDefs;
90 SmallSet LocalDefSet;
91 SmallSet DeadDefSet;
92 SmallSet KilledDefSet;
93 SmallVector ExternUses;
94 SmallSet ExternUseSet;
95 SmallSet KilledUseSet;
96 SmallSet UndefUseSet;
97 SmallVector Defs;
98 do {
99 for (unsigned i = 0, e = FirstMI->getNumOperands(); i != e; ++i) {
100 MachineOperand &MO = FirstMI->getOperand(i);
101 if (!MO.isReg())
102 continue;
103 if (MO.isDef()) {
104 Defs.push_back(&MO);
105 continue;
106 }
107
108 unsigned Reg = MO.getReg();
109 if (!Reg)
110 continue;
111 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
112 if (LocalDefSet.count(Reg)) {
113 MO.setIsInternalRead();
114 if (MO.isKill())
115 // Internal def is now killed.
116 KilledDefSet.insert(Reg);
117 } else {
118 if (ExternUseSet.insert(Reg)) {
119 ExternUses.push_back(Reg);
120 if (MO.isUndef())
121 UndefUseSet.insert(Reg);
122 }
123 if (MO.isKill())
124 // External def is now killed.
125 KilledUseSet.insert(Reg);
126 }
127 }
128
129 for (unsigned i = 0, e = Defs.size(); i != e; ++i) {
130 MachineOperand &MO = *Defs[i];
131 unsigned Reg = MO.getReg();
132 if (!Reg)
133 continue;
134
135 if (LocalDefSet.insert(Reg)) {
136 LocalDefs.push_back(Reg);
137 if (MO.isDead()) {
138 DeadDefSet.insert(Reg);
139 }
140 } else {
141 // Re-defined inside the bundle, it's no longer killed.
142 KilledDefSet.erase(Reg);
143 if (!MO.isDead())
144 // Previously defined but dead.
145 DeadDefSet.erase(Reg);
146 }
147
148 if (!MO.isDead()) {
149 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg);
150 unsigned SubReg = *SubRegs; ++SubRegs) {
151 if (LocalDefSet.insert(SubReg))
152 LocalDefs.push_back(SubReg);
153 }
154 }
155 }
156
157 FirstMI->setIsInsideBundle();
158 Defs.clear();
159 } while (FirstMI++ != LastMI);
160
161 SmallSet Added;
162 for (unsigned i = 0, e = LocalDefs.size(); i != e; ++i) {
163 unsigned Reg = LocalDefs[i];
164 if (Added.insert(Reg)) {
165 // If it's not live beyond end of the bundle, mark it dead.
166 bool isDead = DeadDefSet.count(Reg) || KilledDefSet.count(Reg);
167 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
168 getImplRegState(true));
169 }
170 }
171
172 for (unsigned i = 0, e = ExternUses.size(); i != e; ++i) {
173 unsigned Reg = ExternUses[i];
174 bool isKill = KilledUseSet.count(Reg);
175 bool isUndef = UndefUseSet.count(Reg);
176 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
177 getImplRegState(true));
178 }
179 }
278278 for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end();
279279 MFI!=MFE; ++MFI) {
280280 visitMachineBasicBlockBefore(MFI);
281 for (MachineBasicBlock::const_iterator MBBI = MFI->begin(),
282 MBBE = MFI->end(); MBBI != MBBE; ++MBBI) {
281 for (MachineBasicBlock::const_instr_iterator MBBI = MFI->instr_begin(),
282 MBBE = MFI->instr_end(); MBBI != MBBE; ++MBBI) {
283283 if (MBBI->getParent() != MFI) {
284284 report("Bad instruction parent pointer", MFI);
285285 *OS << "Instruction: " << *MBBI;
286286 continue;
287287 }
288 // Skip BUNDLE instruction for now. FIXME: We should add code to verify
289 // the BUNDLE's specifically.
290 if (MBBI->isBundle())
291 continue;
288292 visitMachineInstrBefore(MBBI);
289293 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I)
290294 visitMachineOperand(&MBBI->getOperand(I), I);
211211 RegClassInfo.runOnMachineFunction(Fn);
212212
213213 // Check for explicit enable/disable of post-ra scheduling.
214 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode = TargetSubtargetInfo::ANTIDEP_NONE;
214 TargetSubtargetInfo::AntiDepBreakMode AntiDepMode =
215 TargetSubtargetInfo::ANTIDEP_NONE;
215216 SmallVector CriticalPathRCs;
216217 if (EnablePostRAScheduler.getPosition() > 0) {
217218 if (!EnablePostRAScheduler)
270271 }
271272 I = MI;
272273 --Count;
274 if (MI->isBundle())
275 Count -= MI->getBundleSize();
273276 }
274277 assert(Count == 0 && "Instruction count mismatch!");
275278 assert((MBB->begin() == Current || CurrentCount != 0) &&
276276 continue;
277277 if (DefSU != SU &&
278278 (Kind != SDep::Output || !MO.isDead() ||
279 !DefSU->getInstr()->registerDefIsDead(Reg)))
279 !DefSU->getInstr()->registerDefIsDead(Reg))) {
280280 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg));
281 }
281282 }
282283 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) {
283284 std::vector &MemDefList = Defs[*Alias];
656657
657658 // EmitSchedule - Emit the machine code in scheduled order.
658659 MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
659 // For MachineInstr-based scheduling, we're rescheduling the instructions in
660 // the block, so start by removing them from the block.
661 while (Begin != InsertPos) {
662 MachineBasicBlock::iterator I = Begin;
663 ++Begin;
664 BB->remove(I);
665 }
660 Begin = InsertPos;
666661
667662 // If first instruction was a DBG_VALUE then put it back.
668663 if (FirstDbgValue)
669 BB->insert(InsertPos, FirstDbgValue);
664 BB->splice(InsertPos, BB, FirstDbgValue);
670665
671666 // Then re-insert them according to the given schedule.
672667 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
673668 if (SUnit *SU = Sequence[i])
674 BB->insert(InsertPos, SU->getInstr());
669 BB->splice(InsertPos, BB, SU->getInstr());
675670 else
676671 // Null SUnit* is a noop.
677672 EmitNoop();
688683 std::pair P = *prior(DI);
689684 MachineInstr *DbgValue = P.first;
690685 MachineBasicBlock::iterator OrigPrivMI = P.second;
691 BB->insertAfter(OrigPrivMI, DbgValue);
686 BB->splice(++OrigPrivMI, BB, DbgValue);
692687 }
693688 DbgValues.clear();
694689 FirstDbgValue = NULL;
120120 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
121121 unsigned &SrcOpIdx1,
122122 unsigned &SrcOpIdx2) const {
123 assert(MI->getOpcode() != TargetOpcode::BUNDLE &&
123 assert(!MI->isBundle() &&
124124 "TargetInstrInfoImpl::findCommutedOpIndices() can't handle bundles");
125125
126126 const MCInstrDesc &MCID = MI->getDesc();
155155 const SmallVectorImpl &Pred) const {
156156 bool MadeChange = false;
157157
158 assert(MI->getOpcode() != TargetOpcode::BUNDLE &&
158 assert(!MI->isBundle() &&
159159 "TargetInstrInfoImpl::PredicateInstruction() can't handle bundles");
160160
161161 const MCInstrDesc &MCID = MI->getDesc();
438438 return false;
439439 }
440440
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442 if (MI->isBundle()) {
443 MachineBasicBlock::const_instr_iterator I = MI;
444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445 while (++I != E && I->isInsideBundle()) {
446 int PIdx = I->findFirstPredOperandIdx();
447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
448 return true;
449 }
450 return false;
451 }
452
453 int PIdx = MI->findFirstPredOperandIdx();
454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
455 }
456
441457 bool ARMBaseInstrInfo::
442458 PredicateInstruction(MachineInstr *MI,
443459 const SmallVectorImpl &Pred) const {
546562 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
547563 if (MI->isLabel())
548564 return 0;
549 unsigned Opc = MI->getOpcode();
565 unsigned Opc = MI->getOpcode();
550566 switch (Opc) {
551567 case TargetOpcode::IMPLICIT_DEF:
552568 case TargetOpcode::KILL:
554570 case TargetOpcode::EH_LABEL:
555571 case TargetOpcode::DBG_VALUE:
556572 return 0;
573 case TargetOpcode::BUNDLE:
574 return getInstBundleLength(MI);
557575 case ARM::MOVi16_ga_pcrel:
558576 case ARM::MOVTi16_ga_pcrel:
559577 case ARM::t2MOVi16_ga_pcrel:
618636 return 0;
619637 }
620638 return 0; // Not reached
639 }
640
641 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
642 unsigned Size = 0;
643 MachineBasicBlock::const_instr_iterator I = MI;
644 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
645 while (++I != E && I->isInsideBundle()) {
646 assert(!I->isBundle() && "No nested bundle!");
647 Size += GetInstSizeInBytes(&*I);
648 }
649 return Size;
621650 }
622651
623652 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
19541983 bool isKill = UseMI->getOperand(OpIdx).isKill();
19551984 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
19561985 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
1957 *UseMI, UseMI->getDebugLoc(),
1986 UseMI, UseMI->getDebugLoc(),
19581987 get(NewUseOpc), NewReg)
19591988 .addReg(Reg1, getKillRegState(isKill))
19601989 .addImm(SOImmValV1)));
23292358 return UseCycle;
23302359 }
23312360
2361 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
2362 const MachineInstr *MI,
2363 unsigned &DefIdx, unsigned &Dist) {
2364 Dist = 0;
2365
2366 MachineBasicBlock::const_iterator I = MI; ++I;
2367 MachineBasicBlock::const_instr_iterator II =
2368 llvm::prior(I.getInstrIterator());
2369 assert(II->isInsideBundle() && "Empty bundle?");
2370
2371 int Idx = -1;
2372 unsigned Reg = MI->getOperand(DefIdx).getReg();
2373 while (II->isInsideBundle()) {
2374 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
2375 if (Idx != -1)
2376 break;
2377 --II;
2378 ++Dist;
2379 }
2380
2381 assert(Idx != -1 && "Cannot find bundled definition!");
2382 DefIdx = Idx;
2383 return II;
2384 }
2385
2386 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
2387 const MachineInstr *MI,
2388 unsigned &UseIdx, unsigned &Dist) {
2389 Dist = 0;
2390
2391 MachineBasicBlock::const_instr_iterator II = MI; ++II;
2392 assert(II->isInsideBundle() && "Empty bundle?");
2393 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2394
2395 // FIXME: This doesn't properly handle multiple uses.
2396 int Idx = -1;
2397 unsigned Reg = MI->getOperand(UseIdx).getReg();
2398 while (II != E && II->isInsideBundle()) {
2399 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
2400 if (Idx != -1)
2401 break;
2402 if (II->getOpcode() != ARM::t2IT)
2403 ++Dist;
2404 ++II;
2405 }
2406
2407 assert(Idx != -1 && "Cannot find bundled definition!");
2408 UseIdx = Idx;
2409 return II;
2410 }
2411
23322412 int
23332413 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
23342414 const MachineInstr *DefMI, unsigned DefIdx,
23402420 if (!ItinData || ItinData->isEmpty())
23412421 return DefMI->mayLoad() ? 3 : 1;
23422422
2343 const MCInstrDesc &DefMCID = DefMI->getDesc();
2344 const MCInstrDesc &UseMCID = UseMI->getDesc();
2423 const MCInstrDesc *DefMCID = &DefMI->getDesc();
2424 const MCInstrDesc *UseMCID = &UseMI->getDesc();
23452425 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
23462426 if (DefMO.getReg() == ARM::CPSR) {
23472427 if (DefMI->getOpcode() == ARM::FMSTAT) {
23522432 // CPSR set and branch can be paired in the same cycle.
23532433 if (UseMI->isBranch())
23542434 return 0;
2435
2436 // Otherwise it takes the instruction latency (generally one).
2437 int Latency = getInstrLatency(ItinData, DefMI);
2438 // For Thumb2, prefer scheduling CPSR setting instruction close to its uses.
2439 // Instructions which are otherwise scheduled between them may incur a code
2440 // size penalty (not able to use the CPSR setting 16-bit instructions).
2441 if (Latency > 0 && Subtarget.isThumb2())
2442 --Latency;
2443 return Latency;
23552444 }
23562445
23572446 unsigned DefAlign = DefMI->hasOneMemOperand()
23582447 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
23592448 unsigned UseAlign = UseMI->hasOneMemOperand()
23602449 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
2361 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
2362 UseMCID, UseIdx, UseAlign);
2450
2451 unsigned DefAdj = 0;
2452 if (DefMI->isBundle()) {
2453 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, DefIdx, DefAdj);
2454 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
2455 DefMI->isRegSequence() || DefMI->isImplicitDef())
2456 return 1;
2457 DefMCID = &DefMI->getDesc();
2458 }
2459 unsigned UseAdj = 0;
2460 if (UseMI->isBundle()) {
2461 UseMI = getBundledUseMI(&getRegisterInfo(), UseMI, UseIdx, UseAdj);
2462 UseMCID = &UseMI->getDesc();
2463 }
2464
2465 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
2466 *UseMCID, UseIdx, UseAlign);
2467 int Adj = DefAdj + UseAdj;
2468 if (Adj) {
2469 Latency -= (int)(DefAdj + UseAdj);
2470 if (Latency < 1)
2471 return 1;
2472 }
23632473
23642474 if (Latency > 1 &&
23652475 (Subtarget.isCortexA8() || Subtarget.isCortexA9())) {
23662476 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
23672477 // variants are one cycle cheaper.
2368 switch (DefMCID.getOpcode()) {
2478 switch (DefMCID->getOpcode()) {
23692479 default: break;
23702480 case ARM::LDRrs:
23712481 case ARM::LDRBrs: {
23902500 }
23912501
23922502 if (DefAlign < 8 && Subtarget.isCortexA9())
2393 switch (DefMCID.getOpcode()) {
2503 switch (DefMCID->getOpcode()) {
23942504 default: break;
23952505 case ARM::VLD1q8:
23962506 case ARM::VLD1q16:
26962806 if (!ItinData || ItinData->isEmpty())
26972807 return 1;
26982808
2809 if (MI->isBundle()) {
2810 int Latency = 0;
2811 MachineBasicBlock::const_instr_iterator I = MI;
2812 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
2813 while (++I != E && I->isInsideBundle()) {
2814 if (I->getOpcode() != ARM::t2IT)
2815 Latency += getInstrLatency(ItinData, I, PredCost);
2816 }
2817 return Latency;
2818 }
2819
26992820 const MCInstrDesc &MCID = MI->getDesc();
27002821 unsigned Class = MCID.getSchedClass();
27012822 unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
6868 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
6969
7070 // Predication support.
71 bool isPredicated(const MachineInstr *MI) const {
72 int PIdx = MI->findFirstPredOperandIdx();
73 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
74 }
71 bool isPredicated(const MachineInstr *MI) const;
7572
7673 ARMCC::CondCodes getPredicate(const MachineInstr *MI) const {
7774 int PIdx = MI->findFirstPredOperandIdx();
218215 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
219216
220217 private:
218 unsigned getInstBundleLength(const MachineInstr *MI) const;
219
221220 int getVLDMDefCycle(const InstrItineraryData *ItinData,
222221 const MCInstrDesc &DefMCID,
223222 unsigned DefClass,
701701 TargetRegisterClass* RC = TLI.getRegClassFor(VT);
702702 unsigned ResultReg = createResultReg(RC);
703703 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
704 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
704 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
705705 TII.get(Opc), ResultReg)
706706 .addFrameIndex(SI->second)
707707 .addImm(0));
897897 ARM::GPRRegisterClass;
898898 unsigned ResultReg = createResultReg(RC);
899899 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
900 AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
900 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
901901 TII.get(Opc), ResultReg)
902902 .addFrameIndex(Addr.Base.FI)
903903 .addImm(0));
3737 MachineInstr *MI = SU->getInstr();
3838
3939 if (!MI->isDebugValue()) {
40 if (ITBlockSize && MI != ITBlockMIs[ITBlockSize-1])
41 return Hazard;
42
4340 // Look for special VMLA / VMLS hazards. A VMUL / VADD / VSUB following
4441 // a VMLA / VMLS will cause 4 cycle stall.
4542 const MCInstrDesc &MCID = MI->getDesc();
7572 void ARMHazardRecognizer::Reset() {
7673 LastMI = 0;
7774 FpMLxStalls = 0;
78 ITBlockSize = 0;
7975 ScoreboardHazardRecognizer::Reset();
8076 }
8177
8278 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
8379 MachineInstr *MI = SU->getInstr();
84 unsigned Opcode = MI->getOpcode();
85 if (ITBlockSize) {
86 --ITBlockSize;
87 } else if (Opcode == ARM::t2IT) {
88 unsigned Mask = MI->getOperand(1).getImm();
89 unsigned NumTZ = CountTrailingZeros_32(Mask);
90 assert(NumTZ <= 3 && "Invalid IT mask!");
91 ITBlockSize = 4 - NumTZ;
92 MachineBasicBlock::iterator I = MI;
93 for (unsigned i = 0; i < ITBlockSize; ++i) {
94 // Advance to the next instruction, skipping any dbg_value instructions.
95 do {
96 ++I;
97 } while (I->isDebugValue());
98 ITBlockMIs[ITBlockSize-1-i] = &*I;
99 }
100 }
101
10280 if (!MI->isDebugValue()) {
10381 LastMI = MI;
10482 FpMLxStalls = 0;
3333
3434 MachineInstr *LastMI;
3535 unsigned FpMLxStalls;
36 unsigned ITBlockSize; // No. of MIs in current IT block yet to be scheduled.
37 MachineInstr *ITBlockMIs[4];
3836
3937 public:
4038 ARMHazardRecognizer(const InstrItineraryData *ItinData,
4341 const ARMSubtarget &sti,
4442 const ScheduleDAG *DAG) :
4543 ScoreboardHazardRecognizer(ItinData, DAG, "post-RA-sched"), TII(tii),
46 TRI(tri), STI(sti), LastMI(0), ITBlockSize(0) {}
44 TRI(tri), STI(sti), LastMI(0) {}
4745
4846 virtual HazardType getHazardType(SUnit *SU, int Stalls);
4947 virtual void Reset();
146146 }
147147
148148 bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM) {
149 if (Subtarget.isThumb2() && !Subtarget.prefers32BitThumb())
150 PM.add(createThumb2SizeReductionPass());
149 if (Subtarget.isThumb2()) {
150 if (!Subtarget.prefers32BitThumb())
151 PM.add(createThumb2SizeReductionPass());
152
153 // Constant island pass work on unbundled instructions.
154 PM.add(createUnpackMachineBundlesPass());
155 }
151156
152157 PM.add(createARMConstantIslandPass());
158
153159 return true;
154160 }
155161
221221 const MCInstrDesc &MCID2 = TII->get(AddSubOpc);
222222 unsigned TmpReg = MRI->createVirtualRegister(TII->getRegClass(MCID1, 0, TRI));
223223
224 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID1, TmpReg)
224 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
225225 .addReg(Src1Reg, getKillRegState(Src1Kill))
226226 .addReg(Src2Reg, getKillRegState(Src2Kill));
227227 if (HasLane)
228228 MIB.addImm(LaneImm);
229229 MIB.addImm(Pred).addReg(PredReg);
230230
231 MIB = BuildMI(MBB, *MI, MI->getDebugLoc(), MCID2)
231 MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID2)
232232 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
233233
234234 if (NegAcc) {
1212 #include "Thumb2InstrInfo.h"
1313 #include "llvm/CodeGen/MachineInstr.h"
1414 #include "llvm/CodeGen/MachineInstrBuilder.h"
15 #include "llvm/CodeGen/MachineInstrBundle.h"
1516 #include "llvm/CodeGen/MachineFunctionPass.h"
1617 #include "llvm/ADT/SmallSet.h"
1718 #include "llvm/ADT/Statistic.h"
236237 // Last instruction in IT block kills ITSTATE.
237238 LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill();
238239
240 // Finalize the bundle.
241 FinalizeBundle(MBB, InsertPos.getInstrIterator(), LastITMI);
242
239243 Modified = true;
240244 ++NumITs;
241245 }
451451
452452 // Add the 16-bit load / store instruction.
453453 DebugLoc dl = MI->getDebugLoc();
454 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
454 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
455455 if (!isLdStMul) {
456456 MIB.addOperand(MI->getOperand(0));
457457 MIB.addOperand(MI->getOperand(1));
477477
478478 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
479479
480 MBB.erase(MI);
480 MBB.erase_instr(MI);
481481 ++NumLdSts;
482482 return true;
483483 }
512512 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
513513 return false;
514514
515 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(),
515 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(),
516516 TII->get(ARM::tADDrSPi))
517517 .addOperand(MI->getOperand(0))
518518 .addOperand(MI->getOperand(1))
524524
525525 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB);
526526
527 MBB.erase(MI);
527 MBB.erase_instr(MI);
528528 ++NumNarrows;
529529 return true;
530530 }
652652
653653 // Add the 16-bit instruction.
654654 DebugLoc dl = MI->getDebugLoc();
655 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID);
655 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
656656 MIB.addOperand(MI->getOperand(0));
657657 if (NewMCID.hasOptionalDef()) {
658658 if (HasCC)
676676
677677 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
678678
679 MBB.erase(MI);
679 MBB.erase_instr(MI);
680680 ++Num2Addrs;
681681 return true;
682682 }
743743
744744 // Add the 16-bit instruction.
745745 DebugLoc dl = MI->getDebugLoc();
746 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID);
746 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
747747 MIB.addOperand(MI->getOperand(0));
748748 if (NewMCID.hasOptionalDef()) {
749749 if (HasCC)
783783
784784 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
785785
786 MBB.erase(MI);
786 MBB.erase_instr(MI);
787787 ++NumNarrows;
788788 return true;
789789 }
828828 // Yes, CPSR could be livein.
829829 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
830830 MachineInstr *CPSRDef = 0;
831 MachineInstr *BundleMI = 0;
831832
832833 // If this BB loops back to itself, conservatively avoid narrowing the
833834 // first instruction that does partial flag update.
834835 bool IsSelfLoop = MBB.isSuccessor(&MBB);
835 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
836 MachineBasicBlock::iterator NextMII;
836 MachineBasicBlock::instr_iterator MII = MBB.instr_begin(), E = MBB.instr_end();
837 MachineBasicBlock::instr_iterator NextMII;
837838 for (; MII != E; MII = NextMII) {
838839 NextMII = llvm::next(MII);
839840
840841 MachineInstr *MI = &*MII;
842 if (MI->isBundle()) {
843 BundleMI = MI;
844 continue;
845 }
846
841847 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
842848
843849 unsigned Opcode = MI->getOpcode();
848854 if (Entry.Special) {
849855 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
850856 Modified = true;
851 MachineBasicBlock::iterator I = prior(NextMII);
857 MachineBasicBlock::instr_iterator I = prior(NextMII);
852858 MI = &*I;
853859 }
854860 goto ProcessNext;
858864 if (Entry.NarrowOpc2 &&
859865 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
860866 Modified = true;
861 MachineBasicBlock::iterator I = prior(NextMII);
867 MachineBasicBlock::instr_iterator I = prior(NextMII);
862868 MI = &*I;
863869 goto ProcessNext;
864870 }
867873 if (Entry.NarrowOpc1 &&
868874 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
869875 Modified = true;
870 MachineBasicBlock::iterator I = prior(NextMII);
876 MachineBasicBlock::instr_iterator I = prior(NextMII);
871877 MI = &*I;
872878 }
873879 }
874880
875881 ProcessNext:
882 if (LiveCPSR &&
883 NextMII != E && MI->isInsideBundle() && !NextMII->isInsideBundle() &&
884 BundleMI->killsRegister(ARM::CPSR))
885 // FIXME: Since post-ra scheduler operates on bundles, the CPSR kill
886 // marker is only on the BUNDLE instruction. Process the BUNDLE
887 // instruction as we finish with the bundled instruction to work around
888 // the inconsistency.
889 LiveCPSR = false;
890
876891 bool DefCPSR = false;
877892 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
878893 if (MI->isCall()) {
15271527 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
15281528 // Build and insert into an implicit UNDEF value. This is OK because
15291529 // well be shifting and then extracting the lower 16-bits.
1530 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
1530 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
15311531 InsMI2 =
1532 BuildMI(*MFI, MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
1532 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
15331533 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
15341534 .addReg(Src2, getKillRegState(isKill2));
15351535 addRegReg(MIB, leaInReg, true, leaInReg2, true);
None ; RUN: llc < %s - | FileCheck %s
0 ; RUN: llc < %s | FileCheck %s
11 ; Radar 9309221
22 ; Test dwarf reg no for d16
33 ;CHECK: DW_OP_regx
2424 ; CHECK: lsr{{.*}}r2
2525 ; CHECK-NEXT: rsb r3, r2, #32
2626 ; CHECK-NEXT: sub r2, r2, #32
27 ; CHECK-NEXT: orr r0, r0, r1, lsl r3
2728 ; CHECK-NEXT: cmp r2, #0
28 ; CHECK-NEXT: orr r0, r0, r1, lsl r3
2929 ; CHECK-NEXT: asrge r0, r1, r2
3030 %a = ashr i64 %x, %y
3131 %b = trunc i64 %a to i32
3737 ; CHECK: lsr{{.*}}r2
3838 ; CHECK-NEXT: rsb r3, r2, #32
3939 ; CHECK-NEXT: sub r2, r2, #32
40 ; CHECK-NEXT: orr r0, r0, r1, lsl r3
4041 ; CHECK-NEXT: cmp r2, #0
41 ; CHECK-NEXT: orr r0, r0, r1, lsl r3
4242 ; CHECK-NEXT: lsrge r0, r1, r2
4343 %a = lshr i64 %x, %y
4444 %b = trunc i64 %a to i32
9393
9494 bb: ; preds = %bb, %bb.nph
9595 ; CHECK: bb
96 ; CHECK: eor.w
9697 ; CHECK: eor.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]]
97 ; CHECK: eor.w
9898 ; CHECK-NOT: eor
9999 ; CHECK: and
100100 %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; [#uses=2]
22 define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
33 ; CHECK: t1
44 ; CHECK: mvn r0, #-2147483648
5 ; CHECK: cmp r2, #10
56 ; CHECK: add r0, r1
6 ; CHECK: cmp r2, #10
77 ; CHECK: it gt
88 ; CHECK: movgt r0, r1
99 %tmp1 = icmp sgt i32 %c, 10