llvm.org GIT mirror llvm / dd99f3a
Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91223 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
2 changed file(s) with 15 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
10571057 return false;
10581058 }
10591059
1060 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when 16-bit
1060 /// convertToThreeAddressWithLEA - Helper for convertToThreeAddress when
10611061 /// 16-bit LEA is disabled, use 32-bit LEA to form 3-address code by promoting
10621062 /// to a 32-bit superregister and then truncating back down to a 16-bit
10631063 /// subregister.
10801080
10811081 // Build and insert into an implicit UNDEF value. This is OK because
10821082 // well be shifting and then extracting the lower 16-bits.
1083 // This has the potential to cause partial stall. e.g.
1083 // This has the potential to cause partial register stall. e.g.
10841084 // movw (%rbp,%rcx,2), %dx
10851085 // leal -65(%rdx), %esi
1086 // But testing has shown this *does* help performance (at least on modern
1087 // x86 machines).
1086 // But testing has shown this *does* help performance in 64-bit mode (at
1087 // least on modern x86 machines).
10881088 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
10891089 MachineInstr *InsMI =
10901090 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::INSERT_SUBREG),leaInReg)
11881188 MachineInstr *NewMI = NULL;
11891189 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
11901190 // we have better subtarget support, enable the 16-bit LEA generation here.
1191 // 16-bit LEA is also slow on Core2.
11911192 bool DisableLEA16 = true;
1193 bool is64Bit = TM.getSubtarget().is64Bit();
11921194
11931195 unsigned MIOpc = MI->getOpcode();
11941196 switch (MIOpc) {
12271229 unsigned ShAmt = MI->getOperand(2).getImm();
12281230 if (ShAmt == 0 || ShAmt >= 4) return 0;
12291231
1230 unsigned Opc = TM.getSubtarget().is64Bit() ?
1231 X86::LEA64_32r : X86::LEA32r;
1232 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
12321233 NewMI = BuildMI(MF, MI->getDebugLoc(), get(Opc))
12331234 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
12341235 .addReg(0).addImm(1 << ShAmt)
12431244 if (ShAmt == 0 || ShAmt >= 4) return 0;
12441245
12451246 if (DisableLEA16)
1246 return convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV);
1247 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
12471248 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
12481249 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
12491250 .addReg(0).addImm(1 << ShAmt)
12581259 if (hasLiveCondCodeDef(MI))
12591260 return 0;
12601261
1261 bool is64Bit = TM.getSubtarget().is64Bit();
12621262 switch (MIOpc) {
12631263 default: return 0;
12641264 case X86::INC64r:
12761276 case X86::INC16r:
12771277 case X86::INC64_16r:
12781278 if (DisableLEA16)
1279 return convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV);
1279 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
12801280 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
12811281 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
12821282 .addReg(Dest, RegState::Define |
12981298 case X86::DEC16r:
12991299 case X86::DEC64_16r:
13001300 if (DisableLEA16)
1301 return convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV);
1301 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
13021302 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
13031303 NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
13041304 .addReg(Dest, RegState::Define |
13221322 }
13231323 case X86::ADD16rr: {
13241324 if (DisableLEA16)
1325 return convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV);
1325 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
13261326 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
13271327 unsigned Src2 = MI->getOperand(2).getReg();
13281328 bool isKill2 = MI->getOperand(2).isKill();
13551355 case X86::ADD16ri:
13561356 case X86::ADD16ri8:
13571357 if (DisableLEA16)
1358 return convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV);
1358 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : 0;
13591359 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
13601360 NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
13611361 .addReg(Dest, RegState::Define |
None ; RUN: llc < %s -mtriple=i386-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=32BIT
1 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -asm-verbose=false | FileCheck %s -check-prefix=64BIT
1 ; rdar://7329206
2
3 ; In 32-bit the partial register stall would degrade performance.
24
35 define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
46 entry: