llvm.org GIT mirror llvm / dd11988
Properly pseudo-ize the ARM LDMIA_RET instruction. This has the nice side- effect that we get proper instruction printing using the "pop" mnemonic for it. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127502 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
13 changed file(s) with 32 addition(s) and 28 deletion(s). Raw diff Collapse all Expand all
944944 unsigned Opc = MI->getOpcode();
945945 switch (Opc) {
946946 default: break;
947 case ARM::LDMIA_RET: {
948 // LDMIA_RET is just a normal LDMIA_UPD instruction that targets PC and as
949 // such has additional code-gen properties and scheduling information.
950 // To emit it, we just construct as normal and set the opcode to LDMIA_UPD.
951 MCInst TmpInst;
952 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
953 TmpInst.setOpcode(ARM::LDMIA_UPD);
954 OutStreamer.EmitInstruction(TmpInst);
955 return;
956 }
947957 case ARM::t2ADDrSPi:
948958 case ARM::t2ADDrSPi12:
949959 case ARM::t2SUBrSPi:
19271927 // FIXME: Should pc be an implicit operand like PICADD, etc?
19281928 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
19291929 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
1930 // FIXME: Should be a pseudo-instruction.
1931 def LDMIA_RET : AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1932 reglist:$regs, variable_ops),
1933 IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr,
1934 "ldmia${p}\t$Rn!, $regs",
1935 "$Rn = $wb", []> {
1936 let Inst{24-23} = 0b01; // Increment After
1937 let Inst{21} = 1; // Writeback
1938 let Inst{20} = 1; // Load
1939 }
1930 def LDMIA_RET : ARMPseudoInst<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
1931 reglist:$regs, variable_ops),
1932 Size4Bytes, IIC_iLoad_mBr, []>,
1933 RegConstraint<"$Rn = $wb">;
19401934
19411935 //===----------------------------------------------------------------------===//
19421936 // Move Instructions.
55 entry:
66 %0 = tail call i32 @foo(i32 %a) nounwind ; [#uses=1]
77 %1 = add nsw i32 %0, 3 ; [#uses=1]
8 ; CHECK: ldmia sp!, {r11, pc}
8 ; CHECK: pop {r11, pc}
99 ; V4: pop
1010 ; V4-NEXT: mov pc, lr
1111 ret i32 %1
33 ; was being treated as an instruction count.
44
55 ; CHECK: push
6 ; CHECK: ldmia
7 ; CHECK: ldmia
8 ; CHECK: ldmia
6 ; CHECK: pop
7 ; CHECK: pop
8 ; CHECK: pop
99
1010 define i32 @test(i32 %x) {
1111 entry:
99 ; ARM: bl _foo
1010 ; ARM: bl _foo
1111 ; ARM: bl _foo
12 ; ARM: ldmia sp!, {r7, pc}
12 ; ARM: pop {r7, pc}
1313
1414 ; THUMB2: t:
1515 ; THUMB2: push
2323
2424 bb18: ; preds = %bb1
2525 ; CHECK-NOT: bx
26 ; CHECK: ldmia sp!
26 ; CHECK: pop
2727 ret void
2828 }
2929
7171 br i1 %4, label %bb1, label %bb3
7272
7373 ; CHECK: LBB1_[[RET]]: @ %bb5
74 ; CHECK: ldmia sp!
74 ; CHECK: pop
7575 bb5: ; preds = %bb3, %entry
7676 %sum.1.lcssa = phi i32 [ 0, %entry ], [ %sum.0.lcssa, %bb3 ] ; [#uses=1]
7777 ret i32 %sum.1.lcssa
88 ; CHECK: t:
99 ; CHECK: vpop {d8}
1010 ; CHECK-NOT: vpopne
11 ; CHECK: ldmia sp!, {r7, pc}
11 ; CHECK: pop {r7, pc}
1212 ; CHECK: vpop {d8}
13 ; CHECK: ldmia sp!, {r7, pc}
13 ; CHECK: pop {r7, pc}
1414 br i1 undef, label %if.else, label %if.then
1515
1616 if.then: ; preds = %entry
1010
1111 define i32 @t1(i32 %a, i32 %b) {
1212 ; CHECK: t1:
13 ; CHECK: ldmialt sp!, {r7, pc}
13 ; CHECK: poplt {r7, pc}
1414 entry:
1515 %tmp1 = icmp sgt i32 %a, 10 ; [#uses=1]
1616 br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
22 define void @foo(i32 %X, i32 %Y) {
33 entry:
44 ; CHECK: cmpne
5 ; CHECK: ldmiahi sp!
5 ; CHECK: pophi
66 %tmp1 = icmp ult i32 %X, 4 ; [#uses=1]
77 %tmp4 = icmp eq i32 %Y, 0 ; [#uses=1]
88 %tmp7 = or i1 %tmp4, %tmp1 ; [#uses=1]
55 define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
66 ; CHECK: cmpeq
77 ; CHECK: moveq
8 ; CHECK: ldmiaeq sp!
8 ; CHECK: popeq
99 entry:
1010 br label %tailrecurse
1111
44 declare void @abort()
55
66 define fastcc void @t(%struct.SString* %word, i8 signext %c) {
7 ; CHECK: ldmiane sp!
7 ; CHECK: popne
88 entry:
99 %tmp1 = icmp eq %struct.SString* %word, null ; [#uses=1]
1010 br i1 %tmp1, label %cond_true, label %cond_false
44
55 define i32 @t1() {
66 ; CHECK: t1:
7 ; CHECK: ldmia
7 ; CHECK: pop
88 ; V4T: t1:
9 ; V4T: ldmia
9 ; V4T: pop
1010 %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; [#uses=1]
1111 %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; [#uses=1]
1212 %tmp4 = tail call i32 @f1( i32 %tmp, i32 %tmp3 ) ; [#uses=1]
1515
1616 define i32 @t2() {
1717 ; CHECK: t2:
18 ; CHECK: ldmia
18 ; CHECK: pop
1919 ; V4T: t2:
20 ; V4T: ldmia
20 ; V4T: pop
2121 %tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; [#uses=1]
2222 %tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; [#uses=1]
2323 %tmp5 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 4) ; [#uses=1]
2828 define i32 @t3() {
2929 ; CHECK: t3:
3030 ; CHECK: ldmib
31 ; CHECK: ldmia sp!
31 ; CHECK: pop
3232 ; V4T: t3:
3333 ; V4T: ldmib
3434 ; V4T: pop