llvm.org GIT mirror llvm / dcfe5f3
Keep track of phi join registers explicitly in LiveVariables. Previously, LiveIntervalAnalysis would infer phi joins by looking for multiply defined registers. That doesn't work if the phi join is implicitly defined in all but one of the predecessors. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96994 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 10 years ago
5 changed file(s) with 193 addition(s) and 52 deletion(s). Raw diff Collapse all Expand all
123123 ///
124124 std::vector VirtRegInfo;
125125
126 /// PHIJoins - list of virtual registers that are PHI joins. These registers
127 /// may have multiple definitions, and they require special handling when
128 /// building live intervals.
129 SparseBitVector<> PHIJoins;
130
126131 /// ReservedRegisters - This vector keeps track of which registers
127132 /// are reserved register which are not allocatable by the target machine.
128133 /// We can not track liveness for values that are in this set.
294299 void addNewBlock(MachineBasicBlock *BB,
295300 MachineBasicBlock *DomBB,
296301 MachineBasicBlock *SuccBB);
302
303 /// isPHIJoin - Return true if Reg is a phi join register.
304 bool isPHIJoin(unsigned Reg) { return PHIJoins.test(Reg); }
305
306 /// setPHIJoin - Mark Reg as a phi join register.
307 void setPHIJoin(unsigned Reg) { PHIJoins.set(Reg); }
297308 };
298309
299310 } // End llvm namespace
328328 DEBUG(dbgs() << " +" << NewLR);
329329 interval.addRange(NewLR);
330330
331 // Iterate over all of the blocks that the variable is completely
332 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
333 // live interval.
334 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
335 E = vi.AliveBlocks.end(); I != E; ++I) {
336 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
337 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
338 interval.addRange(LR);
339 DEBUG(dbgs() << " +" << LR);
331 bool PHIJoin = lv_->isPHIJoin(interval.reg);
332
333 if (PHIJoin) {
334 // A phi join register is killed at the end of the MBB and revived as a new
335 // valno in the killing blocks.
336 assert(vi.AliveBlocks.empty() && "Phi join can't pass through blocks");
337 DEBUG(dbgs() << " phi-join");
338 ValNo->addKill(indexes_->getTerminatorGap(mbb));
339 ValNo->setHasPHIKill(true);
340 } else {
341 // Iterate over all of the blocks that the variable is completely
342 // live in, adding [insrtIndex(begin), instrIndex(end)+4) to the
343 // live interval.
344 for (SparseBitVector<>::iterator I = vi.AliveBlocks.begin(),
345 E = vi.AliveBlocks.end(); I != E; ++I) {
346 MachineBasicBlock *aliveBlock = mf_->getBlockNumbered(*I);
347 LiveRange LR(getMBBStartIdx(aliveBlock), getMBBEndIdx(aliveBlock), ValNo);
348 interval.addRange(LR);
349 DEBUG(dbgs() << " +" << LR);
350 }
340351 }
341352
342353 // Finally, this virtual register is live from the start of any killing
343354 // block to the 'use' slot of the killing instruction.
344355 for (unsigned i = 0, e = vi.Kills.size(); i != e; ++i) {
345356 MachineInstr *Kill = vi.Kills[i];
346 SlotIndex killIdx =
347 getInstructionIndex(Kill).getDefIndex();
348 LiveRange LR(getMBBStartIdx(Kill->getParent()), killIdx, ValNo);
357 SlotIndex Start = getMBBStartIdx(Kill->getParent());
358 SlotIndex killIdx = getInstructionIndex(Kill).getDefIndex();
359
360 // Create interval with one of a NEW value number. Note that this value
361 // number isn't actually defined by an instruction, weird huh? :)
362 if (PHIJoin) {
363 ValNo = interval.getNextValue(SlotIndex(Start, true), 0, false,
364 VNInfoAllocator);
365 ValNo->setIsPHIDef(true);
366 }
367 LiveRange LR(Start, killIdx, ValNo);
349368 interval.addRange(LR);
350369 ValNo->addKill(killIdx);
351370 DEBUG(dbgs() << " +" << LR);
408427 interval.print(dbgs(), tri_);
409428 });
410429 } else {
411 // Otherwise, this must be because of phi elimination. If this is the
412 // first redefinition of the vreg that we have seen, go back and change
413 // the live range in the PHI block to be a different value number.
414 if (interval.containsOneValue()) {
415
416 VNInfo *VNI = interval.getValNumInfo(0);
417 // Phi elimination may have reused the register for multiple identical
418 // phi nodes. There will be a kill per phi. Remove the old ranges that
419 // we now know have an incorrect number.
420 for (unsigned ki=0, ke=vi.Kills.size(); ki != ke; ++ki) {
421 MachineInstr *Killer = vi.Kills[ki];
422 SlotIndex Start = getMBBStartIdx(Killer->getParent());
423 SlotIndex End = getInstructionIndex(Killer).getDefIndex();
424 DEBUG({
425 dbgs() << "\n\t\trenaming [" << Start << "," << End << "] in: ";
426 interval.print(dbgs(), tri_);
427 });
428 interval.removeRange(Start, End);
429
430 // Replace the interval with one of a NEW value number. Note that
431 // this value number isn't actually defined by an instruction, weird
432 // huh? :)
433 LiveRange LR(Start, End,
434 interval.getNextValue(SlotIndex(Start, true),
435 0, false, VNInfoAllocator));
436 LR.valno->setIsPHIDef(true);
437 interval.addRange(LR);
438 LR.valno->addKill(End);
439 }
440
441 MachineBasicBlock *killMBB = getMBBFromIndex(VNI->def);
442 VNI->addKill(indexes_->getTerminatorGap(killMBB));
443 VNI->setHasPHIKill(true);
444 DEBUG({
445 dbgs() << " RESULT: ";
446 interval.print(dbgs(), tri_);
447 });
448 }
449
430 assert(lv_->isPHIJoin(interval.reg) && "Multiply defined register");
450431 // In the case of PHI elimination, each variable definition is only
451432 // live until the end of the block. We've already taken care of the
452433 // rest of the live range.
434
453435 SlotIndex defIndex = MIIdx.getDefIndex();
454436 if (MO.isEarlyClobber())
455437 defIndex = MIIdx.getUseIndex();
467449 interval.addRange(LR);
468450 ValNo->addKill(indexes_->getTerminatorGap(mbb));
469451 ValNo->setHasPHIKill(true);
470 DEBUG(dbgs() << " +" << LR);
452 DEBUG(dbgs() << " phi-join +" << LR);
471453 }
472454 }
473455
509509 PHIVarInfo = new SmallVector[MF->getNumBlockIDs()];
510510 std::fill(PhysRegDef, PhysRegDef + NumRegs, (MachineInstr*)0);
511511 std::fill(PhysRegUse, PhysRegUse + NumRegs, (MachineInstr*)0);
512 PHIJoins.clear();
512513
513514 /// Get some space for a respectable number of registers.
514515 VirtRegInfo.resize(64);
222222
223223 // Increment use count of the newly created virtual register.
224224 VI.NumUses++;
225 LV->setPHIJoin(IncomingReg);
225226
226227 // When we are reusing the incoming register, it may already have been
227228 // killed in this block. The old kill will also have been inserted at
0 ; RUN: llc < %s
1 ; PR6363
2 ;
3 ; This test case creates a phi join register with a single definition. The other
4 ; predecessor blocks are implicit-def.
5 ;
6 ; If LiveIntervalAnalysis fails to recognize this as a phi join, the coalescer
7 ; will detect an infinity valno loop.
8 ;
9 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
10 target triple = "x86_64-unknown-linux-gnu"
11
12 define i32 @decode(i8* nocapture %input, i32 %offset, i8* nocapture %output) nounwind {
13 entry:
14 br i1 undef, label %meshBB86, label %meshBB102
15
16 bb: ; preds = %meshBB106, %meshBB102
17 br i1 false, label %bb9, label %meshBB90
18
19 bb.nph: ; preds = %meshBB90
20 br label %meshBB114
21
22 bb.nph.fragment: ; preds = %meshBB114
23 br label %meshBB118
24
25 bb1.fragment: ; preds = %meshBB118
26 br i1 false, label %bb2, label %bb3
27
28 bb2: ; preds = %bb1.fragment
29 br label %meshBB74
30
31 bb2.fragment15: ; preds = %meshBB74
32 br label %meshBB98
33
34 bb3: ; preds = %bb1.fragment
35 br i1 undef, label %meshBB, label %meshBB102
36
37 bb4: ; preds = %meshBB
38 br label %meshBB118
39
40 bb4.fragment: ; preds = %meshBB118
41 br label %meshBB82
42
43 bb5: ; preds = %meshBB102, %meshBB82
44 br i1 false, label %bb6, label %bb7
45
46 bb6: ; preds = %bb5
47 br label %bb7
48
49 bb7: ; preds = %meshBB98, %bb6, %bb5
50 br label %meshBB114
51
52 bb7.fragment: ; preds = %meshBB114
53 br i1 undef, label %meshBB74, label %bb9
54
55 bb9: ; preds = %bb7.fragment, %bb
56 br label %bb1.i23
57
58 bb1.i23: ; preds = %meshBB110, %bb9
59 br i1 undef, label %meshBB106, label %meshBB110
60
61 skip_to_newline.exit26: ; preds = %meshBB106
62 br label %meshBB86
63
64 skip_to_newline.exit26.fragment: ; preds = %meshBB86
65 br i1 false, label %meshBB90, label %meshBB106
66
67 bb11.fragment: ; preds = %meshBB90, %meshBB86
68 br label %meshBB122
69
70 bb1.i: ; preds = %meshBB122, %meshBB
71 %ooffset.2.lcssa.phi.SV.phi203 = phi i32 [ 0, %meshBB122 ], [ %ooffset.2.lcssa.phi.SV.phi233, %meshBB ] ; [#uses=1]
72 br label %meshBB98
73
74 bb1.i.fragment: ; preds = %meshBB98
75 br i1 undef, label %meshBB78, label %meshBB
76
77 skip_to_newline.exit: ; preds = %meshBB78
78 br i1 undef, label %bb12, label %meshBB110
79
80 bb12: ; preds = %skip_to_newline.exit
81 br label %meshBB94
82
83 bb12.fragment: ; preds = %meshBB94
84 br i1 false, label %bb13, label %meshBB78
85
86 bb13: ; preds = %bb12.fragment
87 br label %meshBB82
88
89 bb13.fragment: ; preds = %meshBB82
90 br i1 undef, label %meshBB94, label %meshBB122
91
92 bb14: ; preds = %meshBB94
93 ret i32 %ooffset.2.lcssa.phi.SV.phi250
94
95 bb15: ; preds = %meshBB122, %meshBB110, %meshBB78
96 unreachable
97
98 meshBB: ; preds = %bb1.i.fragment, %bb3
99 %ooffset.2.lcssa.phi.SV.phi233 = phi i32 [ undef, %bb3 ], [ %ooffset.2.lcssa.phi.SV.phi209, %bb1.i.fragment ] ; [#uses=1]
100 br i1 undef, label %bb1.i, label %bb4
101
102 meshBB74: ; preds = %bb7.fragment, %bb2
103 br i1 false, label %meshBB118, label %bb2.fragment15
104
105 meshBB78: ; preds = %bb12.fragment, %bb1.i.fragment
106 %ooffset.2.lcssa.phi.SV.phi239 = phi i32 [ %ooffset.2.lcssa.phi.SV.phi209, %bb1.i.fragment ], [ %ooffset.2.lcssa.phi.SV.phi250, %bb12.fragment ] ; [#uses=1]
107 br i1 false, label %bb15, label %skip_to_newline.exit
108
109 meshBB82: ; preds = %bb13, %bb4.fragment
110 br i1 false, label %bb5, label %bb13.fragment
111
112 meshBB86: ; preds = %skip_to_newline.exit26, %entry
113 br i1 undef, label %skip_to_newline.exit26.fragment, label %bb11.fragment
114
115 meshBB90: ; preds = %skip_to_newline.exit26.fragment, %bb
116 br i1 false, label %bb11.fragment, label %bb.nph
117
118 meshBB94: ; preds = %bb13.fragment, %bb12
119 %ooffset.2.lcssa.phi.SV.phi250 = phi i32 [ 0, %bb13.fragment ], [ %ooffset.2.lcssa.phi.SV.phi239, %bb12 ] ; [#uses=2]
120 br i1 false, label %bb12.fragment, label %bb14
121
122 meshBB98: ; preds = %bb1.i, %bb2.fragment15
123 %ooffset.2.lcssa.phi.SV.phi209 = phi i32 [ undef, %bb2.fragment15 ], [ %ooffset.2.lcssa.phi.SV.phi203, %bb1.i ] ; [#uses=2]
124 br i1 undef, label %bb1.i.fragment, label %bb7
125
126 meshBB102: ; preds = %bb3, %entry
127 br i1 undef, label %bb5, label %bb
128
129 meshBB106: ; preds = %skip_to_newline.exit26.fragment, %bb1.i23
130 br i1 undef, label %bb, label %skip_to_newline.exit26
131
132 meshBB110: ; preds = %skip_to_newline.exit, %bb1.i23
133 br i1 false, label %bb15, label %bb1.i23
134
135 meshBB114: ; preds = %bb7, %bb.nph
136 %meshStackVariable115.phi = phi i32 [ 19, %bb7 ], [ 8, %bb.nph ] ; [#uses=0]
137 br i1 undef, label %bb.nph.fragment, label %bb7.fragment
138
139 meshBB118: ; preds = %meshBB74, %bb4, %bb.nph.fragment
140 %meshCmp121 = icmp eq i32 undef, 10 ; [#uses=1]
141 br i1 %meshCmp121, label %bb4.fragment, label %bb1.fragment
142
143 meshBB122: ; preds = %bb13.fragment, %bb11.fragment
144 br i1 false, label %bb1.i, label %bb15
145 }