llvm.org GIT mirror llvm / dcca366
[PowerPC] Fix ADDE, SUBE do not know how to promote operator Summary: This patch is created to fix the Bugzilla bug 39815: https://bugs.llvm.org/show_bug.cgi?id=39815 This patch is to support promotion integer result for the instruction ADDE, SUBE. Reviewed By: hfinkel Differential Revision: https://reviews.llvm.org/D56119 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350161 91177308-0d34-0410-b5e6-96231b3b80d8 Kang Zhang 9 months ago
2 changed file(s) with 36 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
139139 case ISD::SMULO:
140140 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break;
141141
142 case ISD::ADDE:
143 case ISD::SUBE:
142144 case ISD::ADDCARRY:
143145 case ISD::SUBCARRY: Res = PromoteIntRes_ADDSUBCARRY(N, ResNo); break;
144146
864866 return Res;
865867 }
866868
869 // Handle promotion for the ADDE/SUBE/ADDCARRY/SUBCARRY nodes. Notice that
870 // the third operand of ADDE/SUBE nodes is carry flag, which differs from
871 // the ADDCARRY/SUBCARRY nodes in that the third operand is carry Boolean.
867872 SDValue DAGTypeLegalizer::PromoteIntRes_ADDSUBCARRY(SDNode *N, unsigned ResNo) {
868873 if (ResNo == 1)
869874 return PromoteIntRes_Overflow(N);
0 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu < %s \
1 ; RUN: -verify-machineinstrs | FileCheck %s
2
3 @b = common dso_local local_unnamed_addr global i64* null, align 8
4 @a = common dso_local local_unnamed_addr global i8 0, align 1
5
6 define void @testADDEPromoteResult() {
7 entry:
8 %0 = load i64*, i64** @b, align 8
9 %1 = load i64, i64* %0, align 8
10 %cmp = icmp ne i64* %0, null
11 %conv1 = zext i1 %cmp to i64
12 %add = add nsw i64 %1, %conv1
13 %2 = trunc i64 %add to i8
14 %conv2 = and i8 %2, 5
15 store i8 %conv2, i8* @a, align 1
16 ret void
17
18 ; CHECK-LABEL: @testADDEPromoteResult
19 ; CHECK: # %bb.0:
20 ; CHECK-DAG: addis [[REG1:[0-9]+]], [[REG2:[0-9]+]], [[VAR1:[a-z0-9A-Z_.]+]]@toc@ha
21 ; CHECK-DAG: ld [[REG3:[0-9]+]], [[VAR1]]@toc@l([[REG1]])
22 ; CHECK-DAG: lbz [[REG4:[0-9]+]], 0([[REG3]])
23 ; CHECK-DAG: addic [[REG5:[0-9]+]], [[REG3]], -1
24 ; CHECK-DAG: extsb [[REG6:[0-9]+]], [[REG4]]
25 ; CHECK-DAG: addze [[REG7:[0-9]+]], [[REG6]]
26 ; CHECK-DAG: addis [[REG8:[0-9]+]], [[REG2]], [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
27 ; CHECK-DAG: andi. [[REG9:[0-9]+]], [[REG7]], 5
28 ; CHECK-DAG: stb [[REG9]], [[VAR2]]@toc@l([[REG8]])
29 ; CHECK: blr
30 }