llvm.org GIT mirror llvm / dca684a
[X86] Pull out repeated Subtarget feature tests. NFCI. Avoids a scan-build "uninitialized value" warning in X86FastISel::X86SelectFPExtOrFPTrunc git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@360001 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 1 year, 5 months ago
1 changed file(s) with 11 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
24772477 assert((I->getOpcode() == Instruction::FPExt ||
24782478 I->getOpcode() == Instruction::FPTrunc) &&
24792479 "Instruction must be an FPExt or FPTrunc!");
2480 bool HasAVX = Subtarget->hasAVX();
24802481
24812482 unsigned OpReg = getRegForValue(I->getOperand(0));
24822483 if (OpReg == 0)
24832484 return false;
24842485
24852486 unsigned ImplicitDefReg;
2486 if (Subtarget->hasAVX()) {
2487 if (HasAVX) {
24872488 ImplicitDefReg = createResultReg(RC);
24882489 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
24892490 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
24952496 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc),
24962497 ResultReg);
24972498
2498 if (Subtarget->hasAVX())
2499 if (HasAVX)
24992500 MIB.addReg(ImplicitDefReg);
25002501
25012502 MIB.addReg(OpReg);
37493750
37503751 // Get opcode and regclass of the output for the given load instruction.
37513752 unsigned Opc = 0;
3753 bool HasAVX = Subtarget->hasAVX();
3754 bool HasAVX512 = Subtarget->hasAVX512();
37523755 const TargetRegisterClass *RC = nullptr;
37533756 switch (VT.SimpleTy) {
37543757 default: return 0;
37553758 case MVT::f32:
37563759 if (X86ScalarSSEf32) {
3757 Opc = Subtarget->hasAVX512()
3758 ? X86::VMOVSSZrm
3759 : Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm;
3760 RC = Subtarget->hasAVX512() ? &X86::FR32XRegClass : &X86::FR32RegClass;
3760 Opc = HasAVX512 ? X86::VMOVSSZrm : HasAVX ? X86::VMOVSSrm : X86::MOVSSrm;
3761 RC = HasAVX512 ? &X86::FR32XRegClass : &X86::FR32RegClass;
37613762 } else {
37623763 Opc = X86::LD_Fp32m;
3763 RC = &X86::RFP32RegClass;
3764 RC = &X86::RFP32RegClass;
37643765 }
37653766 break;
37663767 case MVT::f64:
37673768 if (X86ScalarSSEf64) {
3768 Opc = Subtarget->hasAVX512()
3769 ? X86::VMOVSDZrm
3770 : Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm;
3771 RC = Subtarget->hasAVX512() ? &X86::FR64XRegClass : &X86::FR64RegClass;
3769 Opc = HasAVX512 ? X86::VMOVSDZrm : HasAVX ? X86::VMOVSDrm : X86::MOVSDrm;
3770 RC = HasAVX512 ? &X86::FR64XRegClass : &X86::FR64RegClass;
37723771 } else {
37733772 Opc = X86::LD_Fp64m;
3774 RC = &X86::RFP64RegClass;
3773 RC = &X86::RFP64RegClass;
37753774 }
37763775 break;
37773776 case MVT::f80: