llvm.org GIT mirror llvm / dc77540
hasFP() is now a virtual method of MRegisterInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
15 changed file(s) with 47 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
366366 return 0;
367367 }
368368
369 /// hasFP - Return true if the specified function should have a dedicated frame
370 /// pointer register. For most targets this is true only if the function has
371 /// variable sized allocas or if frame pointer elimination is disabled.
372 virtual bool hasFP(const MachineFunction &MF) const = 0;
373
369374 /// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
370375 /// frame setup/destroy instructions if they exist (-1 otherwise). Some
371376 /// targets use pseudo instructions in order to abstract away the difference
276276 /// pointer register. This is true if the function has variable sized allocas
277277 /// or if frame pointer elimination is disabled.
278278 ///
279 static bool hasFP(const MachineFunction &MF) {
279 bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
280280 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
281281 }
282282
6767
6868 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
6969
70 bool hasFP(const MachineFunction &MF) const;
71
7072 void eliminateCallFramePseudoInstr(MachineFunction &MF,
7173 MachineBasicBlock &MBB,
7274 MachineBasicBlock::iterator I) const;
149149 GPRClass::iterator
150150 GPRClass::allocation_order_end(const MachineFunction &MF) const {
151151 const TargetMachine &TM = MF.getTarget();
152 const MRegisterInfo *RI = TM.getRegisterInfo();
152153 const ARMSubtarget &Subtarget = TM.getSubtarget();
153154 GPRClass::iterator I;
154155 if (Subtarget.isThumb())
166167 }
167168
168169 // Mac OS X requires FP not to be clobbered for backtracing purpose.
169 return (Subtarget.isTargetDarwin() || hasFP(MF)) ? I-1 : I;
170 return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
170171 }
171172 }];
172173 }
185185 // pointer register. This is true if the function has variable sized allocas or
186186 // if frame pointer elimination is disabled.
187187 //
188 static bool hasFP(const MachineFunction &MF) {
188 bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
189189 MachineFrameInfo *MFI = MF.getFrameInfo();
190190 return MFI->hasVarSizedObjects();
191191 }
4848
4949 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5050
51 bool hasFP(const MachineFunction &MF) const;
52
5153 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5254 MachineBasicBlock &MBB,
5355 MachineBasicBlock::iterator I) const;
113113 // pointer register. This is true if the function has variable sized allocas or
114114 // if frame pointer elimination is disabled.
115115 //
116 static bool hasFP(const MachineFunction &MF) {
116 bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
117117 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
118118 }
119119
4747
4848 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
4949
50 bool hasFP(const MachineFunction &MF) const;
51
5052 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5153 MachineBasicBlock &MBB,
5254 MachineBasicBlock::iterator MI) const;
409409 // hasFP - Return true if the specified function actually has a dedicated frame
410410 // pointer register. This is true if the function needs a frame pointer and has
411411 // a non-zero stack size.
412 static bool hasFP(const MachineFunction &MF) {
412 bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
413413 const MachineFrameInfo *MFI = MF.getFrameInfo();
414414 return MFI->getStackSize() && needsFP(MF);
415415 }
5757
5858 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5959
60 bool hasFP(const MachineFunction &MF) const;
61
6062 void eliminateCallFramePseudoInstr(MachineFunction &MF,
6163 MachineBasicBlock &MBB,
6264 MachineBasicBlock::iterator I) const;
121121 return CalleeSavedRegClasses;
122122 }
123123
124 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
125 return false;
126 }
124127
125128 void SparcRegisterInfo::
126129 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
5151
5252 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
5353
54 bool hasFP(const MachineFunction &MF) const;
55
5456 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5557 MachineBasicBlock &MBB,
5658 MachineBasicBlock::iterator I) const;
890890 // pointer register. This is true if the function has variable sized allocas or
891891 // if frame pointer elimination is disabled.
892892 //
893 static bool hasFP(const MachineFunction &MF) {
893 bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
894894 return (NoFramePointerElim ||
895895 MF.getFrameInfo()->hasVarSizedObjects() ||
896896 MF.getInfo()->getForceFramePointer());
997997
998998 // Get the number of bytes to allocate from the FrameInfo
999999 unsigned NumBytes = MFI->getStackSize();
1000 if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
1000 if (MFI->hasCalls() || MFI->hasVarSizedObjects()) {
10011001 // When we have no frame pointer, we reserve argument space for call sites
10021002 // in the function immediately on entry to the current function. This
10031003 // eliminates the need for add/sub ESP brackets around call sites.
7777 /// length of this list match the getCalleeSavedRegs() list.
7878 const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
7979
80 bool hasFP(const MachineFunction &MF) const;
81
8082 void eliminateCallFramePseudoInstr(MachineFunction &MF,
8183 MachineBasicBlock &MBB,
8284 MachineBasicBlock::iterator MI) const;
196196 GR8Class::iterator
197197 GR8Class::allocation_order_begin(const MachineFunction &MF) const {
198198 const TargetMachine &TM = MF.getTarget();
199 const MRegisterInfo *RI = TM.getRegisterInfo();
199200 const X86Subtarget &Subtarget = TM.getSubtarget();
200201 if (!Subtarget.is64Bit())
201202 return X86_GR8_AO_32;
202 else if (hasFP(MF))
203 else if (RI->hasFP(MF))
203204 return X86_GR8_AO_64_fp;
204205 else
205206 return X86_GR8_AO_64;
208209 GR8Class::iterator
209210 GR8Class::allocation_order_end(const MachineFunction &MF) const {
210211 const TargetMachine &TM = MF.getTarget();
212 const MRegisterInfo *RI = TM.getRegisterInfo();
211213 const X86Subtarget &Subtarget = TM.getSubtarget();
212214 if (!Subtarget.is64Bit())
213215 return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
214 else if (hasFP(MF))
216 else if (RI->hasFP(MF))
215217 return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
216218 else
217219 return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
247249 GR16Class::iterator
248250 GR16Class::allocation_order_begin(const MachineFunction &MF) const {
249251 const TargetMachine &TM = MF.getTarget();
252 const MRegisterInfo *RI = TM.getRegisterInfo();
250253 const X86Subtarget &Subtarget = TM.getSubtarget();
251254 if (Subtarget.is64Bit()) {
252 if (hasFP(MF))
255 if (RI->hasFP(MF))
253256 return X86_GR16_AO_64_fp;
254257 else
255258 return X86_GR16_AO_64;
256259 } else {
257 if (hasFP(MF))
260 if (RI->hasFP(MF))
258261 return X86_GR16_AO_32_fp;
259262 else
260263 return X86_GR16_AO_32;
264267 GR16Class::iterator
265268 GR16Class::allocation_order_end(const MachineFunction &MF) const {
266269 const TargetMachine &TM = MF.getTarget();
270 const MRegisterInfo *RI = TM.getRegisterInfo();
267271 const X86Subtarget &Subtarget = TM.getSubtarget();
268272 if (Subtarget.is64Bit()) {
269 if (hasFP(MF))
273 if (RI->hasFP(MF))
270274 return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
271275 else
272276 return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
273277 } else {
274 if (hasFP(MF))
278 if (RI->hasFP(MF))
275279 return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
276280 else
277281 return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
308312 GR32Class::iterator
309313 GR32Class::allocation_order_begin(const MachineFunction &MF) const {
310314 const TargetMachine &TM = MF.getTarget();
315 const MRegisterInfo *RI = TM.getRegisterInfo();
311316 const X86Subtarget &Subtarget = TM.getSubtarget();
312317 if (Subtarget.is64Bit()) {
313 if (hasFP(MF))
318 if (RI->hasFP(MF))
314319 return X86_GR32_AO_64_fp;
315320 else
316321 return X86_GR32_AO_64;
317322 } else {
318 if (hasFP(MF))
323 if (RI->hasFP(MF))
319324 return X86_GR32_AO_32_fp;
320325 else
321326 return X86_GR32_AO_32;
325330 GR32Class::iterator
326331 GR32Class::allocation_order_end(const MachineFunction &MF) const {
327332 const TargetMachine &TM = MF.getTarget();
333 const MRegisterInfo *RI = TM.getRegisterInfo();
328334 const X86Subtarget &Subtarget = TM.getSubtarget();
329335 if (Subtarget.is64Bit()) {
330 if (hasFP(MF))
336 if (RI->hasFP(MF))
331337 return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
332338 else
333339 return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
334340 } else {
335 if (hasFP(MF))
341 if (RI->hasFP(MF))
336342 return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
337343 else
338344 return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
351357 let MethodBodies = [{
352358 GR64Class::iterator
353359 GR64Class::allocation_order_end(const MachineFunction &MF) const {
354 if (hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
360 const TargetMachine &TM = MF.getTarget();
361 const MRegisterInfo *RI = TM.getRegisterInfo();
362 if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
355363 return end()-2; // If so, don't allocate RSP or RBP
356364 else
357365 return end()-1; // If not, just don't allocate RSP