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Generalize a pattern for PKHTB: an SRL of 16-31 bits will guarantee that the high halfword is zero. The shift need not be exactly 16 bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111196 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
4 changed file(s) with 27 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
22562256 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
22572257
22582258
2259 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2260 // will match the pattern below.
22592261 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
22602262 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
22612263 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
22672269
22682270 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
22692271 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2270 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, (i32 16))),
2271 (PKHTB GPR:$src1, GPR:$src2, 16)>;
2272 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2273 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
22722274 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
22732275 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
22742276 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
21052105 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$shamt)>,
21062106 Requires<[HasT2ExtractPack]>;
21072107
2108 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
2109 // will match the pattern below.
21082110 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
21092111 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
21102112 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
21202122
21212123 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
21222124 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
2123 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, (i32 16))),
2124 (t2PKHTB rGPR:$src1, rGPR:$src2, 16)>,
2125 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2126 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
21252127 Requires<[HasT2ExtractPack]>;
21262128 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
21272129 (and (srl rGPR:$src2, imm1_15:$shamt), 0xFFFF)),
3737 }
3838
3939 ; CHECK: test4
40 ; CHECK: pkhbt r0, r0, r1
40 ; CHECK: pkhbt r0, r0, r1, lsl #0
4141 define i32 @test4(i32 %X, i32 %Y) {
4242 %tmp1 = and i32 %X, 65535 ; [#uses=1]
4343 %tmp3 = and i32 %Y, -65536 ; [#uses=1]
8585 %tmp57 = or i32 %tmp4, %tmp1 ; [#uses=1]
8686 ret i32 %tmp57
8787 }
88
89 ; CHECK: test8
90 ; CHECK: pkhtb r0, r0, r1, asr #22
91 define i32 @test8(i32 %X, i32 %Y) {
92 %tmp1 = and i32 %X, -65536
93 %tmp3 = lshr i32 %Y, 22
94 %tmp57 = or i32 %tmp3, %tmp1
95 ret i32 %tmp57
96 }
8585 %tmp57 = or i32 %tmp4, %tmp1 ; [#uses=1]
8686 ret i32 %tmp57
8787 }
88
89 ; CHECK: test8
90 ; CHECK: pkhtb r0, r0, r1, asr #22
91 define i32 @test8(i32 %X, i32 %Y) {
92 %tmp1 = and i32 %X, -65536
93 %tmp3 = lshr i32 %Y, 22
94 %tmp57 = or i32 %tmp3, %tmp1
95 ret i32 %tmp57
96 }