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[llvm-exegesis][X86] Randomize CMOVcc/SETcc OPERAND_COND_CODE CondCodes Reviewers: courbet, gchatelet Reviewed By: gchatelet Subscribers: tschuett, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D60066 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@357898 91177308-0d34-0410-b5e6-96231b3b80d8 Roman Lebedev 1 year, 7 months ago
4 changed file(s) with 13 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
33 CHECK-NEXT: mode: latency
44 CHECK-NEXT: key:
55 CHECK-NEXT: instructions:
6 CHECK-NEXT: CMOV32rr
6 CHECK-NEXT: 'CMOV32rr {{.*}} i_0x{{[0-9a-f]}}'
77 CHECK-NEXT: config: ''
88 CHECK-LAST: ...
145145 return RandomGenerator;
146146 }
147147
148 static size_t randomIndex(size_t Size) {
149 assert(Size > 0);
150 std::uniform_int_distribution<> Distribution(0, Size - 1);
148 size_t randomIndex(size_t Max) {
149 std::uniform_int_distribution<> Distribution(0, Max);
151150 return Distribution(randomGenerator());
152151 }
153152
154153 template
155154 static auto randomElement(const C &Container) -> decltype(Container[0]) {
156 return Container[randomIndex(Container.size())];
155 assert(!Container.empty() &&
156 "Can't pick a random element from an empty container)");
157 return Container[randomIndex(Container.size() - 1)];
157158 }
158159
159160 static void setRegisterOperandValue(const RegisterOperandAssignment &ROV,
175176 size_t randomBit(const llvm::BitVector &Vector) {
176177 assert(Vector.any());
177178 auto Itr = Vector.set_bits_begin();
178 for (size_t I = randomIndex(Vector.count()); I != 0; --I)
179 for (size_t I = randomIndex(Vector.count() - 1); I != 0; --I)
179180 ++Itr;
180181 return *Itr;
181182 }
7676 // unit tests.
7777 std::mt19937 &randomGenerator();
7878
79 // Picks a random unsigned integer from 0 to Max (inclusive).
80 size_t randomIndex(size_t Max);
81
7982 // Picks a random bit among the bits set in Vector and returns its index.
8083 // Precondition: Vector must have at least one bit set.
8184 size_t randomBit(const llvm::BitVector &Vector);
77 #include "../Target.h"
88
99 #include "../Latency.h"
10 #include "../SnippetGenerator.h"
1011 #include "../Uops.h"
1112 #include "MCTargetDesc/X86BaseInfo.h"
1213 #include "MCTargetDesc/X86MCTargetDesc.h"
497498 const Operand &Op = Instr.getPrimaryOperand(Var);
498499 switch (Op.getExplicitOperandInfo().OperandType) {
499500 case llvm::X86::OperandType::OPERAND_COND_CODE:
500 // FIXME: explore all CC variants.
501 AssignedValue = llvm::MCOperand::createImm(1);
501 AssignedValue = llvm::MCOperand::createImm(
502 randomIndex(llvm::X86::CondCode::LAST_VALID_COND));
502503 break;
503504 default:
504505 break;