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Mask directive completed with CalleeSave info Comments for Mips directives added. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41526 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 13 years ago
2 changed file(s) with 114 addition(s) and 76 deletion(s). Raw diff Collapse all Expand all
3030 #include "llvm/Target/TargetMachine.h"
3131 #include "llvm/Support/Mangler.h"
3232 #include "llvm/ADT/Statistic.h"
33 #include "llvm/ADT/SetVector.h"
3334 #include "llvm/ADT/StringExtras.h"
3435 #include "llvm/Support/Debug.h"
3536 #include "llvm/Support/CommandLine.h"
6162 void printMemOperand(const MachineInstr *MI, int opNum,
6263 const char *Modifier = 0);
6364
65 unsigned int getSavedRegsBitmask(bool isFloat, MachineFunction &MF);
6466 void printHex32(unsigned int Value);
67
6568 void emitFunctionStart(MachineFunction &MF);
6669 void emitFunctionEnd();
6770 void emitFrameDirective(MachineFunction &MF);
6871 void emitMaskDirective(MachineFunction &MF);
69 void emitFMaskDirective();
72 void emitFMaskDirective(MachineFunction &MF);
7073 void emitSetDirective(SetDirectiveFlags Flag);
7174
7275 bool printInstruction(const MachineInstr *MI); // autogenerated.
8891 return new MipsAsmPrinter(o, tm, tm.getTargetAsmInfo());
8992 }
9093
91 /// This pattern will be emitted :
92 /// .frame reg1, size, reg2
93 /// It describes the stack frame.
94 /// reg1 - stack pointer
95 /// size - stack size allocated for the function
96 /// reg2 - return address register
94 //===----------------------------------------------------------------------===//
95 //
96 // Mips Asm Directives
97 //
98 // -- Frame directive "frame Stackpointer, Stacksize, RARegister"
99 // Describe the stack frame.
100 //
101 // -- Mask directives "(f)mask bitmask, offset"
102 // Tells the assembler which registers are saved and where.
103 // bitmask - contain a little endian bitset indicating which registers are
104 // saved on function prologue (e.g. with a 0x80000000 mask, the
105 // assembler knows the register 31 (RA) is saved at prologue.
106 // offset - the position before stack pointer subtraction indicating where
107 // the first saved register on prologue is located. (e.g. with a
108 //
109 // Consider the following function prologue:
110 //
111 // .frame $fp,48,$ra
112 // .mask 0xc0000000,-8
113 // addiu $sp, $sp, -48
114 // sw $ra, 40($sp)
115 // sw $fp, 36($sp)
116 //
117 // With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
118 // 30 (FP) are saved at prologue. As the save order on prologue is from
119 // left to right, RA is saved first. A -8 offset means that after the
120 // stack pointer subtration, the first register in the mask (RA) will be
121 // saved at address 48-8=40.
122 //
123 //===----------------------------------------------------------------------===//
124
125 /// Mask directive for GPR
126 void MipsAsmPrinter::
127 emitMaskDirective(MachineFunction &MF)
128 {
129 MipsFunctionInfo *MipsFI = MF.getInfo();
130
131 int StackSize = MF.getFrameInfo()->getStackSize();
132 int Offset = (!MipsFI->getTopSavedRegOffset()) ? 0 :
133 (-(StackSize-MipsFI->getTopSavedRegOffset()));
134
135 #ifndef NDEBUG
136 DOUT << "--> emitMaskDirective" << "\n";
137 DOUT << "StackSize : " << StackSize << "\n";
138 DOUT << "getTopSavedReg : " << MipsFI->getTopSavedRegOffset() << "\n";
139 DOUT << "Offset : " << Offset << "\n\n";
140 #endif
141
142 unsigned int Bitmask = getSavedRegsBitmask(false, MF);
143 O << "\t.mask\t";
144 printHex32(Bitmask);
145 O << "," << Offset << "\n";
146 }
147
148 /// TODO: Mask Directive for Float Point
149 void MipsAsmPrinter::
150 emitFMaskDirective(MachineFunction &MF)
151 {
152 unsigned int Bitmask = getSavedRegsBitmask(true, MF);
153
154 O << "\t.fmask\t";
155 printHex32(Bitmask);
156 O << ",0" << "\n";
157 }
158
159 /// Frame Directive
97160 void MipsAsmPrinter::
98161 emitFrameDirective(MachineFunction &MF)
99162 {
110173 << "\n";
111174 }
112175
113 /// This pattern will be emitted :
114 /// .mask bitmask, offset
115 /// Tells the assembler (and possibly linker) which registers are saved and where.
116 /// bitmask - mask of all GPRs (little endian)
117 /// offset - negative value. offset+stackSize should give where on the stack
118 /// the first GPR is saved.
119 /// TODO: consider calle saved GPR regs here, not hardcode register numbers.
120 void MipsAsmPrinter::
121 emitMaskDirective(MachineFunction &MF)
122 {
123 const MRegisterInfo &RI = *TM.getRegisterInfo();
124 MipsFunctionInfo *MipsFI = MF.getInfo();
125
126 bool hasFP = RI.hasFP(MF);
127 bool saveRA = MF.getFrameInfo()->hasCalls();
128
129 int offset;
130
131 if (!MipsFI->getTopSavedRegOffset())
132 offset = 0;
133 else
134 offset = -(MF.getFrameInfo()->getStackSize()
135 -MipsFI->getTopSavedRegOffset());
136
137 #ifndef NDEBUG
138 DOUT << "<--ASM PRINTER--emitMaskDirective-->" << "\n";
139 DOUT << "StackSize : " << MF.getFrameInfo()->getStackSize() << "\n";
140 DOUT << "getTopSavedRegOffset() : " << MipsFI->getTopSavedRegOffset() << "\n";
141 DOUT << "offset : " << offset << "\n\n";
142 #endif
143
144 unsigned int bitmask = 0;
145
146 if (hasFP)
147 bitmask |= (1 << 30);
148
149 if (saveRA)
150 bitmask |= (1 << 31);
151
152 O << "\t.mask\t";
153 printHex32(bitmask);
154 O << "," << offset << "\n";
155 }
156
157 /// This pattern will be emitted :
158 /// .fmask bitmask, offset
159 /// Tells the assembler (and possibly linker) which float registers are saved.
160 /// bitmask - mask of all Float Point registers (little endian)
161 /// offset - negative value. offset+stackSize should give where on the stack
162 /// the first Float Point register is saved.
163 /// TODO: implement this, dummy for now
164 void MipsAsmPrinter::
165 emitFMaskDirective()
166 {
167 O << "\t.fmask\t0x00000000,0" << "\n";
168 }
169
170 /// Print a 32 bit hex number filling with 0's on the left.
171 /// TODO: make this setfill and setw
172 void MipsAsmPrinter::
173 printHex32(unsigned int Value) {
174 O << "0x" << std::hex << Value << std::dec;
175 }
176
177176 /// Emit Set directives.
178177 void MipsAsmPrinter::
179 emitSetDirective(SetDirectiveFlags Flag) {
180
178 emitSetDirective(SetDirectiveFlags Flag)
179 {
181180 O << "\t.set\t";
182181 switch(Flag) {
183182 case REORDER: O << "reorder" << "\n"; break;
186185 case NOMACRO: O << "nomacro" << "\n"; break;
187186 default: break;
188187 }
188 }
189
190 // Create a bitmask with all callee saved registers for CPU
191 // or Float Point registers. For CPU registers consider RA,
192 // GP and FP for saving if necessary.
193 unsigned int MipsAsmPrinter::
194 getSavedRegsBitmask(bool isFloat, MachineFunction &MF)
195 {
196 const MRegisterInfo &RI = *TM.getRegisterInfo();
197
198 // Float Point Registers, TODO
199 if (isFloat)
200 return 0;
201
202 // CPU Registers
203 unsigned int Bitmask = 0;
204
205 MachineFrameInfo *MFI = MF.getFrameInfo();
206 const std::vector &CSI = MFI->getCalleeSavedInfo();
207 for (unsigned i = 0, e = CSI.size(); i != e; ++i)
208 Bitmask |= (1 << MipsRegisterInfo::getRegisterNumbering(CSI[i].getReg()));
209
210 if (RI.hasFP(MF))
211 Bitmask |= (1 << MipsRegisterInfo::getRegisterNumbering(RI.getFrameRegister(MF)));
212
213 if (MF.getFrameInfo()->hasCalls())
214 Bitmask |= (1 << MipsRegisterInfo::getRegisterNumbering(RI.getRARegister()));
215
216 return Bitmask;
217 }
218
219 // Print a 32 bit hex number with all numbers.
220 void MipsAsmPrinter::
221 printHex32(unsigned int Value)
222 {
223 O << "0x" << std::hex;
224 for (int i = 7; i >= 0; i--)
225 O << std::hex << ( (Value & (0xF << (i*4))) >> (i*4) );
226 O << std::dec;
189227 }
190228
191229 /// Emit the directives used by GAS on the start of functions
207245
208246 emitFrameDirective(MF);
209247 emitMaskDirective(MF);
210 emitFMaskDirective();
248 emitFMaskDirective(MF);
211249 emitSetDirective(NOREORDER);
212250 emitSetDirective(NOMACRO);
213251 O << "\n";
419457 default:
420458 assert(0 && "Unknown linkage type!");
421459 }
460
422461 O << "\t.align " << Align << "\n";
423462 O << "\t.type " << name << ",@object\n";
424463 O << "\t.size " << name << "," << Size << "\n";
2121
2222 namespace Mips {
2323
24 // All CC branch operations on Mips I are turned
25 // into BEQ and BNE CC branches instructions.
24 // Mips Condition Codes
2625 enum CondCode {
2726 COND_E,
2827 COND_GZ,