llvm.org GIT mirror llvm / dc05f3a
Add support for ARM modified-immediate assembly syntax. Certain ARM instructions accept 32-bit immediate operands encoded as a 8-bit integer value (0-255) and a 4-bit rotation (0-30, even). Current ARM assembly syntax support in LLVM allows the decoded (32-bit) immediate to be specified as a single immediate operand for such instructions: mov r0, #4278190080 The ARMARM defines an extended assembly syntax allowing the encoding to be made more explicit, as in: mov r0, #255, #8 ; (same 32-bit value as above) The behaviour of the two instructions can be different w.r.t flags, which is documented under "Modified immediate constants" in ARMARM. This patch enables support for this extended syntax at the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223113 91177308-0d34-0410-b5e6-96231b3b80d8 Asiri Rathnayake 5 years ago
11 changed file(s) with 690 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
586586 let DecoderMethod = "DecodeSOImmOperand";
587587 }
588588
589 // mod_imm: match a 32-bit immediate operand, which is encoded as a 12-bit
590 // immediate (See ARMARM - "Modified Immediate Constants"). Unlike so_imm,
591 // mod_imm keeps the immediate in its encoded form (within the MC layer).
592 def ModImmAsmOperand: AsmOperandClass {
593 let Name = "ModImm";
594 let ParserMethod = "parseModImm";
595 }
596 def mod_imm : Operand, ImmLeaf
597 return ARM_AM::getSOImmVal(Imm) != -1;
598 }]> {
599 let EncoderMethod = "getModImmOpValue";
600 let PrintMethod = "printModImmOperand";
601 let ParserMatchClass = ModImmAsmOperand;
602 }
603
604 // similar to so_imm_not, but keeps the immediate in its encoded form
605 def ModImmNotAsmOperand : AsmOperandClass { let Name = "ModImmNot"; }
606 def mod_imm_not : Operand, PatLeaf<(imm), [{
607 return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1;
608 }], imm_not_XFORM> {
609 let ParserMatchClass = ModImmNotAsmOperand;
610 }
611
612 // similar to so_imm_neg, but keeps the immediate in its encoded form
613 def ModImmNegAsmOperand : AsmOperandClass { let Name = "ModImmNeg"; }
614 def mod_imm_neg : Operand, PatLeaf<(imm), [{
615 unsigned Value = -(unsigned)N->getZExtValue();
616 return Value && ARM_AM::getSOImmVal(Value) != -1;
617 }], imm_neg_XFORM> {
618 let ParserMatchClass = ModImmNegAsmOperand;
619 }
620
589621 // Break so_imm's up into two pieces. This handles immediates with up to 16
590622 // bits set in them. This uses so_imm2part to match and so_imm2part_[12] to
591623 // get the first/second pieces.
12121244 // The register-immediate version is re-materializable. This is useful
12131245 // in particular for taking the address of a local.
12141246 let isReMaterializable = 1 in {
1215 def ri : AsI1so_imm:$imm), DPFrm,
1247 def ri : AsI1mod_imm:$imm), DPFrm,
12161248 iii, opc, "\t$Rd, $Rn, $imm",
1217 [(set GPR:$Rd, (opnode GPR:$Rn, so_imm:$imm))]>,
1249 [(set GPR:$Rd, (opnode GPR:$Rn, mod_imm:$imm))]>,
12181250 Sched<[WriteALU, ReadALU]> {
12191251 bits<4> Rd;
12201252 bits<4> Rn;
12851317 // The register-immediate version is re-materializable. This is useful
12861318 // in particular for taking the address of a local.
12871319 let isReMaterializable = 1 in {
1288 def ri : AsI1so_imm:$imm), DPFrm,
1320 def ri : AsI1mod_imm:$imm), DPFrm,
12891321 iii, opc, "\t$Rd, $Rn, $imm",
1290 [(set GPR:$Rd, (opnode so_imm:$imm, GPR:$Rn))]>,
1322 [(set GPR:$Rd, (opnode mod_imm:$imm, GPR:$Rn))]>,
12911323 Sched<[WriteALU, ReadALU]> {
12921324 bits<4> Rd;
12931325 bits<4> Rn;
13551387 multiclass AsI1_bin_s_irs
13561388 InstrItinClass iis, PatFrag opnode,
13571389 bit Commutable = 0> {
1358 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1390 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
13591391 4, iii,
1360 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm))]>,
1392 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm))]>,
13611393 Sched<[WriteALU, ReadALU]>;
13621394
13631395 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
13881420 multiclass AsI1_rbin_s_is
13891421 InstrItinClass iis, PatFrag opnode,
13901422 bit Commutable = 0> {
1391 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, so_imm:$imm, pred:$p),
1423 def ri : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, mod_imm:$imm, pred:$p),
13921424 4, iii,
1393 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn))]>,
1425 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn))]>,
13941426 Sched<[WriteALU, ReadALU]>;
13951427
13961428 def rsi : ARMPseudoInst<(outs GPR:$Rd),
14161448 multiclass AI1_cmp_irs opcod, string opc,
14171449 InstrItinClass iii, InstrItinClass iir, InstrItinClass iis,
14181450 PatFrag opnode, bit Commutable = 0> {
1419 def ri : AI1so_imm:$imm), DPFrm, iii,
1451 def ri : AI1mod_imm:$imm), DPFrm, iii,
14201452 opc, "\t$Rn, $imm",
1421 [(opnode GPR:$Rn, so_imm:$imm)]>,
1453 [(opnode GPR:$Rn, mod_imm:$imm)]>,
14221454 Sched<[WriteCMP, ReadALU]> {
14231455 bits<4> Rn;
14241456 bits<12> imm;
15461578 multiclass AI1_adde_sube_irs opcod, string opc, PatFrag opnode,
15471579 bit Commutable = 0> {
15481580 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1549 def ri : AsI1so_imm:$imm),
1581 def ri : AsI1mod_imm:$imm),
15501582 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1551 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, so_imm:$imm, CPSR))]>,
1583 [(set GPR:$Rd, CPSR, (opnode GPR:$Rn, mod_imm:$imm, CPSR))]>,
15521584 Requires<[IsARM]>,
15531585 Sched<[WriteALU, ReadALU]> {
15541586 bits<4> Rd;
16161648 let TwoOperandAliasConstraint = "$Rn = $Rd" in
16171649 multiclass AI1_rsc_irs opcod, string opc, PatFrag opnode> {
16181650 let hasPostISelHook = 1, Defs = [CPSR], Uses = [CPSR] in {
1619 def ri : AsI1so_imm:$imm),
1651 def ri : AsI1mod_imm:$imm),
16201652 DPFrm, IIC_iALUi, opc, "\t$Rd, $Rn, $imm",
1621 [(set GPR:$Rd, CPSR, (opnode so_imm:$imm, GPR:$Rn, CPSR))]>,
1653 [(set GPR:$Rd, CPSR, (opnode mod_imm:$imm, GPR:$Rn, CPSR))]>,
16221654 Requires<[IsARM]>,
16231655 Sched<[WriteALU, ReadALU]> {
16241656 bits<4> Rd;
32233255 }
32243256
32253257 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3226 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm, IIC_iMOVi,
3227 "mov", "\t$Rd, $imm", [(set GPR:$Rd, so_imm:$imm)]>, UnaryDP,
3258 def MOVi : AsI1<0b1101, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm, IIC_iMOVi,
3259 "mov", "\t$Rd, $imm", [(set GPR:$Rd, mod_imm:$imm)]>, UnaryDP,
32283260 Sched<[WriteALU]> {
32293261 bits<4> Rd;
32303262 bits<12> imm;
37313763 let Inst{3-0} = shift{3-0};
37323764 }
37333765 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
3734 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins so_imm:$imm), DPFrm,
3766 def MVNi : AsI1<0b1111, (outs GPR:$Rd), (ins mod_imm:$imm), DPFrm,
37353767 IIC_iMVNi, "mvn", "\t$Rd, $imm",
3736 [(set GPR:$Rd, so_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
3768 [(set GPR:$Rd, mod_imm_not:$imm)]>,UnaryDP, Sched<[WriteALU]> {
37373769 bits<4> Rd;
37383770 bits<12> imm;
37393771 let Inst{25} = 1;
42794311
42804312 // CMN register-integer
42814313 let isCompare = 1, Defs = [CPSR] in {
4282 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, so_imm:$imm), DPFrm, IIC_iCMPi,
4314 def CMNri : AI1<0b1011, (outs), (ins GPR:$Rn, mod_imm:$imm), DPFrm, IIC_iCMPi,
42834315 "cmn", "\t$Rn, $imm",
4284 [(ARMcmn GPR:$Rn, so_imm:$imm)]>,
4316 [(ARMcmn GPR:$Rn, mod_imm:$imm)]>,
42854317 Sched<[WriteCMP, ReadALU]> {
42864318 bits<4> Rn;
42874319 bits<12> imm;
51295161 let Inst{3-0} = Rn;
51305162 }
51315163
5132 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
5133 "msr", "\t$mask, $a", []> {
5164 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
5165 "msr", "\t$mask, $imm", []> {
51345166 bits<5> mask;
5135 bits<12> a;
5167 bits<12> imm;
51365168
51375169 let Inst{23} = 0;
51385170 let Inst{22} = mask{4}; // R bit
51395171 let Inst{21-20} = 0b10;
51405172 let Inst{19-16} = mask{3-0};
51415173 let Inst{15-12} = 0b1111;
5142 let Inst{11-0} = a;
5174 let Inst{11-0} = imm;
51435175 }
51445176
51455177 // However, the MSR (banked register) system instruction (ARMv7VE) *does* have a
55485580 // "mov Rd, so_imm_not" can be handled via "mvn" in assembly, just like
55495581 // for isel.
55505582 def : ARMInstAlias<"mov${s}${p} $Rd, $imm",
5551 (MVNi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5583 (MVNi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
55525584 def : ARMInstAlias<"mvn${s}${p} $Rd, $imm",
5553 (MOVi rGPR:$Rd, so_imm_not:$imm, pred:$p, cc_out:$s)>;
5585 (MOVi rGPR:$Rd, mod_imm_not:$imm, pred:$p, cc_out:$s)>;
55545586 // Same for AND <--> BIC
55555587 def : ARMInstAlias<"bic${s}${p} $Rd, $Rn, $imm",
5556 (ANDri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5588 (ANDri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
55575589 pred:$p, cc_out:$s)>;
55585590 def : ARMInstAlias<"bic${s}${p} $Rdn, $imm",
5559 (ANDri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5591 (ANDri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
55605592 pred:$p, cc_out:$s)>;
55615593 def : ARMInstAlias<"and${s}${p} $Rd, $Rn, $imm",
5562 (BICri rGPR:$Rd, rGPR:$Rn, so_imm_not:$imm,
5594 (BICri rGPR:$Rd, rGPR:$Rn, mod_imm_not:$imm,
55635595 pred:$p, cc_out:$s)>;
55645596 def : ARMInstAlias<"and${s}${p} $Rdn, $imm",
5565 (BICri rGPR:$Rdn, rGPR:$Rdn, so_imm_not:$imm,
5597 (BICri rGPR:$Rdn, rGPR:$Rdn, mod_imm_not:$imm,
55665598 pred:$p, cc_out:$s)>;
55675599
55685600 // Likewise, "add Rd, so_imm_neg" -> sub
55695601 def : ARMInstAlias<"add${s}${p} $Rd, $Rn, $imm",
5570 (SUBri GPR:$Rd, GPR:$Rn, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5602 (SUBri GPR:$Rd, GPR:$Rn, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
55715603 def : ARMInstAlias<"add${s}${p} $Rd, $imm",
5572 (SUBri GPR:$Rd, GPR:$Rd, so_imm_neg:$imm, pred:$p, cc_out:$s)>;
5604 (SUBri GPR:$Rd, GPR:$Rd, mod_imm_neg:$imm, pred:$p, cc_out:$s)>;
55735605 // Same for CMP <--> CMN via so_imm_neg
55745606 def : ARMInstAlias<"cmp${p} $Rd, $imm",
5575 (CMNri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5607 (CMNri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
55765608 def : ARMInstAlias<"cmn${p} $Rd, $imm",
5577 (CMPri rGPR:$Rd, so_imm_neg:$imm, pred:$p)>;
5609 (CMPri rGPR:$Rd, mod_imm_neg:$imm, pred:$p)>;
55785610
55795611 // The shifter forms of the MOV instruction are aliased to the ASR, LSL,
55805612 // LSR, ROR, and RRX instructions.
118118 ARMAsmPrinter &AP) {
119119 OutMI.setOpcode(MI->getOpcode());
120120
121 // In the MC layer, we keep modified immediates in their encoded form
122 bool EncodeImms = false;
123 switch (MI->getOpcode()) {
124 default: break;
125 case ARM::MOVi:
126 case ARM::MVNi:
127 case ARM::CMPri:
128 case ARM::CMNri:
129 case ARM::TSTri:
130 case ARM::TEQri:
131 case ARM::MSRi:
132 case ARM::ADCri:
133 case ARM::ADDri:
134 case ARM::ADDSri:
135 case ARM::SBCri:
136 case ARM::SUBri:
137 case ARM::SUBSri:
138 case ARM::ANDri:
139 case ARM::ORRri:
140 case ARM::EORri:
141 case ARM::BICri:
142 case ARM::RSBri:
143 case ARM::RSBSri:
144 case ARM::RSCri:
145 EncodeImms = true;
146 break;
147 }
148
121149 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
122150 const MachineOperand &MO = MI->getOperand(i);
123151
124152 MCOperand MCOp;
125 if (AP.lowerOperand(MO, MCOp))
153 if (AP.lowerOperand(MO, MCOp)) {
154 if (MCOp.isImm() && EncodeImms) {
155 int32_t Enc = ARM_AM::getSOImmVal(MCOp.getImm());
156 if (Enc != -1)
157 MCOp.setImm(Enc);
158 }
126159 OutMI.addOperand(MCOp);
160 }
127161 }
128162 }
304304 OperandMatchResultTy parseSetEndImm(OperandVector &);
305305 OperandMatchResultTy parseShifterImm(OperandVector &);
306306 OperandMatchResultTy parseRotImm(OperandVector &);
307 OperandMatchResultTy parseModImm(OperandVector &);
307308 OperandMatchResultTy parseBitfield(OperandVector &);
308309 OperandMatchResultTy parsePostIdxReg(OperandVector &);
309310 OperandMatchResultTy parseAM3Offset(OperandVector &);
399400 k_ShiftedImmediate,
400401 k_ShifterImmediate,
401402 k_RotateImmediate,
403 k_ModifiedImmediate,
402404 k_BitfieldDescriptor,
403405 k_Token
404406 } Kind;
508510
509511 struct RotImmOp {
510512 unsigned Imm;
513 };
514
515 struct ModImmOp {
516 unsigned Bits;
517 unsigned Rot;
511518 };
512519
513520 struct BitfieldOp {
536543 struct RegShiftedRegOp RegShiftedReg;
537544 struct RegShiftedImmOp RegShiftedImm;
538545 struct RotImmOp RotImm;
546 struct ModImmOp ModImm;
539547 struct BitfieldOp Bitfield;
540548 };
541549
611619 case k_RotateImmediate:
612620 RotImm = o.RotImm;
613621 break;
622 case k_ModifiedImmediate:
623 ModImm = o.ModImm;
624 break;
614625 case k_BitfieldDescriptor:
615626 Bitfield = o.Bitfield;
616627 break;
10901101 bool isRegShiftedReg() const { return Kind == k_ShiftedRegister; }
10911102 bool isRegShiftedImm() const { return Kind == k_ShiftedImmediate; }
10921103 bool isRotImm() const { return Kind == k_RotateImmediate; }
1104 bool isModImm() const { return Kind == k_ModifiedImmediate; }
1105 bool isModImmNot() const {
1106 if (!isImm()) return false;
1107 const MCConstantExpr *CE = dyn_cast(getImm());
1108 if (!CE) return false;
1109 int64_t Value = CE->getValue();
1110 return ARM_AM::getSOImmVal(~Value) != -1;
1111 }
1112 bool isModImmNeg() const {
1113 if (!isImm()) return false;
1114 const MCConstantExpr *CE = dyn_cast(getImm());
1115 if (!CE) return false;
1116 int64_t Value = CE->getValue();
1117 return ARM_AM::getSOImmVal(Value) == -1 &&
1118 ARM_AM::getSOImmVal(-Value) != -1;
1119 }
10931120 bool isBitfield() const { return Kind == k_BitfieldDescriptor; }
10941121 bool isPostIdxRegShifted() const { return Kind == k_PostIndexRegister; }
10951122 bool isPostIdxReg() const {
18251852 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
18261853 }
18271854
1855 void addModImmOperands(MCInst &Inst, unsigned N) const {
1856 assert(N == 1 && "Invalid number of operands!");
1857
1858 // Support for fixups (MCFixup)
1859 if (isImm())
1860 return addImmOperands(Inst, N);
1861
1862 if (Inst.getOpcode() == ARM::ADDri &&
1863 Inst.getOperand(1).getReg() == ARM::PC) {
1864 // Instructions of the form [ADD , pc, #imm] are manually aliased
1865 // in processInstruction() to use ADR. We must keep the immediate in
1866 // its unencoded form in order to not clash with this aliasing.
1867 Inst.addOperand(MCOperand::CreateImm(ARM_AM::rotr32(ModImm.Bits,
1868 ModImm.Rot)));
1869 } else {
1870 Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
1871 }
1872 }
1873
1874 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
1875 assert(N == 1 && "Invalid number of operands!");
1876 const MCConstantExpr *CE = dyn_cast(getImm());
1877 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1878 Inst.addOperand(MCOperand::CreateImm(Enc));
1879 }
1880
1881 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
1882 assert(N == 1 && "Invalid number of operands!");
1883 const MCConstantExpr *CE = dyn_cast(getImm());
1884 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1885 Inst.addOperand(MCOperand::CreateImm(Enc));
1886 }
1887
18281888 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
18291889 assert(N == 1 && "Invalid number of operands!");
18301890 // Munge the lsb/width into a bitfield mask.
26242684 SMLoc E) {
26252685 auto Op = make_unique(k_RotateImmediate);
26262686 Op->RotImm.Imm = Imm;
2687 Op->StartLoc = S;
2688 Op->EndLoc = E;
2689 return Op;
2690 }
2691
2692 static std::unique_ptr CreateModImm(unsigned Bits, unsigned Rot,
2693 SMLoc S, SMLoc E) {
2694 auto Op = make_unique(k_ModifiedImmediate);
2695 Op->ModImm.Bits = Bits;
2696 Op->ModImm.Rot = Rot;
26272697 Op->StartLoc = S;
26282698 Op->EndLoc = E;
26292699 return Op;
28812951 break;
28822952 case k_RotateImmediate:
28832953 OS << "";
2954 break;
2955 case k_ModifiedImmediate:
2956 OS << "
2957 << ModImm.Rot << ")>";
28842958 break;
28852959 case k_BitfieldDescriptor:
28862960 OS << "
43384412 }
43394413
43404414 ARMAsmParser::OperandMatchResultTy
4415 ARMAsmParser::parseModImm(OperandVector &Operands) {
4416 MCAsmParser &Parser = getParser();
4417 MCAsmLexer &Lexer = getLexer();
4418 int64_t Imm1, Imm2;
4419
4420 if ((Parser.getTok().isNot(AsmToken::Hash) &&
4421 Parser.getTok().isNot(AsmToken::Dollar) /* looking for an immediate */ )
4422 || Lexer.peekTok().is(AsmToken::Colon)
4423 || Lexer.peekTok().is(AsmToken::LParen) /* avoid complex operands */ )
4424 return MatchOperand_NoMatch;
4425
4426 SMLoc S = Parser.getTok().getLoc();
4427
4428 // Eat the hash (or dollar)
4429 Parser.Lex();
4430
4431 SMLoc Sx1, Ex1;
4432 Sx1 = Parser.getTok().getLoc();
4433 const MCExpr *Imm1Exp;
4434 if (getParser().parseExpression(Imm1Exp, Ex1)) {
4435 Error(Sx1, "malformed expression");
4436 return MatchOperand_ParseFail;
4437 }
4438
4439 const MCConstantExpr *CE = dyn_cast(Imm1Exp);
4440
4441 if (CE) {
4442 // immediate must fit within 32-bits
4443 Imm1 = CE->getValue();
4444 if (Imm1 < INT32_MIN || Imm1 > UINT32_MAX) {
4445 Error(Sx1, "immediate operand must be representable with 32 bits");
4446 return MatchOperand_ParseFail;
4447 }
4448
4449 int Enc = ARM_AM::getSOImmVal(Imm1);
4450 if (Enc != -1 && Parser.getTok().is(AsmToken::EndOfStatement)) {
4451 // We have a match!
4452 Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
4453 (Enc & 0xF00) >> 7,
4454 Sx1, Ex1));
4455 return MatchOperand_Success;
4456 }
4457 } else {
4458 Error(Sx1, "constant expression expected");
4459 return MatchOperand_ParseFail;
4460 }
4461
4462 if (Parser.getTok().isNot(AsmToken::Comma)) {
4463 // Consider [mov r0, #-10], which is aliased with mvn. We cannot fail
4464 // the parse here.
4465 Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
4466 return MatchOperand_Success;
4467 }
4468
4469 // From this point onward, we expect the input to be a (#bits, #rot) pair
4470 if (Imm1 & ~0xFF) {
4471 Error(Sx1, "immediate operand must a number in the range [0, 255]");
4472 return MatchOperand_ParseFail;
4473 }
4474
4475 if (Lexer.peekTok().isNot(AsmToken::Hash) &&
4476 Lexer.peekTok().isNot(AsmToken::Dollar)) {
4477 Error(Lexer.peekTok().getLoc(), "immediate operand expected");
4478 return MatchOperand_ParseFail;
4479 }
4480
4481 // Eat the comma
4482 Parser.Lex();
4483
4484 // Repeat for #rot
4485 SMLoc Sx2, Ex2;
4486 Sx2 = Parser.getTok().getLoc();
4487
4488 // Eat the hash (or dollar)
4489 Parser.Lex();
4490
4491 const MCExpr *Imm2Exp;
4492 if (getParser().parseExpression(Imm2Exp, Ex2)) {
4493 Error(Sx2, "malformed expression");
4494 return MatchOperand_ParseFail;
4495 }
4496
4497 CE = dyn_cast(Imm2Exp);
4498
4499 if (CE) {
4500 Imm2 = CE->getValue();
4501 if (!(Imm2 & ~0x1E)) {
4502 // We have a match!
4503 Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
4504 return MatchOperand_Success;
4505 }
4506 Error(Sx2, "immediate operand must an even number in the range [0, 30]");
4507 return MatchOperand_ParseFail;
4508 } else {
4509 Error(Sx2, "constant expression expected");
4510 return MatchOperand_ParseFail;
4511 }
4512 }
4513
4514 ARMAsmParser::OperandMatchResultTy
43414515 ARMAsmParser::parseBitfield(OperandVector &Operands) {
43424516 MCAsmParser &Parser = getParser();
43434517 SMLoc S = Parser.getTok().getLoc();
97869960 if (CE->getValue() == 0)
97879961 return Match_Success;
97889962 break;
9963 case MCK_ModImm:
97899964 case MCK_ARMSOImm:
97909965 if (Op.isImm()) {
97919966 const MCExpr *SOExpr = Op.getImm();
13171317 O << markup(">");
13181318 }
13191319
1320 void ARMInstPrinter::printModImmOperand(const MCInst *MI, unsigned OpNum,
1321 raw_ostream &O) {
1322 MCOperand Op = MI->getOperand(OpNum);
1323
1324 // Support for fixups (MCFixup)
1325 if (Op.isExpr())
1326 return printOperand(MI, OpNum, O);
1327
1328 unsigned Bits = Op.getImm() & 0xFF;
1329 unsigned Rot = (Op.getImm() & 0xF00) >> 7;
1330
1331 bool PrintUnsigned = false;
1332 switch (MI->getOpcode()){
1333 case ARM::MOVi:
1334 // Movs to PC should be treated unsigned
1335 PrintUnsigned = (MI->getOperand(OpNum - 1).getReg() == ARM::PC);
1336 break;
1337 case ARM::MSRi:
1338 // Movs to special registers should be treated unsigned
1339 PrintUnsigned = true;
1340 break;
1341 }
1342
1343 int32_t Rotated = ARM_AM::rotr32(Bits, Rot);
1344 if (ARM_AM::getSOImmVal(Rotated) == Op.getImm()) {
1345 // #rot has the least possible value
1346 O << "#" << markup("
1347 if (PrintUnsigned)
1348 O << static_cast(Rotated);
1349 else
1350 O << Rotated;
1351 O << markup(">");
1352 return;
1353 }
1354
1355 // Explicit #bits, #rot implied
1356 O << "#"
1357 << markup("
1358 << Bits
1359 << markup(">")
1360 << ", #"
1361 << markup("
1362 << Rot
1363 << markup(">");
1364 }
1365
13201366 void ARMInstPrinter::printFBits16(const MCInst *MI, unsigned OpNum,
13211367 raw_ostream &O) {
13221368 O << markup("
130130 void printNEONModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
131131 void printImmPlusOneOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
132132 void printRotImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
133 void printModImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
133134 void printGPRPairOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
134135
135136 void printPCLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
301301 // Encode immed_8.
302302 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
303303 return Binary;
304 }
305
306 unsigned getModImmOpValue(const MCInst &MI, unsigned Op,
307 SmallVectorImpl &Fixups,
308 const MCSubtargetInfo &ST) const {
309 const MCOperand &MO = MI.getOperand(Op);
310
311 // Support for fixups (MCFixup)
312 if (MO.isExpr()) {
313 const MCExpr *Expr = MO.getExpr();
314 // In instruction code this value always encoded as lowest 12 bits,
315 // so we don't have to perform any specific adjustments.
316 // Due to requirements of relocatable records we have to use FK_Data_4.
317 // See ARMELFObjectWriter::ExplicitRelSym and
318 // ARMELFObjectWriter::GetRelocTypeInner for more details.
319 MCFixupKind Kind = MCFixupKind(FK_Data_4);
320 Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
321 return 0;
322 }
323
324 // Immediate is already in its encoded format
325 return MO.getImm();
304326 }
305327
306328 /// getT2SOImmOpValue - Return an encoded 12-bit shifted-immediate value.
1515 @ ADC (immediate)
1616 @------------------------------------------------------------------------------
1717 adc r1, r2, #0xf
18 adc r7, r8, #42, #2
19 adc r7, r8, #-2147483638
20 adc r7, r8, #40, #2
1821 adc r1, r2, #0xf0
1922 adc r1, r2, #0xf00
2023 adc r1, r2, #0xf000
2427 adc r1, r2, #0xf0000000
2528 adc r1, r2, #0xf000000f
2629 adcs r1, r2, #0xf00
30 adcs r7, r8, #40, #2
2731 adcseq r1, r2, #0xf00
2832 adceq r1, r2, #0xf00
2933
3034 @ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
35 @ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2]
36 @ CHECK: adc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xa8,0xe2]
37 @ CHECK: adc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xa8,0xe2]
3138 @ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
3239 @ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2]
3340 @ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2]
3441 @ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2]
3542 @ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2]
3643 @ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2]
37 @ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2]
38 @ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2]
39
44 @ CHECK: adc r1, r2, #-268435456 @ encoding: [0x0f,0x12,0xa2,0xe2]
45 @ CHECK: adc r1, r2, #-268435441 @ encoding: [0xff,0x12,0xa2,0xe2]
4046 @ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2]
47 @ CHECK: adcs r7, r8, #40, #2 @ encoding: [0x28,0x71,0xb8,0xe2]
4148 @ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02]
4249 @ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02]
4350
161168 @ ADD
162169 @------------------------------------------------------------------------------
163170 add r4, r5, #0xf000
171 add r7, r8, #42, #2
172 add r7, r8, #-2147483638
173 add r7, r8, #40, #2
164174 add r4, r5, r6
165175 add r4, r5, r6, lsl #5
166176 add r4, r5, r6, lsr #5
195205 add r0, pc, #(Lback - .)
196206
197207 @ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
208 @ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2]
209 @ CHECK: add r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe2]
210 @ CHECK: add r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe2]
198211 @ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
199212 @ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]
200213 @ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
236249 @ CHECK: add r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x81,0xe0]
237250
238251 @------------------------------------------------------------------------------
252 @ ADDS
253 @------------------------------------------------------------------------------
254 adds r7, r8, #42, #2
255 adds r7, r8, #-2147483638
256 adds r7, r8, #40, #2
257
258 @ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2]
259 @ CHECK: adds r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x98,0xe2]
260 @ CHECK: adds r7, r8, #40, #2 @ encoding: [0x28,0x71,0x98,0xe2]
261
262 @------------------------------------------------------------------------------
239263 @ AND
240264 @------------------------------------------------------------------------------
241265 and r10, r1, #0xf
266 and r7, r8, #42, #2
267 and r7, r8, #-2147483638
268 and r7, r8, #40, #2
242269 and r10, r1, r6
243270 and r10, r1, r6, lsl #10
244271 and r10, r1, r6, lsr #10
267294 and r10, r1, rrx
268295
269296 @ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
297 @ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2]
298 @ CHECK: and r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x08,0xe2]
299 @ CHECK: and r7, r8, #40, #2 @ encoding: [0x28,0x71,0x08,0xe2]
270300 @ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
271301 @ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0]
272302 @ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
353383 @ BIC
354384 @------------------------------------------------------------------------------
355385 bic r10, r1, #0xf
386 bic r7, r8, #42, #2
387 bic r7, r8, #-2147483638
388 bic r7, r8, #40, #2
356389 bic r10, r1, r6
357390 bic r10, r1, r6, lsl #10
358391 bic r10, r1, r6, lsr #10
367400
368401 @ destination register is optional
369402 bic r1, #0xf
403 bic r7, #42, #2
404 bic r7, #-2147483638
405 bic r7, #40, #2
370406 bic r10, r1
371407 bic r10, r1, lsl #10
372408 bic r10, r1, lsr #10
380416 bic r10, r1, rrx
381417
382418 @ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3]
419 @ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3]
420 @ CHECK: bic r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe3]
421 @ CHECK: bic r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe3]
383422 @ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1]
384423 @ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1]
385424 @ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1]
394433
395434
396435 @ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3]
436 @ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3]
437 @ CHECK: bic r7, r7, #-2147483638 @ encoding: [0x2a,0x71,0xc7,0xe3]
438 @ CHECK: bic r7, r7, #40, #2 @ encoding: [0x28,0x71,0xc7,0xe3]
397439 @ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1]
398440 @ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1]
399441 @ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1]
510552 @ CMN
511553 @------------------------------------------------------------------------------
512554 cmn r1, #0xf
555 cmn r7, #42, #2
556 cmn r7, #-2147483638
557 cmn r7, #40, #2
513558 cmn r1, r6
514559 cmn r1, r6, lsl #10
515560 cmn r1, r6, lsr #10
523568 cmn r1, r6, rrx
524569
525570 @ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3]
571 @ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3]
572 @ CHECK: cmn r7, #-2147483638 @ encoding: [0x2a,0x01,0x77,0xe3]
573 @ CHECK: cmn r7, #40, #2 @ encoding: [0x28,0x01,0x77,0xe3]
526574 @ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1]
527575 @ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1]
528576 @ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1]
539587 @ CMP
540588 @------------------------------------------------------------------------------
541589 cmp r1, #0xf
590 cmp r7, #42, #2
591 cmp r7, #-2147483638
592 cmp r7, #40, #2
542593 cmp r1, r6
543594 cmp r1, r6, lsl #10
544595 cmp r1, r6, lsr #10
554605 cmp lr, #0
555606
556607 @ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
608 @ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3]
609 @ CHECK: cmp r7, #-2147483638 @ encoding: [0x2a,0x01,0x57,0xe3]
610 @ CHECK: cmp r7, #40, #2 @ encoding: [0x28,0x01,0x57,0xe3]
557611 @ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
558612 @ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1]
559613 @ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1]
739793 @ EOR
740794 @------------------------------------------------------------------------------
741795 eor r4, r5, #0xf000
796 eor r7, r8, #42, #2
797 eor r7, r8, #-2147483638
798 eor r7, r8, #40, #2
742799 eor r4, r5, r6
743800 eor r4, r5, r6, lsl #5
744801 eor r4, r5, r6, lsr #5
766823 eor r4, r5, rrx
767824
768825 @ CHECK: eor r4, r5, #61440 @ encoding: [0x0f,0x4a,0x25,0xe2]
826 @ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2]
827 @ CHECK: eor r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x28,0xe2]
828 @ CHECK: eor r7, r8, #40, #2 @ encoding: [0x28,0x71,0x28,0xe2]
769829 @ CHECK: eor r4, r5, r6 @ encoding: [0x06,0x40,0x25,0xe0]
770830 @ CHECK: eor r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x25,0xe0]
771831 @ CHECK: eor r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x25,0xe0]
10351095 mov r3, #7
10361096 mov r4, #0xff0
10371097 mov r5, #0xff0000
1098 mov r7, #0, #2
1099 mov r7, #42, #0
1100 mov r7, #40, #2
1101 mov r7, #42, #10
1102 mov r7, #42, #30
1103 mov r7, #42, #2
1104 mov r7, #-2147483638
1105 mov pc, #42, #2
10381106 mov r6, #0xffff
10391107 movw r9, #0xffff
10401108 movs r3, #7
10441112 @ CHECK: mov r3, #7 @ encoding: [0x07,0x30,0xa0,0xe3]
10451113 @ CHECK: mov r4, #4080 @ encoding: [0xff,0x4e,0xa0,0xe3]
10461114 @ CHECK: mov r5, #16711680 @ encoding: [0xff,0x58,0xa0,0xe3]
1115 @ CHECK: mov r7, #0, #2 @ encoding: [0x00,0x71,0xa0,0xe3]
1116 @ CHECK: mov r7, #42 @ encoding: [0x2a,0x70,0xa0,0xe3]
1117 @ CHECK: mov r7, #40, #2 @ encoding: [0x28,0x71,0xa0,0xe3]
1118 @ CHECK: mov r7, #176160768 @ encoding: [0x2a,0x75,0xa0,0xe3]
1119 @ CHECK: mov r7, #42, #30 @ encoding: [0x2a,0x7f,0xa0,0xe3]
1120 @ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3]
1121 @ CHECK: mov r7, #-2147483638 @ encoding: [0x2a,0x71,0xa0,0xe3]
1122 @ CHECK: mov pc, #2147483658 @ encoding: [0x2a,0xf1,0xa0,0xe3]
10471123 @ CHECK: movw r6, #65535 @ encoding: [0xff,0x6f,0x0f,0xe3]
10481124 @ CHECK: movw r9, #65535 @ encoding: [0xff,0x9f,0x0f,0xe3]
10491125 @ CHECK: movs r3, #7 @ encoding: [0x07,0x30,0xb0,0xe3]
11501226 msr spsr_fc, #5
11511227 msr SPSR_fsxc, #5
11521228 msr cpsr_fsxc, #5
1229 msr APSR_nzcvq, #42, #2
1230 msr apsr_nzcvqg, #2147483658
1231 msr SPSR_fsxc, #40, #2
11531232
11541233 @ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3]
11551234 @ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3]
11651244 @ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3]
11661245 @ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3]
11671246 @ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3]
1247 @ CHECK: msr APSR_nzcvq, #2147483658 @ encoding: [0x2a,0xf1,0x28,0xe3]
1248 @ CHECK: msr APSR_nzcvqg, #2147483658 @ encoding: [0x2a,0xf1,0x2c,0xe3]
1249 @ CHECK: msr SPSR_fsxc, #40, #2 @ encoding: [0x28,0xf1,0x6f,0xe3]
11681250
11691251 msr apsr, r0
11701252 msr apsr_g, r0
12171299 mvn r3, #7
12181300 mvn r4, #0xff0
12191301 mvn r5, #0xff0000
1302 mvn r7, #42, #2
1303 mvn r7, #-2147483638
1304 mvn r7, #40, #2
12201305 mvns r3, #7
12211306 mvneq r4, #0xff0
12221307 mvnseq r5, #0xff0000
12241309 @ CHECK: mvn r3, #7 @ encoding: [0x07,0x30,0xe0,0xe3]
12251310 @ CHECK: mvn r4, #4080 @ encoding: [0xff,0x4e,0xe0,0xe3]
12261311 @ CHECK: mvn r5, #16711680 @ encoding: [0xff,0x58,0xe0,0xe3]
1312 @ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3]
1313 @ CHECK: mvn r7, #-2147483638 @ encoding: [0x2a,0x71,0xe0,0xe3]
1314 @ CHECK: mvn r7, #40, #2 @ encoding: [0x28,0x71,0xe0,0xe3]
12271315 @ CHECK: mvns r3, #7 @ encoding: [0x07,0x30,0xf0,0xe3]
12281316 @ CHECK: mvneq r4, #4080 @ encoding: [0xff,0x4e,0xe0,0x03]
12291317 @ CHECK: mvnseq r5, #16711680 @ encoding: [0xff,0x58,0xf0,0x03]
12901378 @ ORR
12911379 @------------------------------------------------------------------------------
12921380 orr r4, r5, #0xf000
1381 orr r7, r8, #42, #2
1382 orr r7, r8, #-2147483638
1383 orr r7, r8, #40, #2
12931384 orr r4, r5, r6
12941385 orr r4, r5, r6, lsl #5
12951386 orr r4, r5, r6, lsr #5
13171408 orr r4, r5, rrx
13181409
13191410 @ CHECK: orr r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe3]
1411 @ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3]
1412 @ CHECK: orr r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x88,0xe3]
1413 @ CHECK: orr r7, r8, #40, #2 @ encoding: [0x28,0x71,0x88,0xe3]
13201414 @ CHECK: orr r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe1]
13211415 @ CHECK: orr r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe1]
13221416 @ CHECK: orr r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe1]
15751669 @ RSB
15761670 @------------------------------------------------------------------------------
15771671 rsb r4, r5, #0xf000
1672 rsb r7, r8, #42, #2
1673 rsb r7, r8, #-2147483638
1674 rsb r7, r8, #40, #2
15781675 rsb r4, r5, r6
15791676 rsb r4, r5, r6, lsl #5
15801677 rsblo r4, r5, r6, lsr #5
16021699 rsb r4, r5, rrx
16031700
16041701 @ CHECK: rsb r4, r5, #61440 @ encoding: [0x0f,0x4a,0x65,0xe2]
1702 @ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2]
1703 @ CHECK: rsb r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x68,0xe2]
1704 @ CHECK: rsb r7, r8, #40, #2 @ encoding: [0x28,0x71,0x68,0xe2]
16051705 @ CHECK: rsb r4, r5, r6 @ encoding: [0x06,0x40,0x65,0xe0]
16061706 @ CHECK: rsb r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x65,0xe0]
16071707 @ CHECK: rsblo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x65,0x30]
16281728 @ CHECK: rsb r4, r4, r5, rrx @ encoding: [0x65,0x40,0x64,0xe0]
16291729
16301730 @------------------------------------------------------------------------------
1731 @ RSBS
1732 @------------------------------------------------------------------------------
1733 rsbs r7, r8, #42, #2
1734 rsbs r7, r8, #-2147483638
1735 rsbs r7, r8, #40, #2
1736
1737 @ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2]
1738 @ CHECK: rsbs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x78,0xe2]
1739 @ CHECK: rsbs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x78,0xe2]
1740
1741 @------------------------------------------------------------------------------
16311742 @ RSC
16321743 @------------------------------------------------------------------------------
16331744 rsc r4, r5, #0xf000
1745 rsc r7, r8, #42, #2
1746 rsc r7, r8, #-2147483638
1747 rsc r7, r8, #40, #2
16341748 rsc r4, r5, r6
16351749 rsc r4, r5, r6, lsl #5
16361750 rsclo r4, r5, r6, lsr #5
16571771 rsc r6, r7, ror r9
16581772
16591773 @ CHECK: rsc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xe5,0xe2]
1774 @ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2]
1775 @ CHECK: rsc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xe8,0xe2]
1776 @ CHECK: rsc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xe8,0xe2]
16601777 @ CHECK: rsc r4, r5, r6 @ encoding: [0x06,0x40,0xe5,0xe0]
16611778 @ CHECK: rsc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xe5,0xe0]
16621779 @ CHECK: rsclo r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xe5,0x30]
17331850 @ SBC
17341851 @------------------------------------------------------------------------------
17351852 sbc r4, r5, #0xf000
1853 sbc r7, r8, #42, #2
1854 sbc r7, r8, #-2147483638
1855 sbc r7, r8, #40, #2
17361856 sbc r4, r5, r6
17371857 sbc r4, r5, r6, lsl #5
17381858 sbc r4, r5, r6, lsr #5
17581878 sbc r6, r7, ror r9
17591879
17601880 @ CHECK: sbc r4, r5, #61440 @ encoding: [0x0f,0x4a,0xc5,0xe2]
1881 @ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2]
1882 @ CHECK: sbc r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0xc8,0xe2]
1883 @ CHECK: sbc r7, r8, #40, #2 @ encoding: [0x28,0x71,0xc8,0xe2]
17611884 @ CHECK: sbc r4, r5, r6 @ encoding: [0x06,0x40,0xc5,0xe0]
17621885 @ CHECK: sbc r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0xc5,0xe0]
17631886 @ CHECK: sbc r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0xc5,0xe0]
23882511 @ SUB
23892512 @------------------------------------------------------------------------------
23902513 sub r4, r5, #0xf000
2514 sub r7, r8, #42, #2
2515 sub r7, r8, #-2147483638
2516 sub r7, r8, #40, #2
23912517 sub r4, r5, r6
23922518 sub r4, r5, r6, lsl #5
23932519 sub r4, r5, r6, lsr #5
24132539 sub r6, r7, ror r9
24142540
24152541 @ CHECK: sub r4, r5, #61440 @ encoding: [0x0f,0x4a,0x45,0xe2]
2542 @ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2]
2543 @ CHECK: sub r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x48,0xe2]
2544 @ CHECK: sub r7, r8, #40, #2 @ encoding: [0x28,0x71,0x48,0xe2]
24162545 @ CHECK: sub r4, r5, r6 @ encoding: [0x06,0x40,0x45,0xe0]
24172546 @ CHECK: sub r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x45,0xe0]
24182547 @ CHECK: sub r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x45,0xe0]
24442573 @ CHECK: sub r3, r1, r2, asr #32 @ encoding: [0x42,0x30,0x41,0xe0]
24452574
24462575 @------------------------------------------------------------------------------
2576 @ SUBS
2577 @------------------------------------------------------------------------------
2578 subs r7, r8, #42, #2
2579 subs r7, r8, #-2147483638
2580 subs r7, r8, #40, #2
2581
2582 @ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2]
2583 @ CHECK: subs r7, r8, #-2147483638 @ encoding: [0x2a,0x71,0x58,0xe2]
2584 @ CHECK: subs r7, r8, #40, #2 @ encoding: [0x28,0x71,0x58,0xe2]
2585
2586 @------------------------------------------------------------------------------
24472587 @ SVC
24482588 @------------------------------------------------------------------------------
24492589 svc #16
25652705 @ TEQ
25662706 @------------------------------------------------------------------------------
25672707 teq r5, #0xf000
2708 teq r7, #42, #2
2709 teq r7, #-2147483638
2710 teq r7, #40, #2
25682711 teq r4, r5
25692712 teq r4, r5, lsl #5
25702713 teq r4, r5, lsr #5
25772720 teq r6, r7, ror r9
25782721
25792722 @ CHECK: teq r5, #61440 @ encoding: [0x0f,0x0a,0x35,0xe3]
2723 @ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3]
2724 @ CHECK: teq r7, #-2147483638 @ encoding: [0x2a,0x01,0x37,0xe3]
2725 @ CHECK: teq r7, #40, #2 @ encoding: [0x28,0x01,0x37,0xe3]
25802726 @ CHECK: teq r4, r5 @ encoding: [0x05,0x00,0x34,0xe1]
25812727 @ CHECK: teq r4, r5, lsl #5 @ encoding: [0x85,0x02,0x34,0xe1]
25822728 @ CHECK: teq r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x34,0xe1]
25932739 @ TST
25942740 @------------------------------------------------------------------------------
25952741 tst r5, #0xf000
2742 tst r7, #42, #2
2743 tst r7, #-2147483638
2744 tst r7, #40, #2
25962745 tst r4, r5
25972746 tst r4, r5, lsl #5
25982747 tst r4, r5, lsr #5
26052754 tst r6, r7, ror r9
26062755
26072756 @ CHECK: tst r5, #61440 @ encoding: [0x0f,0x0a,0x15,0xe3]
2757 @ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3]
2758 @ CHECK: tst r7, #-2147483638 @ encoding: [0x2a,0x01,0x17,0xe3]
2759 @ CHECK: tst r7, #40, #2 @ encoding: [0x28,0x01,0x17,0xe3]
26082760 @ CHECK: tst r4, r5 @ encoding: [0x05,0x00,0x14,0xe1]
26092761 @ CHECK: tst r4, r5, lsl #5 @ encoding: [0x85,0x02,0x14,0xe1]
26102762 @ CHECK: tst r4, r5, lsr #5 @ encoding: [0xa5,0x02,0x14,0xe1]
620620 @ CHECK-ERRORS: error: destination register and base register can't be identical
621621 @ CHECK-ERRORS: ldrsb r0, [r0], r1
622622 @ CHECK-ERRORS: ^
623
624 @ Out of range modified immediate values
625 mov r5, #-256, #6
626 mov r6, #42, #7
627 mvn r5, #256, #6
628 mvn r6, #42, #298
629 cmp r5, #65535, #6
630 cmp r6, #42, #31
631 cmn r5, #-1, #6
632 cmn r6, #42, #32
633 msr APSR_nzcvq, #-128, #2
634 msr apsr_nzcvqg, #0, #1
635 adc r7, r8, #-256, #2
636 adc r7, r8, #128, #1
637 sbc r7, r8, #-256, #2
638 sbc r7, r8, #128, #1
639 add r7, r8, #-2149, #0
640 add r7, r8, #100, #1
641 sub r7, r8, #-2149, #0
642 sub r7, r8, #100, #1
643 and r7, r8, #-2149, #0
644 and r7, r8, #100, #1
645 orr r7, r8, #-2149, #0
646 orr r7, r8, #100, #1
647 eor r7, r8, #-2149, #0
648 eor r7, r8, #100, #1
649 bic r7, r8, #-2149, #0
650 bic r7, r8, #100, #1
651 rsb r7, r8, #-2149, #0
652 rsb r7, r8, #100, #1
653 adds r7, r8, #-2149, #0
654 adds r7, r8, #100, #1
655 subs r7, r8, #-2149, #0
656 subs r7, r8, #100, #1
657 rsbs r7, r8, #-2149, #0
658 rsbs r7, r8, #100, #1
659 rsc r7, r8, #-2149, #0
660 rsc r7, r8, #100, #1
661 TST r7, #-2149, #0
662 TST r7, #100, #1
663 TEQ r7, #-2149, #0
664 TEQ r7, #100, #1
665 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
666 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
667 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
668 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
669 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
670 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
671 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
672 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
673 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
674 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
675 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
676 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
677 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
678 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
679 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
680 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
681 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
682 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
683 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
684 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
685 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
686 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
687 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
688 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
689 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
690 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
691 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
692 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
693 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
694 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
695 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
696 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
697 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
698 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
699 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
700 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
701 @ CHECK-ERRORS: error: immediate operand must a number in the range [0, 255]
702 @ CHECK-ERRORS: error: immediate operand must an even number in the range [0, 30]
205205 @ CHECK-ERRORS: error: instruction requires: thumb2
206206 @ CHECK-ERRORS: add sp, sp, #512
207207 @ CHECK-ERRORS: ^
208 @ CHECK-ERRORS: error: instruction requires: arm-mode
208 @ CHECK-ERRORS: error: instruction requires: thumb2
209209 @ CHECK-ERRORS: add r2, sp, #1024
210210 @ CHECK-ERRORS: ^
211211
0 # RUN: llvm-mc --disassemble %s -triple=armv7-apple-darwin9 -mcpu=cortex-a9 | FileCheck %s
11
2 # CHECK: addpl r4, pc, #318767104
2 # CHECK: addpl r4, pc, #76, #10
33 0x4c 0x45 0x8f 0x52
44
55 # CHECK: b #0
99 # CHECK: adc r1, r2, #983040
1010 # CHECK: adc r1, r2, #15728640
1111 # CHECK: adc r1, r2, #251658240
12 # CHECK: adc r1, r2, #4026531840
13 # CHECK: adc r1, r2, #4026531855
12 # CHECK: adc r1, r2, #-268435456
13 # CHECK: adc r1, r2, #-268435441
14 # CHECK: adc r7, r8, #-2147483638
15 # CHECK: adc r7, r8, #40, #2
1416 # CHECK: adcs r1, r2, #3840
17 # CHECK: adcs r7, r8, #40, #2
1518 # CHECK: adcseq r1, r2, #3840
1619 # CHECK: adceq r1, r2, #3840
1720
2427 0x0f 0x14 0xa2 0xe2
2528 0x0f 0x12 0xa2 0xe2
2629 0xff 0x12 0xa2 0xe2
30 0x2a 0x71 0xa8 0xe2
31 0x28 0x71 0xa8 0xe2
2732
2833 0x0f 0x1c 0xb2 0xe2
34 0x28 0x71 0xb8 0xe2
2935 0x0f 0x1c 0xb2 0x02
3036 0x0f 0x1c 0xa2 0x02
3137
111117 # ADD
112118 #------------------------------------------------------------------------------
113119 # CHECK: add r4, r5, #61440
120 # CHECK: add r7, r8, #-2147483638
121 # CHECK: add r7, r8, #40, #2
114122 # CHECK: add r4, r5, r6
115123 # CHECK: add r4, r5, r6, lsl #5
116124 # CHECK: add r4, r5, r6, lsr #5
137145 # CHECK: add r4, r4, r5, rrx
138146
139147 0x0f 0x4a 0x85 0xe2
148 0x2a 0x71 0x88 0xe2
149 0x28 0x71 0x88 0xe2
140150 0x06 0x40 0x85 0xe0
141151 0x86 0x42 0x85 0xe0
142152 0xa6 0x42 0x85 0xe0
164174 0x65 0x40 0x84 0xe0
165175
166176 #------------------------------------------------------------------------------
177 # ADDS
178 #------------------------------------------------------------------------------
179 # CHECK: adds r7, r8, #-2147483638
180 # CHECK: adds r7, r8, #40, #2
181
182 0x2a 0x71 0x98 0xe2
183 0x28 0x71 0x98 0xe2
184
185 #------------------------------------------------------------------------------
167186 # ADR
168187 #------------------------------------------------------------------------------
169188 # CHECK: add r2, pc, #3
182201 # AND
183202 #------------------------------------------------------------------------------
184203 # CHECK: and r10, r1, #15
204 # CHECK: and r7, r8, #-2147483638
205 # CHECK: and r7, r8, #40, #2
185206 # CHECK: and r10, r1, r6
186207 # CHECK: and r10, r1, r6, lsl #10
187208 # CHECK: and r10, r1, r6, lsr #10
208229 # CHECK: and r10, r10, r1, rrx
209230
210231 0x0f 0xa0 0x01 0xe2
232 0x2a 0x71 0x08 0xe2
233 0x28 0x71 0x08 0xe2
211234 0x06 0xa0 0x01 0xe0
212235 0x06 0xa5 0x01 0xe0
213236 0x26 0xa5 0x01 0xe0
261284 # BIC
262285 #------------------------------------------------------------------------------
263286 # CHECK: bic r10, r1, #15
287 # CHECK: bic r7, r8, #-2147483638
288 # CHECK: bic r7, r8, #40, #2
264289 # CHECK: bic r10, r1, r6
265290 # CHECK: bic r10, r1, r6, lsl #10
266291 # CHECK: bic r10, r1, r6, lsr #10
287312 # CHECK: bic r10, r10, r1, rrx
288313
289314 0x0f 0xa0 0xc1 0xe3
315 0x2a 0x71 0xc8 0xe3
316 0x28 0x71 0xc8 0xe3
290317 0x06 0xa0 0xc1 0xe1
291318 0x06 0xa5 0xc1 0xe1
292319 0x26 0xa5 0xc1 0xe1
392419 # CMN
393420 #------------------------------------------------------------------------------
394421 # CHECK: cmn r1, #15
422 # CHECK: cmn r7, #40, #2
423 # CHECK: cmn r7, #-2147483638
395424 # CHECK: cmn r1, r6
396425 # CHECK: cmn r1, r6, lsl #10
397426 # CHECK: cmn r1, r6, lsr #10
405434 # CHECK: cmn r1, r6, rrx
406435
407436 0x0f 0x00 0x71 0xe3
437 0x28 0x01 0x77 0xe3
438 0x2a 0x01 0x77 0xe3
408439 0x06 0x00 0x71 0xe1
409440 0x06 0x05 0x71 0xe1
410441 0x26 0x05 0x71 0xe1
421452 # CMP
422453 #------------------------------------------------------------------------------
423454 # CHECK: cmp r1, #15
455 # CHECK: cmp r7, #40, #2
456 # CHECK: cmp r7, #-2147483638
424457 # CHECK: cmp r1, r6
425458 # CHECK: cmp r1, r6, lsl #10
426459 # CHECK: cmp r1, r6, lsr #10
434467 # CHECK: cmp r1, r6, rrx
435468
436469 0x0f 0x00 0x51 0xe3
470 0x28 0x01 0x57 0xe3
471 0x2a 0x01 0x57 0xe3
437472 0x06 0x00 0x51 0xe1
438473 0x06 0x05 0x51 0xe1
439474 0x26 0x05 0x51 0xe1
555590 # EOR
556591 #------------------------------------------------------------------------------
557592 # CHECK: eor r4, r5, #61440
593 # CHECK: eor r7, r8, #-2147483638
594 # CHECK: eor r7, r8, #40, #2
558595 # CHECK: eor r4, r5, r6
559596 # CHECK: eor r4, r5, r6, lsl #5
560597 # CHECK: eor r4, r5, r6, lsr #5
581618 # CHECK: eor r4, r4, r5, rrx
582619
583620 0x0f 0x4a 0x25 0xe2
621 0x2a 0x71 0x28 0xe2
622 0x28 0x71 0x28 0xe2
584623 0x06 0x40 0x25 0xe0
585624 0x86 0x42 0x25 0xe0
586625 0xa6 0x42 0x25 0xe0
713752 # CHECK: mov r4, #4080
714753 # CHECK: mov r5, #16711680
715754 # CHECK: mov sp, #35
755 # CHECK: mov r9, #240, #30
756 # CHECK: mov r7, #-2147483638
757 # CHECK: mov pc, #2147483658
716758 # CHECK: movw r6, #65535
717759 # CHECK: movw r9, #65535
718760 # CHECK: movw sp, #1193
719761 # CHECK: movs r3, #7
762 # CHECK: movs r11, #99
763 # CHECK: movs r11, #240, #30
720764 # CHECK: moveq r4, #4080
721765 # CHECK: movseq r5, #16711680
722766
724768 0xff 0x4e 0xa0 0xe3
725769 0xff 0x58 0xa0 0xe3
726770 0x23 0xd0 0xa0 0xe3
771 0xf0 0x9f 0xa0 0xe3
772 0x2a 0x71 0xa0 0xe3
773 0x2a 0xf1 0xa0 0xe3
727774 0xff 0x6f 0x0f 0xe3
728775 0xff 0x9f 0x0f 0xe3
729776 0xa9 0xd4 0x00 0xe3
730777 0x07 0x30 0xb0 0xe3
778 0x63 0xb0 0xb0 0xe3
779 0xf0 0xbf 0xb0 0xe3
731780 0xff 0x4e 0xa0 0x03
732781 0xff 0x58 0xb0 0x03
733782
809858 # CHECK: msr SPSR_fc, #5
810859 # CHECK: msr SPSR_fsxc, #5
811860 # CHECK: msr CPSR_fsxc, #5
861 # CHECK: msr APSR_nzcvq, #2147483658
862 # CHECK: msr SPSR_fsxc, #40, #2
812863
813864 0x05 0xf0 0x29 0xe3
814865 0x05 0xf0 0x24 0xe3
824875 0x05 0xf0 0x69 0xe3
825876 0x05 0xf0 0x6f 0xe3
826877 0x05 0xf0 0x2f 0xe3
878 0x2a 0xf1 0x28 0xe3
879 0x28 0xf1 0x6f 0xe3
827880
828881 # CHECK: msr CPSR_fc, r0
829882 # CHECK: msr APSR_g, r0
876929 # CHECK: mvn r3, #7
877930 # CHECK: mvn r4, #4080
878931 # CHECK: mvn r5, #16711680
932 # CHECK: mvn r7, #40, #2
933 # CHECK: mvn r7, #-2147483638
879934 # CHECK: mvns r3, #7
935 # CHECK: mvns r11, #240, #30
936 # CHECK: mvns r11, #-2147483638
880937 # CHECK: mvneq r4, #4080
881938 # CHECK: mvnseq r5, #16711680
882939
883940 0x07 0x30 0xe0 0xe3
884941 0xff 0x4e 0xe0 0xe3
885942 0xff 0x58 0xe0 0xe3
943 0x28 0x71 0xe0 0xe3
944 0x2a 0x71 0xe0 0xe3
886945 0x07 0x30 0xf0 0xe3
946 0xf0 0xbf 0xf0 0xe3
947 0x2a 0xb1 0xf0 0xe3
887948 0xff 0x4e 0xe0 0x03
888949 0xff 0x58 0xf0 0x03
889950
9391000 # ORR
9401001 #------------------------------------------------------------------------------
9411002 # CHECK: orr r4, r5, #61440
1003 # CHECK: orr r7, r8, #-2147483638
1004 # CHECK: orr r7, r8, #40, #2
9421005 # CHECK: orr r4, r5, r6
9431006 # CHECK: orr r4, r5, r6, lsl #5
9441007 # CHECK: orr r4, r5, r6, lsr #5
9651028 # CHECK: orr r4, r4, r5, rrx
9661029
9671030 0x0f 0x4a 0x85 0xe3
1031 0x2a 0x71 0x88 0xe3
1032 0x28 0x71 0x88 0xe3
9681033 0x06 0x40 0x85 0xe1
9691034 0x86 0x42 0x85 0xe1
9701035 0xa6 0x42 0x85 0xe1
12031268 # RSB
12041269 #------------------------------------------------------------------------------
12051270 # CHECK: rsb r4, r5, #61440
1271 # CHECK: rsb r7, r8, #-2147483638
1272 # CHECK: rsb r7, r8, #40, #2
12061273 # CHECK: rsb r4, r5, r6
12071274 # CHECK: rsb r4, r5, r6, lsl #5
12081275 # CHECK: rsblo r4, r5, r6, lsr #5
12291296 # CHECK: rsb r4, r4, r5, rrx
12301297
12311298 0x0f 0x4a 0x65 0xe2
1299 0x2a 0x71 0x68 0xe2
1300 0x28 0x71 0x68 0xe2
12321301 0x06 0x40 0x65 0xe0
12331302 0x86 0x42 0x65 0xe0
12341303 0xa6 0x42 0x65 0x30
12551324 0x65 0x40 0x64 0xe0
12561325
12571326 #------------------------------------------------------------------------------
1327 # RSBS
1328 #------------------------------------------------------------------------------
1329 # CHECK: rsbs r7, r8, #-2147483638
1330 # CHECK: rsbs r7, r8, #40, #2
1331
1332 0x2a 0x71 0x78 0xe2
1333 0x28 0x71 0x78 0xe2
1334
1335 #------------------------------------------------------------------------------
12581336 # RSC
12591337 #------------------------------------------------------------------------------
12601338 # CHECK: rsc r4, r5, #61440
1339 # CHECK: rsc r7, r8, #-2147483638
1340 # CHECK: rsc r7, r8, #40, #2
12611341 # CHECK: rsc r4, r5, r6
12621342 # CHECK: rsc r4, r5, r6, lsl #5
12631343 # CHECK: rsclo r4, r5, r6, lsr #5
12821362 # CHECK: rsc r6, r6, r7, ror r9
12831363
12841364 0x0f 0x4a 0xe5 0xe2
1365 0x2a 0x71 0xe8 0xe2
1366 0x28 0x71 0xe8 0xe2
12851367 0x06 0x40 0xe5 0xe0
12861368 0x86 0x42 0xe5 0xe0
12871369 0xa6 0x42 0xe5 0x30
13561438 # SBC
13571439 #------------------------------------------------------------------------------
13581440 # CHECK: sbc r4, r5, #61440
1441 # CHECK: sbc r7, r8, #-2147483638
1442 # CHECK: sbc r7, r8, #40, #2
13591443 # CHECK: sbc r4, r5, r6
13601444 # CHECK: sbc r4, r5, r6, lsl #5
13611445 # CHECK: sbc r4, r5, r6, lsr #5
13801464 # CHECK: sbc r6, r6, r7, ror r9
13811465
13821466 0x0f 0x4a 0xc5 0xe2
1467 0x2a 0x71 0xc8 0xe2
1468 0x28 0x71 0xc8 0xe2
13831469 0x06 0x40 0xc5 0xe0
13841470 0x86 0x42 0xc5 0xe0
13851471 0xa6 0x42 0xc5 0xe0
18671953 # SUB
18681954 #------------------------------------------------------------------------------
18691955 # CHECK: sub r4, r5, #61440
1956 # CHECK: sub r7, r8, #-2147483638
1957 # CHECK: sub r7, r8, #40, #2
18701958 # CHECK: sub r4, r5, r6
18711959 # CHECK: sub r4, r5, r6, lsl #5
18721960 # CHECK: sub r4, r5, r6, lsr #5
18911979 # CHECK: sub r6, r6, r7, ror r9
18921980
18931981 0x0f 0x4a 0x45 0xe2
1982 0x2a 0x71 0x48 0xe2
1983 0x28 0x71 0x48 0xe2
18941984 0x06 0x40 0x45 0xe0
18951985 0x86 0x42 0x45 0xe0
18961986 0xa6 0x42 0x45 0xe0
19152005 0x57 0x69 0x46 0xe0
19162006 0x77 0x69 0x46 0xe0
19172007
2008 #------------------------------------------------------------------------------
2009 # SUBS
2010 #------------------------------------------------------------------------------
2011 # CHECK: subs r7, r8, #-2147483638
2012 # CHECK: subs r7, r8, #40, #2
2013
2014 0x2a 0x71 0x58 0xe2
2015 0x28 0x71 0x58 0xe2
19182016
19192017 #------------------------------------------------------------------------------
19202018 # SVC
20432141 # TEQ
20442142 #------------------------------------------------------------------------------
20452143 # CHECK: teq r5, #61440
2144 # CHECK: teq r7, #-2147483638
2145 # CHECK: teq r7, #40, #2
20462146 # CHECK: teq r4, r5
20472147 # CHECK: teq r4, r5, lsl #5
20482148 # CHECK: teq r4, r5, lsr #5
20552155 # CHECK: teq r6, r7, ror r9
20562156
20572157 0x0f 0x0a 0x35 0xe3
2158 0x2a 0x01 0x37 0xe3
2159 0x28 0x01 0x37 0xe3
20582160 0x05 0x00 0x34 0xe1
20592161 0x85 0x02 0x34 0xe1
20602162 0xa5 0x02 0x34 0xe1
20712173 # TST
20722174 #------------------------------------------------------------------------------
20732175 # CHECK: tst r5, #61440
2176 # CHECK: tst r7, #-2147483638
2177 # CHECK: tst r7, #40, #2
20742178 # CHECK: tst r4, r5
20752179 # CHECK: tst r4, r5, lsl #5
20762180 # CHECK: tst r4, r5, lsr #5
20832187 # CHECK: tst r6, r7, ror r9
20842188
20852189 0x0f 0x0a 0x15 0xe3
2190 0x2a 0x01 0x17 0xe3
2191 0x28 0x01 0x17 0xe3
20862192 0x05 0x00 0x14 0xe1
20872193 0x85 0x02 0x14 0xe1
20882194 0xa5 0x02 0x14 0xe1