llvm.org GIT mirror llvm / dbe6d43
TableGen subtarget emitter cleanup. Consistently evaluate Aliases and Sequences recursively. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165604 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 8 years ago
2 changed file(s) with 47 addition(s) and 37 deletion(s). Raw diff Collapse all Expand all
14481448 }
14491449 }
14501450
1451 void CodeGenSchedModels::collectRWResources(unsigned RWIdx, bool IsRead,
1452 const IdxVec &ProcIndices) {
1453 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead);
1454 if (SchedRW.TheDef) {
1455 if (!IsRead && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
1456 for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
1457 PI != PE; ++PI) {
1458 addWriteRes(SchedRW.TheDef, *PI);
1459 }
1460 }
1461 else if (IsRead && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
1462 for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
1463 PI != PE; ++PI) {
1464 addReadAdvance(SchedRW.TheDef, *PI);
1465 }
1466 }
1467 }
1468 for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
1469 AI != AE; ++AI) {
1470 IdxVec AliasProcIndices;
1471 if ((*AI)->getValueInit("SchedModel")->isComplete()) {
1472 AliasProcIndices.push_back(
1473 getProcModel((*AI)->getValueAsDef("SchedModel")).Index);
1474 }
1475 else
1476 AliasProcIndices = ProcIndices;
1477 const CodeGenSchedRW &AliasRW = getSchedRW((*AI)->getValueAsDef("AliasRW"));
1478 assert(AliasRW.IsRead == IsRead && "cannot alias reads to writes");
1479
1480 IdxVec ExpandedRWs;
1481 expandRWSequence(AliasRW.Index, ExpandedRWs, IsRead);
1482 for (IdxIter SI = ExpandedRWs.begin(), SE = ExpandedRWs.end();
1483 SI != SE; ++SI) {
1484 collectRWResources(*SI, IsRead, AliasProcIndices);
1485 }
1486 }
1487 }
14511488
14521489 // Collect resources for a set of read/write types and processor indices.
14531490 void CodeGenSchedModels::collectRWResources(const IdxVec &Writes,
14541491 const IdxVec &Reads,
14551492 const IdxVec &ProcIndices) {
14561493
1457 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
1458 const CodeGenSchedRW &SchedRW = getSchedRW(*WI, /*IsRead=*/false);
1459 if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedWriteRes")) {
1460 for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
1461 PI != PE; ++PI) {
1462 addWriteRes(SchedRW.TheDef, *PI);
1463 }
1464 }
1465 for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
1466 AI != AE; ++AI) {
1467 const CodeGenSchedRW &AliasRW =
1468 getSchedRW((*AI)->getValueAsDef("AliasRW"));
1469 if (AliasRW.TheDef && AliasRW.TheDef->isSubClassOf("SchedWriteRes")) {
1470 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
1471 addWriteRes(AliasRW.TheDef, getProcModel(ModelDef).Index);
1472 }
1473 }
1474 }
1475 for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI) {
1476 const CodeGenSchedRW &SchedRW = getSchedRW(*RI, /*IsRead=*/true);
1477 if (SchedRW.TheDef && SchedRW.TheDef->isSubClassOf("SchedReadAdvance")) {
1478 for (IdxIter PI = ProcIndices.begin(), PE = ProcIndices.end();
1479 PI != PE; ++PI) {
1480 addReadAdvance(SchedRW.TheDef, *PI);
1481 }
1482 }
1483 for (RecIter AI = SchedRW.Aliases.begin(), AE = SchedRW.Aliases.end();
1484 AI != AE; ++AI) {
1485 const CodeGenSchedRW &AliasRW =
1486 getSchedRW((*AI)->getValueAsDef("AliasRW"));
1487 if (AliasRW.TheDef && AliasRW.TheDef->isSubClassOf("SchedReadAdvance")) {
1488 Record *ModelDef = AliasRW.TheDef->getValueAsDef("SchedModel");
1489 addReadAdvance(AliasRW.TheDef, getProcModel(ModelDef).Index);
1490 }
1491 }
1492 }
1493 }
1494 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI)
1495 collectRWResources(*WI, /*IsRead=*/false, ProcIndices);
1496
1497 for (IdxIter RI = Reads.begin(), RE = Reads.end(); RI != RE; ++RI)
1498 collectRWResources(*RI, /*IsRead=*/true, ProcIndices);
1499 }
1500
14941501
14951502 // Find the processor's resource units for this kind of resource.
14961503 Record *CodeGenSchedModels::findProcResUnits(Record *ProcResKind,
393393
394394 void collectItinProcResources(Record *ItinClassDef);
395395
396 void collectRWResources(unsigned RWIdx, bool IsRead,
397 const IdxVec &ProcIndices);
398
396399 void collectRWResources(const IdxVec &Writes, const IdxVec &Reads,
397400 const IdxVec &ProcIndices);
398401