llvm.org GIT mirror llvm / dbdbf0c
Separate X86ISelLowering stuff out from the X86ISelPattern.cpp file. Patch contributed by Evan Cheng. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24358 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 14 years ago
5 changed file(s) with 1061 addition(s) and 1007 deletion(s). Raw diff Collapse all Expand all
3131 extern X86VectorEnum X86Vector;
3232 extern bool X86ScalarSSE;
3333
34 /// createX86PatternInstructionSelector - This pass converts an LLVM function
35 /// into a machine code representation in a more aggressive way.
34 /// createX86ISelPattern - This pass converts an LLVM function into a
35 /// machine code representation using pattern matching and a machine
36 /// description file.
3637 ///
37 FunctionPass *createX86PatternInstructionSelector(TargetMachine &TM);
38 FunctionPass *createX86ISelPattern(TargetMachine &TM);
39
40 /// createX86ISelDag - This pass converts a legalized DAG into a
41 /// X86-specific DAG, ready for instruction scheduling.
42 ///
43 FunctionPass *createX86ISelDag(TargetMachine &TM);
3844
3945 /// createX86SSAPeepholeOptimizerPass - Create a pass to perform SSA-based X86
4046 /// specific peephole optimizations.
0 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by Chris Lattner and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "X86.h"
15 #include "X86ISelLowering.h"
16 #include "X86TargetMachine.h"
17 #include "llvm/CallingConv.h"
18 #include "llvm/Function.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/Target/TargetOptions.h"
24 using namespace llvm;
25
26 // FIXME: temporary.
27 #include "llvm/Support/CommandLine.h"
28 static cl::opt EnableFastCC("enable-x86-fastcc", cl::Hidden,
29 cl::desc("Enable fastcc on X86"));
30
31 X86TargetLowering::X86TargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
33
34 // Set up the TargetLowering object.
35
36 // X86 is weird, it always uses i8 for shift amounts and setcc results.
37 setShiftAmountType(MVT::i8);
38 setSetCCResultType(MVT::i8);
39 setSetCCResultContents(ZeroOrOneSetCCResult);
40 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
41
42 // Set up the register classes.
43 // FIXME: Eliminate these two classes when legalize can handle promotions
44 // well.
45 addRegisterClass(MVT::i1, X86::R8RegisterClass);
46 addRegisterClass(MVT::i8, X86::R8RegisterClass);
47 addRegisterClass(MVT::i16, X86::R16RegisterClass);
48 addRegisterClass(MVT::i32, X86::R32RegisterClass);
49
50 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
51 // operation.
52 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
53 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
54 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
55 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
56
57 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
58 // this operation.
59 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
60 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
61
62 if (!X86ScalarSSE) {
63 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
64 // isn't legal.
65 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
66 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
67 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
68 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
69 }
70
71 // Handle FP_TO_UINT by promoting the destination to a larger signed
72 // conversion.
73 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
74 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
75 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
76
77 if (!X86ScalarSSE)
78 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
79
80 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
81 // this operation.
82 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
83 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
84 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
85
86 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
87 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
88 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
89 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
90 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
91 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
92 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
93 setOperationAction(ISD::FREM , MVT::f64 , Expand);
94 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
95 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
96 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
97 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
98 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
99 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
100 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
101 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
102 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
103
104 setOperationAction(ISD::READIO , MVT::i1 , Expand);
105 setOperationAction(ISD::READIO , MVT::i8 , Expand);
106 setOperationAction(ISD::READIO , MVT::i16 , Expand);
107 setOperationAction(ISD::READIO , MVT::i32 , Expand);
108 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
109 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
110 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
111 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
112
113 // These should be promoted to a larger select which is supported.
114 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
115 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
116
117 if (X86ScalarSSE) {
118 // Set up the FP register classes.
119 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
120 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
121
122 // SSE has no load+extend ops
123 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
124 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
125
126 // SSE has no i16 to fp conversion, only i32
127 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
128 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
129
130 // Expand FP_TO_UINT into a select.
131 // FIXME: We would like to use a Custom expander here eventually to do
132 // the optimal thing for SSE vs. the default expansion in the legalizer.
133 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
134
135 // We don't support sin/cos/sqrt/fmod
136 setOperationAction(ISD::FSIN , MVT::f64, Expand);
137 setOperationAction(ISD::FCOS , MVT::f64, Expand);
138 setOperationAction(ISD::FABS , MVT::f64, Expand);
139 setOperationAction(ISD::FNEG , MVT::f64, Expand);
140 setOperationAction(ISD::FREM , MVT::f64, Expand);
141 setOperationAction(ISD::FSIN , MVT::f32, Expand);
142 setOperationAction(ISD::FCOS , MVT::f32, Expand);
143 setOperationAction(ISD::FABS , MVT::f32, Expand);
144 setOperationAction(ISD::FNEG , MVT::f32, Expand);
145 setOperationAction(ISD::FREM , MVT::f32, Expand);
146
147 addLegalFPImmediate(+0.0); // xorps / xorpd
148 } else {
149 // Set up the FP register classes.
150 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
151
152 if (!UnsafeFPMath) {
153 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
154 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
155 }
156
157 addLegalFPImmediate(+0.0); // FLD0
158 addLegalFPImmediate(+1.0); // FLD1
159 addLegalFPImmediate(-0.0); // FLD0/FCHS
160 addLegalFPImmediate(-1.0); // FLD1/FCHS
161 }
162 computeRegisterProperties();
163
164 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
165 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
166 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
167 allowUnalignedMemoryAccesses = true; // x86 supports it!
168 }
169
170 std::vector
171 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
172 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
173 return LowerFastCCArguments(F, DAG);
174 return LowerCCCArguments(F, DAG);
175 }
176
177 std::pair
178 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
179 bool isVarArg, unsigned CallingConv,
180 bool isTailCall,
181 SDOperand Callee, ArgListTy &Args,
182 SelectionDAG &DAG) {
183 assert((!isVarArg || CallingConv == CallingConv::C) &&
184 "Only C takes varargs!");
185 if (CallingConv == CallingConv::Fast && EnableFastCC)
186 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
187 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
188 }
189
190 //===----------------------------------------------------------------------===//
191 // C Calling Convention implementation
192 //===----------------------------------------------------------------------===//
193
194 std::vector
195 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
196 std::vector ArgValues;
197
198 MachineFunction &MF = DAG.getMachineFunction();
199 MachineFrameInfo *MFI = MF.getFrameInfo();
200
201 // Add DAG nodes to load the arguments... On entry to a function on the X86,
202 // the stack frame looks like this:
203 //
204 // [ESP] -- return address
205 // [ESP + 4] -- first argument (leftmost lexically)
206 // [ESP + 8] -- second argument, if first argument is four bytes in size
207 // ...
208 //
209 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
210 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
211 MVT::ValueType ObjectVT = getValueType(I->getType());
212 unsigned ArgIncrement = 4;
213 unsigned ObjSize;
214 switch (ObjectVT) {
215 default: assert(0 && "Unhandled argument type!");
216 case MVT::i1:
217 case MVT::i8: ObjSize = 1; break;
218 case MVT::i16: ObjSize = 2; break;
219 case MVT::i32: ObjSize = 4; break;
220 case MVT::i64: ObjSize = ArgIncrement = 8; break;
221 case MVT::f32: ObjSize = 4; break;
222 case MVT::f64: ObjSize = ArgIncrement = 8; break;
223 }
224 // Create the frame index object for this incoming parameter...
225 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
226
227 // Create the SelectionDAG nodes corresponding to a load from this parameter
228 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
229
230 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
231 // dead loads.
232 SDOperand ArgValue;
233 if (!I->use_empty())
234 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
235 DAG.getSrcValue(NULL));
236 else {
237 if (MVT::isInteger(ObjectVT))
238 ArgValue = DAG.getConstant(0, ObjectVT);
239 else
240 ArgValue = DAG.getConstantFP(0, ObjectVT);
241 }
242 ArgValues.push_back(ArgValue);
243
244 ArgOffset += ArgIncrement; // Move on to the next argument...
245 }
246
247 // If the function takes variable number of arguments, make a frame index for
248 // the start of the first vararg value... for expansion of llvm.va_start.
249 if (F.isVarArg())
250 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
251 ReturnAddrIndex = 0; // No return address slot generated yet.
252 BytesToPopOnReturn = 0; // Callee pops nothing.
253 BytesCallerReserves = ArgOffset;
254
255 // Finally, inform the code generator which regs we return values in.
256 switch (getValueType(F.getReturnType())) {
257 default: assert(0 && "Unknown type!");
258 case MVT::isVoid: break;
259 case MVT::i1:
260 case MVT::i8:
261 case MVT::i16:
262 case MVT::i32:
263 MF.addLiveOut(X86::EAX);
264 break;
265 case MVT::i64:
266 MF.addLiveOut(X86::EAX);
267 MF.addLiveOut(X86::EDX);
268 break;
269 case MVT::f32:
270 case MVT::f64:
271 MF.addLiveOut(X86::ST0);
272 break;
273 }
274 return ArgValues;
275 }
276
277 std::pair
278 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
279 bool isVarArg, bool isTailCall,
280 SDOperand Callee, ArgListTy &Args,
281 SelectionDAG &DAG) {
282 // Count how many bytes are to be pushed on the stack.
283 unsigned NumBytes = 0;
284
285 if (Args.empty()) {
286 // Save zero bytes.
287 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
288 DAG.getConstant(0, getPointerTy()));
289 } else {
290 for (unsigned i = 0, e = Args.size(); i != e; ++i)
291 switch (getValueType(Args[i].second)) {
292 default: assert(0 && "Unknown value type!");
293 case MVT::i1:
294 case MVT::i8:
295 case MVT::i16:
296 case MVT::i32:
297 case MVT::f32:
298 NumBytes += 4;
299 break;
300 case MVT::i64:
301 case MVT::f64:
302 NumBytes += 8;
303 break;
304 }
305
306 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
307 DAG.getConstant(NumBytes, getPointerTy()));
308
309 // Arguments go on the stack in reverse order, as specified by the ABI.
310 unsigned ArgOffset = 0;
311 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
312 X86::ESP, MVT::i32);
313 std::vector Stores;
314
315 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
316 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
317 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
318
319 switch (getValueType(Args[i].second)) {
320 default: assert(0 && "Unexpected ValueType for argument!");
321 case MVT::i1:
322 case MVT::i8:
323 case MVT::i16:
324 // Promote the integer to 32 bits. If the input type is signed use a
325 // sign extend, otherwise use a zero extend.
326 if (Args[i].second->isSigned())
327 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
328 else
329 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
330
331 // FALL THROUGH
332 case MVT::i32:
333 case MVT::f32:
334 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
335 Args[i].first, PtrOff,
336 DAG.getSrcValue(NULL)));
337 ArgOffset += 4;
338 break;
339 case MVT::i64:
340 case MVT::f64:
341 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
342 Args[i].first, PtrOff,
343 DAG.getSrcValue(NULL)));
344 ArgOffset += 8;
345 break;
346 }
347 }
348 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
349 }
350
351 std::vector RetVals;
352 MVT::ValueType RetTyVT = getValueType(RetTy);
353 RetVals.push_back(MVT::Other);
354
355 // The result values produced have to be legal. Promote the result.
356 switch (RetTyVT) {
357 case MVT::isVoid: break;
358 default:
359 RetVals.push_back(RetTyVT);
360 break;
361 case MVT::i1:
362 case MVT::i8:
363 case MVT::i16:
364 RetVals.push_back(MVT::i32);
365 break;
366 case MVT::f32:
367 if (X86ScalarSSE)
368 RetVals.push_back(MVT::f32);
369 else
370 RetVals.push_back(MVT::f64);
371 break;
372 case MVT::i64:
373 RetVals.push_back(MVT::i32);
374 RetVals.push_back(MVT::i32);
375 break;
376 }
377 std::vector Ops;
378 Ops.push_back(Chain);
379 Ops.push_back(Callee);
380 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
381 Ops.push_back(DAG.getConstant(0, getPointerTy()));
382 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
383 RetVals, Ops);
384 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
385
386 SDOperand ResultVal;
387 switch (RetTyVT) {
388 case MVT::isVoid: break;
389 default:
390 ResultVal = TheCall.getValue(1);
391 break;
392 case MVT::i1:
393 case MVT::i8:
394 case MVT::i16:
395 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
396 break;
397 case MVT::f32:
398 // FIXME: we would really like to remember that this FP_ROUND operation is
399 // okay to eliminate if we allow excess FP precision.
400 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
401 break;
402 case MVT::i64:
403 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
404 TheCall.getValue(2));
405 break;
406 }
407
408 return std::make_pair(ResultVal, Chain);
409 }
410
411 SDOperand
412 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
413 Value *VAListV, SelectionDAG &DAG) {
414 // vastart just stores the address of the VarArgsFrameIndex slot.
415 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
416 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
417 DAG.getSrcValue(VAListV));
418 }
419
420
421 std::pair
422 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
423 Value *VAListV, const Type *ArgTy,
424 SelectionDAG &DAG) {
425 MVT::ValueType ArgVT = getValueType(ArgTy);
426 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
427 VAListP, DAG.getSrcValue(VAListV));
428 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
429 DAG.getSrcValue(NULL));
430 unsigned Amt;
431 if (ArgVT == MVT::i32)
432 Amt = 4;
433 else {
434 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
435 "Other types should have been promoted for varargs!");
436 Amt = 8;
437 }
438 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
439 DAG.getConstant(Amt, Val.getValueType()));
440 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
441 Val, VAListP, DAG.getSrcValue(VAListV));
442 return std::make_pair(Result, Chain);
443 }
444
445 //===----------------------------------------------------------------------===//
446 // Fast Calling Convention implementation
447 //===----------------------------------------------------------------------===//
448 //
449 // The X86 'fast' calling convention passes up to two integer arguments in
450 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
451 // and requires that the callee pop its arguments off the stack (allowing proper
452 // tail calls), and has the same return value conventions as C calling convs.
453 //
454 // This calling convention always arranges for the callee pop value to be 8n+4
455 // bytes, which is needed for tail recursion elimination and stack alignment
456 // reasons.
457 //
458 // Note that this can be enhanced in the future to pass fp vals in registers
459 // (when we have a global fp allocator) and do other tricks.
460 //
461
462 /// AddLiveIn - This helper function adds the specified physical register to the
463 /// MachineFunction as a live in value. It also creates a corresponding virtual
464 /// register for it.
465 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
466 TargetRegisterClass *RC) {
467 assert(RC->contains(PReg) && "Not the correct regclass!");
468 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
469 MF.addLiveIn(PReg, VReg);
470 return VReg;
471 }
472
473
474 std::vector
475 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
476 std::vector ArgValues;
477
478 MachineFunction &MF = DAG.getMachineFunction();
479 MachineFrameInfo *MFI = MF.getFrameInfo();
480
481 // Add DAG nodes to load the arguments... On entry to a function the stack
482 // frame looks like this:
483 //
484 // [ESP] -- return address
485 // [ESP + 4] -- first nonreg argument (leftmost lexically)
486 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
487 // ...
488 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
489
490 // Keep track of the number of integer regs passed so far. This can be either
491 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
492 // used).
493 unsigned NumIntRegs = 0;
494
495 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
496 MVT::ValueType ObjectVT = getValueType(I->getType());
497 unsigned ArgIncrement = 4;
498 unsigned ObjSize = 0;
499 SDOperand ArgValue;
500
501 switch (ObjectVT) {
502 default: assert(0 && "Unhandled argument type!");
503 case MVT::i1:
504 case MVT::i8:
505 if (NumIntRegs < 2) {
506 if (!I->use_empty()) {
507 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
508 X86::R8RegisterClass);
509 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
510 DAG.setRoot(ArgValue.getValue(1));
511 }
512 ++NumIntRegs;
513 break;
514 }
515
516 ObjSize = 1;
517 break;
518 case MVT::i16:
519 if (NumIntRegs < 2) {
520 if (!I->use_empty()) {
521 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
522 X86::R16RegisterClass);
523 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
524 DAG.setRoot(ArgValue.getValue(1));
525 }
526 ++NumIntRegs;
527 break;
528 }
529 ObjSize = 2;
530 break;
531 case MVT::i32:
532 if (NumIntRegs < 2) {
533 if (!I->use_empty()) {
534 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
535 X86::R32RegisterClass);
536 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
537 DAG.setRoot(ArgValue.getValue(1));
538 }
539 ++NumIntRegs;
540 break;
541 }
542 ObjSize = 4;
543 break;
544 case MVT::i64:
545 if (NumIntRegs == 0) {
546 if (!I->use_empty()) {
547 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
548 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
549
550 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
551 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
552 DAG.setRoot(Hi.getValue(1));
553
554 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
555 }
556 NumIntRegs = 2;
557 break;
558 } else if (NumIntRegs == 1) {
559 if (!I->use_empty()) {
560 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
561 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
562 DAG.setRoot(Low.getValue(1));
563
564 // Load the high part from memory.
565 // Create the frame index object for this incoming parameter...
566 int FI = MFI->CreateFixedObject(4, ArgOffset);
567 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
568 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
569 DAG.getSrcValue(NULL));
570 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
571 }
572 ArgOffset += 4;
573 NumIntRegs = 2;
574 break;
575 }
576 ObjSize = ArgIncrement = 8;
577 break;
578 case MVT::f32: ObjSize = 4; break;
579 case MVT::f64: ObjSize = ArgIncrement = 8; break;
580 }
581
582 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
583 // dead loads.
584 if (ObjSize && !I->use_empty()) {
585 // Create the frame index object for this incoming parameter...
586 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
587
588 // Create the SelectionDAG nodes corresponding to a load from this
589 // parameter.
590 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
591
592 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
593 DAG.getSrcValue(NULL));
594 } else if (ArgValue.Val == 0) {
595 if (MVT::isInteger(ObjectVT))
596 ArgValue = DAG.getConstant(0, ObjectVT);
597 else
598 ArgValue = DAG.getConstantFP(0, ObjectVT);
599 }
600 ArgValues.push_back(ArgValue);
601
602 if (ObjSize)
603 ArgOffset += ArgIncrement; // Move on to the next argument.
604 }
605
606 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
607 // arguments and the arguments after the retaddr has been pushed are aligned.
608 if ((ArgOffset & 7) == 0)
609 ArgOffset += 4;
610
611 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
612 ReturnAddrIndex = 0; // No return address slot generated yet.
613 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
614 BytesCallerReserves = 0;
615
616 // Finally, inform the code generator which regs we return values in.
617 switch (getValueType(F.getReturnType())) {
618 default: assert(0 && "Unknown type!");
619 case MVT::isVoid: break;
620 case MVT::i1:
621 case MVT::i8:
622 case MVT::i16:
623 case MVT::i32:
624 MF.addLiveOut(X86::EAX);
625 break;
626 case MVT::i64:
627 MF.addLiveOut(X86::EAX);
628 MF.addLiveOut(X86::EDX);
629 break;
630 case MVT::f32:
631 case MVT::f64:
632 MF.addLiveOut(X86::ST0);
633 break;
634 }
635 return ArgValues;
636 }
637
638 std::pair
639 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
640 bool isTailCall, SDOperand Callee,
641 ArgListTy &Args, SelectionDAG &DAG) {
642 // Count how many bytes are to be pushed on the stack.
643 unsigned NumBytes = 0;
644
645 // Keep track of the number of integer regs passed so far. This can be either
646 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
647 // used).
648 unsigned NumIntRegs = 0;
649
650 for (unsigned i = 0, e = Args.size(); i != e; ++i)
651 switch (getValueType(Args[i].second)) {
652 default: assert(0 && "Unknown value type!");
653 case MVT::i1:
654 case MVT::i8:
655 case MVT::i16:
656 case MVT::i32:
657 if (NumIntRegs < 2) {
658 ++NumIntRegs;
659 break;
660 }
661 // fall through
662 case MVT::f32:
663 NumBytes += 4;
664 break;
665 case MVT::i64:
666 if (NumIntRegs == 0) {
667 NumIntRegs = 2;
668 break;
669 } else if (NumIntRegs == 1) {
670 NumIntRegs = 2;
671 NumBytes += 4;
672 break;
673 }
674
675 // fall through
676 case MVT::f64:
677 NumBytes += 8;
678 break;
679 }
680
681 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
682 // arguments and the arguments after the retaddr has been pushed are aligned.
683 if ((NumBytes & 7) == 0)
684 NumBytes += 4;
685
686 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
687 DAG.getConstant(NumBytes, getPointerTy()));
688
689 // Arguments go on the stack in reverse order, as specified by the ABI.
690 unsigned ArgOffset = 0;
691 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
692 X86::ESP, MVT::i32);
693 NumIntRegs = 0;
694 std::vector Stores;
695 std::vector RegValuesToPass;
696 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
697 switch (getValueType(Args[i].second)) {
698 default: assert(0 && "Unexpected ValueType for argument!");
699 case MVT::i1:
700 case MVT::i8:
701 case MVT::i16:
702 case MVT::i32:
703 if (NumIntRegs < 2) {
704 RegValuesToPass.push_back(Args[i].first);
705 ++NumIntRegs;
706 break;
707 }
708 // Fall through
709 case MVT::f32: {
710 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
711 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
712 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
713 Args[i].first, PtrOff,
714 DAG.getSrcValue(NULL)));
715 ArgOffset += 4;
716 break;
717 }
718 case MVT::i64:
719 if (NumIntRegs < 2) { // Can pass part of it in regs?
720 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
721 Args[i].first, DAG.getConstant(1, MVT::i32));
722 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
723 Args[i].first, DAG.getConstant(0, MVT::i32));
724 RegValuesToPass.push_back(Lo);
725 ++NumIntRegs;
726 if (NumIntRegs < 2) { // Pass both parts in regs?
727 RegValuesToPass.push_back(Hi);
728 ++NumIntRegs;
729 } else {
730 // Pass the high part in memory.
731 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
732 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
733 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
734 Hi, PtrOff, DAG.getSrcValue(NULL)));
735 ArgOffset += 4;
736 }
737 break;
738 }
739 // Fall through
740 case MVT::f64:
741 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
742 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
743 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
744 Args[i].first, PtrOff,
745 DAG.getSrcValue(NULL)));
746 ArgOffset += 8;
747 break;
748 }
749 }
750 if (!Stores.empty())
751 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
752
753 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
754 // arguments and the arguments after the retaddr has been pushed are aligned.
755 if ((ArgOffset & 7) == 0)
756 ArgOffset += 4;
757
758 std::vector RetVals;
759 MVT::ValueType RetTyVT = getValueType(RetTy);
760
761 RetVals.push_back(MVT::Other);
762
763 // The result values produced have to be legal. Promote the result.
764 switch (RetTyVT) {
765 case MVT::isVoid: break;
766 default:
767 RetVals.push_back(RetTyVT);
768 break;
769 case MVT::i1:
770 case MVT::i8:
771 case MVT::i16:
772 RetVals.push_back(MVT::i32);
773 break;
774 case MVT::f32:
775 if (X86ScalarSSE)
776 RetVals.push_back(MVT::f32);
777 else
778 RetVals.push_back(MVT::f64);
779 break;
780 case MVT::i64:
781 RetVals.push_back(MVT::i32);
782 RetVals.push_back(MVT::i32);
783 break;
784 }
785
786 std::vector Ops;
787 Ops.push_back(Chain);
788 Ops.push_back(Callee);
789 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
790 // Callee pops all arg values on the stack.
791 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
792
793 // Pass register arguments as needed.
794 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
795
796 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
797 RetVals, Ops);
798 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
799
800 SDOperand ResultVal;
801 switch (RetTyVT) {
802 case MVT::isVoid: break;
803 default:
804 ResultVal = TheCall.getValue(1);
805 break;
806 case MVT::i1:
807 case MVT::i8:
808 case MVT::i16:
809 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
810 break;
811 case MVT::f32:
812 // FIXME: we would really like to remember that this FP_ROUND operation is
813 // okay to eliminate if we allow excess FP precision.
814 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
815 break;
816 case MVT::i64:
817 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
818 TheCall.getValue(2));
819 break;
820 }
821
822 return std::make_pair(ResultVal, Chain);
823 }
824
825 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
826 if (ReturnAddrIndex == 0) {
827 // Set up a frame object for the return address.
828 MachineFunction &MF = DAG.getMachineFunction();
829 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
830 }
831
832 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
833 }
834
835
836
837 std::pair X86TargetLowering::
838 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
839 SelectionDAG &DAG) {
840 SDOperand Result;
841 if (Depth) // Depths > 0 not supported yet!
842 Result = DAG.getConstant(0, getPointerTy());
843 else {
844 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
845 if (!isFrameAddress)
846 // Just load the return address
847 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
848 DAG.getSrcValue(NULL));
849 else
850 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
851 DAG.getConstant(4, MVT::i32));
852 }
853 return std::make_pair(Result, Chain);
854 }
855
856 //===----------------------------------------------------------------------===//
857 // X86 Custom Lowering Hooks
858 //===----------------------------------------------------------------------===//
859
860 /// LowerOperation - Provide custom lowering hooks for some operations.
861 ///
862 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
863 switch (Op.getOpcode()) {
864 default: assert(0 && "Should not custom lower this!");
865 case ISD::SINT_TO_FP: {
866 assert(Op.getValueType() == MVT::f64 &&
867 Op.getOperand(0).getValueType() == MVT::i64 &&
868 "Unknown SINT_TO_FP to lower!");
869 // We lower sint64->FP into a store to a temporary stack slot, followed by a
870 // FILD64m node.
871 MachineFunction &MF = DAG.getMachineFunction();
872 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
873 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
874 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
875 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
876 std::vector RTs;
877 RTs.push_back(MVT::f64);
878 RTs.push_back(MVT::Other);
879 std::vector Ops;
880 Ops.push_back(Store);
881 Ops.push_back(StackSlot);
882 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
883 }
884 case ISD::FP_TO_SINT: {
885 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
886 Op.getOperand(0).getValueType() == MVT::f64 &&
887 "Unknown FP_TO_SINT to lower!");
888 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
889 // stack slot.
890 MachineFunction &MF = DAG.getMachineFunction();
891 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
892 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
893 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
894
895 unsigned Opc;
896 switch (Op.getValueType()) {
897 default: assert(0 && "Invalid FP_TO_SINT to lower!");
898 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
899 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
900 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
901 }
902
903 // Build the FP_TO_INT*_IN_MEM
904 std::vector Ops;
905 Ops.push_back(DAG.getEntryNode());
906 Ops.push_back(Op.getOperand(0));
907 Ops.push_back(StackSlot);
908 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
909
910 // Load the result.
911 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
912 DAG.getSrcValue(NULL));
913 }
914 }
915 }
0 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file was developed by Chris Lattner and is distributed under
5 // the University of Illinois Open Source License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that X86 uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #ifndef X86ISELLOWERING_H
15 #define X86ISELLOWERING_H
16
17 #include "llvm/Target/TargetLowering.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19
20 namespace llvm {
21 // X86 Specific DAG Nodes
22 namespace X86ISD {
23 enum NodeType {
24 // Start the numbering where the builtin ops leave off.
25 FIRST_NUMBER = ISD::BUILTIN_OP_END,
26
27 /// FILD64m - This instruction implements SINT_TO_FP with a
28 /// 64-bit source in memory and a FP reg result. This corresponds to
29 /// the X86::FILD64m instruction. It has two inputs (token chain and
30 /// address) and two outputs (FP value and token chain).
31 FILD64m,
32
33 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
34 /// integer destination in memory and a FP reg source. This corresponds
35 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
36 /// has two inputs (token chain and address) and two outputs (FP value and
37 /// token chain).
38 FP_TO_INT16_IN_MEM,
39 FP_TO_INT32_IN_MEM,
40 FP_TO_INT64_IN_MEM,
41
42 /// CALL/TAILCALL - These operations represent an abstract X86 call
43 /// instruction, which includes a bunch of information. In particular the
44 /// operands of these node are:
45 ///
46 /// #0 - The incoming token chain
47 /// #1 - The callee
48 /// #2 - The number of arg bytes the caller pushes on the stack.
49 /// #3 - The number of arg bytes the callee pops off the stack.
50 /// #4 - The value to pass in AL/AX/EAX (optional)
51 /// #5 - The value to pass in DL/DX/EDX (optional)
52 ///
53 /// The result values of these nodes are:
54 ///
55 /// #0 - The outgoing token chain
56 /// #1 - The first register result value (optional)
57 /// #2 - The second register result value (optional)
58 ///
59 /// The CALL vs TAILCALL distinction boils down to whether the callee is
60 /// known not to modify the caller's stack frame, as is standard with
61 /// LLVM.
62 CALL,
63 TAILCALL,
64 };
65 }
66
67 //===----------------------------------------------------------------------===//
68 // X86TargetLowering - X86 Implementation of the TargetLowering interface
69 class X86TargetLowering : public TargetLowering {
70 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
71 int ReturnAddrIndex; // FrameIndex for return slot.
72 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
73 int BytesCallerReserves; // Number of arg bytes caller makes.
74 public:
75 X86TargetLowering(TargetMachine &TM);
76
77 // Return the number of bytes that a function should pop when it returns (in
78 // addition to the space used by the return address).
79 //
80 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
81
82 // Return the number of bytes that the caller reserves for arguments passed
83 // to this function.
84 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
85
86 /// LowerOperation - Provide custom lowering hooks for some operations.
87 ///
88 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
89
90 /// LowerArguments - This hook must be implemented to indicate how we should
91 /// lower the arguments for the specified function, into the specified DAG.
92 virtual std::vector
93 LowerArguments(Function &F, SelectionDAG &DAG);
94
95 /// LowerCallTo - This hook lowers an abstract call to a function into an
96 /// actual call.
97 virtual std::pair
98 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
99 bool isTailCall, SDOperand Callee, ArgListTy &Args,
100 SelectionDAG &DAG);
101
102 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
103 Value *VAListV, SelectionDAG &DAG);
104 virtual std::pair
105 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
106 const Type *ArgTy, SelectionDAG &DAG);
107
108 virtual std::pair
109 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
110 SelectionDAG &DAG);
111
112 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
113
114 private:
115 // C Calling Convention implementation.
116 std::vector LowerCCCArguments(Function &F, SelectionDAG &DAG);
117 std::pair
118 LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
119 bool isTailCall,
120 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
121
122 // Fast Calling Convention implementation.
123 std::vector LowerFastCCArguments(Function &F, SelectionDAG &DAG);
124 std::pair
125 LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
126 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
127 };
128 }
129
130 #endif // X86ISELLOWERING_H
1414 #include "X86InstrBuilder.h"
1515 #include "X86RegisterInfo.h"
1616 #include "X86Subtarget.h"
17 #include "X86ISelLowering.h"
1718 #include "llvm/CallingConv.h"
1819 #include "llvm/Constants.h"
1920 #include "llvm/Instructions.h"
3435 #include
3536 #include
3637 using namespace llvm;
37
38 // FIXME: temporary.
39 #include "llvm/Support/CommandLine.h"
40 static cl::opt EnableFastCC("enable-x86-fastcc", cl::Hidden,
41 cl::desc("Enable fastcc on X86"));
42
43 namespace {
44 // X86 Specific DAG Nodes
45 namespace X86ISD {
46 enum NodeType {
47 // Start the numbering where the builtin ops leave off.
48 FIRST_NUMBER = ISD::BUILTIN_OP_END,
49
50 /// FILD64m - This instruction implements SINT_TO_FP with a
51 /// 64-bit source in memory and a FP reg result. This corresponds to
52 /// the X86::FILD64m instruction. It has two inputs (token chain and
53 /// address) and two outputs (FP value and token chain).
54 FILD64m,
55
56 /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
57 /// integer destination in memory and a FP reg source. This corresponds
58 /// to the X86::FIST*m instructions and the rounding mode change stuff. It
59 /// has two inputs (token chain and address) and two outputs (FP value and
60 /// token chain).
61 FP_TO_INT16_IN_MEM,
62 FP_TO_INT32_IN_MEM,
63 FP_TO_INT64_IN_MEM,
64
65 /// CALL/TAILCALL - These operations represent an abstract X86 call
66 /// instruction, which includes a bunch of information. In particular the
67 /// operands of these node are:
68 ///
69 /// #0 - The incoming token chain
70 /// #1 - The callee
71 /// #2 - The number of arg bytes the caller pushes on the stack.
72 /// #3 - The number of arg bytes the callee pops off the stack.
73 /// #4 - The value to pass in AL/AX/EAX (optional)
74 /// #5 - The value to pass in DL/DX/EDX (optional)
75 ///
76 /// The result values of these nodes are:
77 ///
78 /// #0 - The outgoing token chain
79 /// #1 - The first register result value (optional)
80 /// #2 - The second register result value (optional)
81 ///
82 /// The CALL vs TAILCALL distinction boils down to whether the callee is
83 /// known not to modify the caller's stack frame, as is standard with
84 /// LLVM.
85 CALL,
86 TAILCALL,
87 };
88 }
89 }
90
91 //===----------------------------------------------------------------------===//
92 // X86TargetLowering - X86 Implementation of the TargetLowering interface
93 namespace {
94 class X86TargetLowering : public TargetLowering {
95 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
96 int ReturnAddrIndex; // FrameIndex for return slot.
97 int BytesToPopOnReturn; // Number of arg bytes ret should pop.
98 int BytesCallerReserves; // Number of arg bytes caller makes.
99 public:
100 X86TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
101 // Set up the TargetLowering object.
102
103 // X86 is weird, it always uses i8 for shift amounts and setcc results.
104 setShiftAmountType(MVT::i8);
105 setSetCCResultType(MVT::i8);
106 setSetCCResultContents(ZeroOrOneSetCCResult);
107 setShiftAmountFlavor(Mask); // shl X, 32 == shl X, 0
108
109 // Set up the register classes.
110 // FIXME: Eliminate these two classes when legalize can handle promotions
111 // well.
112 addRegisterClass(MVT::i1, X86::R8RegisterClass);
113 addRegisterClass(MVT::i8, X86::R8RegisterClass);
114 addRegisterClass(MVT::i16, X86::R16RegisterClass);
115 addRegisterClass(MVT::i32, X86::R32RegisterClass);
116
117 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this
118 // operation.
119 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote);
120 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote);
121 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote);
122 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote);
123
124 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have
125 // this operation.
126 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote);
127 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote);
128
129 if (!X86ScalarSSE) {
130 // We can handle SINT_TO_FP and FP_TO_SINT from/TO i64 even though i64
131 // isn't legal.
132 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom);
133 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom);
134 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom);
135 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom);
136 }
137
138 // Handle FP_TO_UINT by promoting the destination to a larger signed
139 // conversion.
140 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote);
141 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote);
142 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote);
143
144 if (!X86ScalarSSE)
145 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote);
146
147 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have
148 // this operation.
149 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote);
150 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote);
151 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote);
152
153 setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand);
154 setOperationAction(ISD::BRTWOWAY_CC , MVT::Other, Expand);
155 setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
156 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand);
157 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand);
158 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand);
159 setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
160 setOperationAction(ISD::FREM , MVT::f64 , Expand);
161 setOperationAction(ISD::CTPOP , MVT::i8 , Expand);
162 setOperationAction(ISD::CTTZ , MVT::i8 , Expand);
163 setOperationAction(ISD::CTLZ , MVT::i8 , Expand);
164 setOperationAction(ISD::CTPOP , MVT::i16 , Expand);
165 setOperationAction(ISD::CTTZ , MVT::i16 , Expand);
166 setOperationAction(ISD::CTLZ , MVT::i16 , Expand);
167 setOperationAction(ISD::CTPOP , MVT::i32 , Expand);
168 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
169 setOperationAction(ISD::CTLZ , MVT::i32 , Expand);
170
171 setOperationAction(ISD::READIO , MVT::i1 , Expand);
172 setOperationAction(ISD::READIO , MVT::i8 , Expand);
173 setOperationAction(ISD::READIO , MVT::i16 , Expand);
174 setOperationAction(ISD::READIO , MVT::i32 , Expand);
175 setOperationAction(ISD::WRITEIO , MVT::i1 , Expand);
176 setOperationAction(ISD::WRITEIO , MVT::i8 , Expand);
177 setOperationAction(ISD::WRITEIO , MVT::i16 , Expand);
178 setOperationAction(ISD::WRITEIO , MVT::i32 , Expand);
179
180 // These should be promoted to a larger select which is supported.
181 setOperationAction(ISD::SELECT , MVT::i1 , Promote);
182 setOperationAction(ISD::SELECT , MVT::i8 , Promote);
183
184 if (X86ScalarSSE) {
185 // Set up the FP register classes.
186 addRegisterClass(MVT::f32, X86::V4F4RegisterClass);
187 addRegisterClass(MVT::f64, X86::V2F8RegisterClass);
188
189 // SSE has no load+extend ops
190 setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
191 setOperationAction(ISD::ZEXTLOAD, MVT::f32, Expand);
192
193 // SSE has no i16 to fp conversion, only i32
194 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
195 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
196
197 // Expand FP_TO_UINT into a select.
198 // FIXME: We would like to use a Custom expander here eventually to do
199 // the optimal thing for SSE vs. the default expansion in the legalizer.
200 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand);
201
202 // We don't support sin/cos/sqrt/fmod
203 setOperationAction(ISD::FSIN , MVT::f64, Expand);
204 setOperationAction(ISD::FCOS , MVT::f64, Expand);
205 setOperationAction(ISD::FABS , MVT::f64, Expand);
206 setOperationAction(ISD::FNEG , MVT::f64, Expand);
207 setOperationAction(ISD::FREM , MVT::f64, Expand);
208 setOperationAction(ISD::FSIN , MVT::f32, Expand);
209 setOperationAction(ISD::FCOS , MVT::f32, Expand);
210 setOperationAction(ISD::FABS , MVT::f32, Expand);
211 setOperationAction(ISD::FNEG , MVT::f32, Expand);
212 setOperationAction(ISD::FREM , MVT::f32, Expand);
213
214 addLegalFPImmediate(+0.0); // xorps / xorpd
215 } else {
216 // Set up the FP register classes.
217 addRegisterClass(MVT::f64, X86::RFPRegisterClass);
218
219 if (!UnsafeFPMath) {
220 setOperationAction(ISD::FSIN , MVT::f64 , Expand);
221 setOperationAction(ISD::FCOS , MVT::f64 , Expand);
222 }
223
224 addLegalFPImmediate(+0.0); // FLD0
225 addLegalFPImmediate(+1.0); // FLD1
226 addLegalFPImmediate(-0.0); // FLD0/FCHS
227 addLegalFPImmediate(-1.0); // FLD1/FCHS
228 }
229 computeRegisterProperties();
230
231 maxStoresPerMemSet = 8; // For %llvm.memset -> sequence of stores
232 maxStoresPerMemCpy = 8; // For %llvm.memcpy -> sequence of stores
233 maxStoresPerMemMove = 8; // For %llvm.memmove -> sequence of stores
234 allowUnalignedMemoryAccesses = true; // x86 supports it!
235 }
236
237 // Return the number of bytes that a function should pop when it returns (in
238 // addition to the space used by the return address).
239 //
240 unsigned getBytesToPopOnReturn() const { return BytesToPopOnReturn; }
241
242 // Return the number of bytes that the caller reserves for arguments passed
243 // to this function.
244 unsigned getBytesCallerReserves() const { return BytesCallerReserves; }
245
246 /// LowerOperation - Provide custom lowering hooks for some operations.
247 ///
248 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
249
250 /// LowerArguments - This hook must be implemented to indicate how we should
251 /// lower the arguments for the specified function, into the specified DAG.
252 virtual std::vector
253 LowerArguments(Function &F, SelectionDAG &DAG);
254
255 /// LowerCallTo - This hook lowers an abstract call to a function into an
256 /// actual call.
257 virtual std::pair
258 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
259 bool isTailCall, SDOperand Callee, ArgListTy &Args,
260 SelectionDAG &DAG);
261
262 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
263 Value *VAListV, SelectionDAG &DAG);
264 virtual std::pair
265 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
266 const Type *ArgTy, SelectionDAG &DAG);
267
268 virtual std::pair
269 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
270 SelectionDAG &DAG);
271
272 SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG);
273
274 private:
275 // C Calling Convention implementation.
276 std::vector LowerCCCArguments(Function &F, SelectionDAG &DAG);
277 std::pair
278 LowerCCCCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
279 bool isTailCall,
280 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
281
282 // Fast Calling Convention implementation.
283 std::vector LowerFastCCArguments(Function &F, SelectionDAG &DAG);
284 std::pair
285 LowerFastCCCallTo(SDOperand Chain, const Type *RetTy, bool isTailCall,
286 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
287 };
288 }
289
290 std::vector
291 X86TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
292 if (F.getCallingConv() == CallingConv::Fast && EnableFastCC)
293 return LowerFastCCArguments(F, DAG);
294 return LowerCCCArguments(F, DAG);
295 }
296
297 std::pair
298 X86TargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
299 bool isVarArg, unsigned CallingConv,
300 bool isTailCall,
301 SDOperand Callee, ArgListTy &Args,
302 SelectionDAG &DAG) {
303 assert((!isVarArg || CallingConv == CallingConv::C) &&
304 "Only C takes varargs!");
305 if (CallingConv == CallingConv::Fast && EnableFastCC)
306 return LowerFastCCCallTo(Chain, RetTy, isTailCall, Callee, Args, DAG);
307 return LowerCCCCallTo(Chain, RetTy, isVarArg, isTailCall, Callee, Args, DAG);
308 }
309
310 //===----------------------------------------------------------------------===//
311 // C Calling Convention implementation
312 //===----------------------------------------------------------------------===//
313
314 std::vector
315 X86TargetLowering::LowerCCCArguments(Function &F, SelectionDAG &DAG) {
316 std::vector ArgValues;
317
318 MachineFunction &MF = DAG.getMachineFunction();
319 MachineFrameInfo *MFI = MF.getFrameInfo();
320
321 // Add DAG nodes to load the arguments... On entry to a function on the X86,
322 // the stack frame looks like this:
323 //
324 // [ESP] -- return address
325 // [ESP + 4] -- first argument (leftmost lexically)
326 // [ESP + 8] -- second argument, if first argument is four bytes in size
327 // ...
328 //
329 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
330 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
331 MVT::ValueType ObjectVT = getValueType(I->getType());
332 unsigned ArgIncrement = 4;
333 unsigned ObjSize;
334 switch (ObjectVT) {
335 default: assert(0 && "Unhandled argument type!");
336 case MVT::i1:
337 case MVT::i8: ObjSize = 1; break;
338 case MVT::i16: ObjSize = 2; break;
339 case MVT::i32: ObjSize = 4; break;
340 case MVT::i64: ObjSize = ArgIncrement = 8; break;
341 case MVT::f32: ObjSize = 4; break;
342 case MVT::f64: ObjSize = ArgIncrement = 8; break;
343 }
344 // Create the frame index object for this incoming parameter...
345 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
346
347 // Create the SelectionDAG nodes corresponding to a load from this parameter
348 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
349
350 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
351 // dead loads.
352 SDOperand ArgValue;
353 if (!I->use_empty())
354 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
355 DAG.getSrcValue(NULL));
356 else {
357 if (MVT::isInteger(ObjectVT))
358 ArgValue = DAG.getConstant(0, ObjectVT);
359 else
360 ArgValue = DAG.getConstantFP(0, ObjectVT);
361 }
362 ArgValues.push_back(ArgValue);
363
364 ArgOffset += ArgIncrement; // Move on to the next argument...
365 }
366
367 // If the function takes variable number of arguments, make a frame index for
368 // the start of the first vararg value... for expansion of llvm.va_start.
369 if (F.isVarArg())
370 VarArgsFrameIndex = MFI->CreateFixedObject(1, ArgOffset);
371 ReturnAddrIndex = 0; // No return address slot generated yet.
372 BytesToPopOnReturn = 0; // Callee pops nothing.
373 BytesCallerReserves = ArgOffset;
374
375 // Finally, inform the code generator which regs we return values in.
376 switch (getValueType(F.getReturnType())) {
377 default: assert(0 && "Unknown type!");
378 case MVT::isVoid: break;
379 case MVT::i1:
380 case MVT::i8:
381 case MVT::i16:
382 case MVT::i32:
383 MF.addLiveOut(X86::EAX);
384 break;
385 case MVT::i64:
386 MF.addLiveOut(X86::EAX);
387 MF.addLiveOut(X86::EDX);
388 break;
389 case MVT::f32:
390 case MVT::f64:
391 MF.addLiveOut(X86::ST0);
392 break;
393 }
394 return ArgValues;
395 }
396
397 std::pair
398 X86TargetLowering::LowerCCCCallTo(SDOperand Chain, const Type *RetTy,
399 bool isVarArg, bool isTailCall,
400 SDOperand Callee, ArgListTy &Args,
401 SelectionDAG &DAG) {
402 // Count how many bytes are to be pushed on the stack.
403 unsigned NumBytes = 0;
404
405 if (Args.empty()) {
406 // Save zero bytes.
407 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
408 DAG.getConstant(0, getPointerTy()));
409 } else {
410 for (unsigned i = 0, e = Args.size(); i != e; ++i)
411 switch (getValueType(Args[i].second)) {
412 default: assert(0 && "Unknown value type!");
413 case MVT::i1:
414 case MVT::i8:
415 case MVT::i16:
416 case MVT::i32:
417 case MVT::f32:
418 NumBytes += 4;
419 break;
420 case MVT::i64:
421 case MVT::f64:
422 NumBytes += 8;
423 break;
424 }
425
426 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
427 DAG.getConstant(NumBytes, getPointerTy()));
428
429 // Arguments go on the stack in reverse order, as specified by the ABI.
430 unsigned ArgOffset = 0;
431 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
432 X86::ESP, MVT::i32);
433 std::vector Stores;
434
435 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
436 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
437 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
438
439 switch (getValueType(Args[i].second)) {
440 default: assert(0 && "Unexpected ValueType for argument!");
441 case MVT::i1:
442 case MVT::i8:
443 case MVT::i16:
444 // Promote the integer to 32 bits. If the input type is signed use a
445 // sign extend, otherwise use a zero extend.
446 if (Args[i].second->isSigned())
447 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
448 else
449 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
450
451 // FALL THROUGH
452 case MVT::i32:
453 case MVT::f32:
454 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
455 Args[i].first, PtrOff,
456 DAG.getSrcValue(NULL)));
457 ArgOffset += 4;
458 break;
459 case MVT::i64:
460 case MVT::f64:
461 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
462 Args[i].first, PtrOff,
463 DAG.getSrcValue(NULL)));
464 ArgOffset += 8;
465 break;
466 }
467 }
468 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
469 }
470
471 std::vector RetVals;
472 MVT::ValueType RetTyVT = getValueType(RetTy);
473 RetVals.push_back(MVT::Other);
474
475 // The result values produced have to be legal. Promote the result.
476 switch (RetTyVT) {
477 case MVT::isVoid: break;
478 default:
479 RetVals.push_back(RetTyVT);
480 break;
481 case MVT::i1:
482 case MVT::i8:
483 case MVT::i16:
484 RetVals.push_back(MVT::i32);
485 break;
486 case MVT::f32:
487 if (X86ScalarSSE)
488 RetVals.push_back(MVT::f32);
489 else
490 RetVals.push_back(MVT::f64);
491 break;
492 case MVT::i64:
493 RetVals.push_back(MVT::i32);
494 RetVals.push_back(MVT::i32);
495 break;
496 }
497 std::vector Ops;
498 Ops.push_back(Chain);
499 Ops.push_back(Callee);
500 Ops.push_back(DAG.getConstant(NumBytes, getPointerTy()));
501 Ops.push_back(DAG.getConstant(0, getPointerTy()));
502 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
503 RetVals, Ops);
504 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
505
506 SDOperand ResultVal;
507 switch (RetTyVT) {
508 case MVT::isVoid: break;
509 default:
510 ResultVal = TheCall.getValue(1);
511 break;
512 case MVT::i1:
513 case MVT::i8:
514 case MVT::i16:
515 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
516 break;
517 case MVT::f32:
518 // FIXME: we would really like to remember that this FP_ROUND operation is
519 // okay to eliminate if we allow excess FP precision.
520 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
521 break;
522 case MVT::i64:
523 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
524 TheCall.getValue(2));
525 break;
526 }
527
528 return std::make_pair(ResultVal, Chain);
529 }
530
531 SDOperand
532 X86TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
533 Value *VAListV, SelectionDAG &DAG) {
534 // vastart just stores the address of the VarArgsFrameIndex slot.
535 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
536 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
537 DAG.getSrcValue(VAListV));
538 }
539
540
541 std::pair
542 X86TargetLowering::LowerVAArg(SDOperand Chain, SDOperand VAListP,
543 Value *VAListV, const Type *ArgTy,
544 SelectionDAG &DAG) {
545 MVT::ValueType ArgVT = getValueType(ArgTy);
546 SDOperand Val = DAG.getLoad(MVT::i32, Chain,
547 VAListP, DAG.getSrcValue(VAListV));
548 SDOperand Result = DAG.getLoad(ArgVT, Chain, Val,
549 DAG.getSrcValue(NULL));
550 unsigned Amt;
551 if (ArgVT == MVT::i32)
552 Amt = 4;
553 else {
554 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
555 "Other types should have been promoted for varargs!");
556 Amt = 8;
557 }
558 Val = DAG.getNode(ISD::ADD, Val.getValueType(), Val,
559 DAG.getConstant(Amt, Val.getValueType()));
560 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
561 Val, VAListP, DAG.getSrcValue(VAListV));
562 return std::make_pair(Result, Chain);
563 }
564
565 //===----------------------------------------------------------------------===//
566 // Fast Calling Convention implementation
567 //===----------------------------------------------------------------------===//
568 //
569 // The X86 'fast' calling convention passes up to two integer arguments in
570 // registers (an appropriate portion of EAX/EDX), passes arguments in C order,
571 // and requires that the callee pop its arguments off the stack (allowing proper
572 // tail calls), and has the same return value conventions as C calling convs.
573 //
574 // This calling convention always arranges for the callee pop value to be 8n+4
575 // bytes, which is needed for tail recursion elimination and stack alignment
576 // reasons.
577 //
578 // Note that this can be enhanced in the future to pass fp vals in registers
579 // (when we have a global fp allocator) and do other tricks.
580 //
581
582 /// AddLiveIn - This helper function adds the specified physical register to the
583 /// MachineFunction as a live in value. It also creates a corresponding virtual
584 /// register for it.
585 static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
586 TargetRegisterClass *RC) {
587 assert(RC->contains(PReg) && "Not the correct regclass!");
588 unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
589 MF.addLiveIn(PReg, VReg);
590 return VReg;
591 }
592
593
594 std::vector
595 X86TargetLowering::LowerFastCCArguments(Function &F, SelectionDAG &DAG) {
596 std::vector ArgValues;
597
598 MachineFunction &MF = DAG.getMachineFunction();
599 MachineFrameInfo *MFI = MF.getFrameInfo();
600
601 // Add DAG nodes to load the arguments... On entry to a function the stack
602 // frame looks like this:
603 //
604 // [ESP] -- return address
605 // [ESP + 4] -- first nonreg argument (leftmost lexically)
606 // [ESP + 8] -- second nonreg argument, if first argument is 4 bytes in size
607 // ...
608 unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
609
610 // Keep track of the number of integer regs passed so far. This can be either
611 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
612 // used).
613 unsigned NumIntRegs = 0;
614
615 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
616 MVT::ValueType ObjectVT = getValueType(I->getType());
617 unsigned ArgIncrement = 4;
618 unsigned ObjSize = 0;
619 SDOperand ArgValue;
620
621 switch (ObjectVT) {
622 default: assert(0 && "Unhandled argument type!");
623 case MVT::i1:
624 case MVT::i8:
625 if (NumIntRegs < 2) {
626 if (!I->use_empty()) {
627 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DL : X86::AL,
628 X86::R8RegisterClass);
629 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i8);
630 DAG.setRoot(ArgValue.getValue(1));
631 }
632 ++NumIntRegs;
633 break;
634 }
635
636 ObjSize = 1;
637 break;
638 case MVT::i16:
639 if (NumIntRegs < 2) {
640 if (!I->use_empty()) {
641 unsigned VReg = AddLiveIn(MF, NumIntRegs ? X86::DX : X86::AX,
642 X86::R16RegisterClass);
643 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i16);
644 DAG.setRoot(ArgValue.getValue(1));
645 }
646 ++NumIntRegs;
647 break;
648 }
649 ObjSize = 2;
650 break;
651 case MVT::i32:
652 if (NumIntRegs < 2) {
653 if (!I->use_empty()) {
654 unsigned VReg = AddLiveIn(MF,NumIntRegs ? X86::EDX : X86::EAX,
655 X86::R32RegisterClass);
656 ArgValue = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
657 DAG.setRoot(ArgValue.getValue(1));
658 }
659 ++NumIntRegs;
660 break;
661 }
662 ObjSize = 4;
663 break;
664 case MVT::i64:
665 if (NumIntRegs == 0) {
666 if (!I->use_empty()) {
667 unsigned BotReg = AddLiveIn(MF, X86::EAX, X86::R32RegisterClass);
668 unsigned TopReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
669
670 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
671 SDOperand Hi = DAG.getCopyFromReg(Low.getValue(1), TopReg, MVT::i32);
672 DAG.setRoot(Hi.getValue(1));
673
674 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
675 }
676 NumIntRegs = 2;
677 break;
678 } else if (NumIntRegs == 1) {
679 if (!I->use_empty()) {
680 unsigned BotReg = AddLiveIn(MF, X86::EDX, X86::R32RegisterClass);
681 SDOperand Low = DAG.getCopyFromReg(DAG.getRoot(), BotReg, MVT::i32);
682 DAG.setRoot(Low.getValue(1));
683
684 // Load the high part from memory.
685 // Create the frame index object for this incoming parameter...
686 int FI = MFI->CreateFixedObject(4, ArgOffset);
687 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
688 SDOperand Hi = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
689 DAG.getSrcValue(NULL));
690 ArgValue = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Low, Hi);
691 }
692 ArgOffset += 4;
693 NumIntRegs = 2;
694 break;
695 }
696 ObjSize = ArgIncrement = 8;
697 break;
698 case MVT::f32: ObjSize = 4; break;
699 case MVT::f64: ObjSize = ArgIncrement = 8; break;
700 }
701
702 // Don't codegen dead arguments. FIXME: remove this check when we can nuke
703 // dead loads.
704 if (ObjSize && !I->use_empty()) {
705 // Create the frame index object for this incoming parameter...
706 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
707
708 // Create the SelectionDAG nodes corresponding to a load from this
709 // parameter.
710 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
711
712 ArgValue = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
713 DAG.getSrcValue(NULL));
714 } else if (ArgValue.Val == 0) {
715 if (MVT::isInteger(ObjectVT))
716 ArgValue = DAG.getConstant(0, ObjectVT);
717 else
718 ArgValue = DAG.getConstantFP(0, ObjectVT);
719 }
720 ArgValues.push_back(ArgValue);
721
722 if (ObjSize)
723 ArgOffset += ArgIncrement; // Move on to the next argument.
724 }
725
726 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
727 // arguments and the arguments after the retaddr has been pushed are aligned.
728 if ((ArgOffset & 7) == 0)
729 ArgOffset += 4;
730
731 VarArgsFrameIndex = 0xAAAAAAA; // fastcc functions can't have varargs.
732 ReturnAddrIndex = 0; // No return address slot generated yet.
733 BytesToPopOnReturn = ArgOffset; // Callee pops all stack arguments.
734 BytesCallerReserves = 0;
735
736 // Finally, inform the code generator which regs we return values in.
737 switch (getValueType(F.getReturnType())) {
738 default: assert(0 && "Unknown type!");
739 case MVT::isVoid: break;
740 case MVT::i1:
741 case MVT::i8:
742 case MVT::i16:
743 case MVT::i32:
744 MF.addLiveOut(X86::EAX);
745 break;
746 case MVT::i64:
747 MF.addLiveOut(X86::EAX);
748 MF.addLiveOut(X86::EDX);
749 break;
750 case MVT::f32:
751 case MVT::f64:
752 MF.addLiveOut(X86::ST0);
753 break;
754 }
755 return ArgValues;
756 }
757
758 std::pair
759 X86TargetLowering::LowerFastCCCallTo(SDOperand Chain, const Type *RetTy,
760 bool isTailCall, SDOperand Callee,
761 ArgListTy &Args, SelectionDAG &DAG) {
762 // Count how many bytes are to be pushed on the stack.
763 unsigned NumBytes = 0;
764
765 // Keep track of the number of integer regs passed so far. This can be either
766 // 0 (neither EAX or EDX used), 1 (EAX is used) or 2 (EAX and EDX are both
767 // used).
768 unsigned NumIntRegs = 0;
769
770 for (unsigned i = 0, e = Args.size(); i != e; ++i)
771 switch (getValueType(Args[i].second)) {
772 default: assert(0 && "Unknown value type!");
773 case MVT::i1:
774 case MVT::i8:
775 case MVT::i16:
776 case MVT::i32:
777 if (NumIntRegs < 2) {
778 ++NumIntRegs;
779 break;
780 }
781 // fall through
782 case MVT::f32:
783 NumBytes += 4;
784 break;
785 case MVT::i64:
786 if (NumIntRegs == 0) {
787 NumIntRegs = 2;
788 break;
789 } else if (NumIntRegs == 1) {
790 NumIntRegs = 2;
791 NumBytes += 4;
792 break;
793 }
794
795 // fall through
796 case MVT::f64:
797 NumBytes += 8;
798 break;
799 }
800
801 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
802 // arguments and the arguments after the retaddr has been pushed are aligned.
803 if ((NumBytes & 7) == 0)
804 NumBytes += 4;
805
806 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
807 DAG.getConstant(NumBytes, getPointerTy()));
808
809 // Arguments go on the stack in reverse order, as specified by the ABI.
810 unsigned ArgOffset = 0;
811 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
812 X86::ESP, MVT::i32);
813 NumIntRegs = 0;
814 std::vector Stores;
815 std::vector RegValuesToPass;
816 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
817 switch (getValueType(Args[i].second)) {
818 default: assert(0 && "Unexpected ValueType for argument!");
819 case MVT::i1:
820 case MVT::i8:
821 case MVT::i16:
822 case MVT::i32:
823 if (NumIntRegs < 2) {
824 RegValuesToPass.push_back(Args[i].first);
825 ++NumIntRegs;
826 break;
827 }
828 // Fall through
829 case MVT::f32: {
830 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
831 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
832 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
833 Args[i].first, PtrOff,
834 DAG.getSrcValue(NULL)));
835 ArgOffset += 4;
836 break;
837 }
838 case MVT::i64:
839 if (NumIntRegs < 2) { // Can pass part of it in regs?
840 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
841 Args[i].first, DAG.getConstant(1, MVT::i32));
842 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
843 Args[i].first, DAG.getConstant(0, MVT::i32));
844 RegValuesToPass.push_back(Lo);
845 ++NumIntRegs;
846 if (NumIntRegs < 2) { // Pass both parts in regs?
847 RegValuesToPass.push_back(Hi);
848 ++NumIntRegs;
849 } else {
850 // Pass the high part in memory.
851 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
852 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
853 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
854 Hi, PtrOff, DAG.getSrcValue(NULL)));
855 ArgOffset += 4;
856 }
857 break;
858 }
859 // Fall through
860 case MVT::f64:
861 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
862 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
863 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
864 Args[i].first, PtrOff,
865 DAG.getSrcValue(NULL)));
866 ArgOffset += 8;
867 break;
868 }
869 }
870 if (!Stores.empty())
871 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
872
873 // Make sure the instruction takes 8n+4 bytes to make sure the start of the
874 // arguments and the arguments after the retaddr has been pushed are aligned.
875 if ((ArgOffset & 7) == 0)
876 ArgOffset += 4;
877
878 std::vector RetVals;
879 MVT::ValueType RetTyVT = getValueType(RetTy);
880
881 RetVals.push_back(MVT::Other);
882
883 // The result values produced have to be legal. Promote the result.
884 switch (RetTyVT) {
885 case MVT::isVoid: break;
886 default:
887 RetVals.push_back(RetTyVT);
888 break;
889 case MVT::i1:
890 case MVT::i8:
891 case MVT::i16:
892 RetVals.push_back(MVT::i32);
893 break;
894 case MVT::f32:
895 if (X86ScalarSSE)
896 RetVals.push_back(MVT::f32);
897 else
898 RetVals.push_back(MVT::f64);
899 break;
900 case MVT::i64:
901 RetVals.push_back(MVT::i32);
902 RetVals.push_back(MVT::i32);
903 break;
904 }
905
906 std::vector Ops;
907 Ops.push_back(Chain);
908 Ops.push_back(Callee);
909 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
910 // Callee pops all arg values on the stack.
911 Ops.push_back(DAG.getConstant(ArgOffset, getPointerTy()));
912
913 // Pass register arguments as needed.
914 Ops.insert(Ops.end(), RegValuesToPass.begin(), RegValuesToPass.end());
915
916 SDOperand TheCall = DAG.getNode(isTailCall ? X86ISD::TAILCALL : X86ISD::CALL,
917 RetVals, Ops);
918 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, TheCall);
919
920 SDOperand ResultVal;
921 switch (RetTyVT) {
922 case MVT::isVoid: break;
923 default:
924 ResultVal = TheCall.getValue(1);
925 break;
926 case MVT::i1:
927 case MVT::i8:
928 case MVT::i16:
929 ResultVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, TheCall.getValue(1));
930 break;
931 case MVT::f32:
932 // FIXME: we would really like to remember that this FP_ROUND operation is
933 // okay to eliminate if we allow excess FP precision.
934 ResultVal = DAG.getNode(ISD::FP_ROUND, MVT::f32, TheCall.getValue(1));
935 break;
936 case MVT::i64:
937 ResultVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, TheCall.getValue(1),
938 TheCall.getValue(2));
939 break;
940 }
941
942 return std::make_pair(ResultVal, Chain);
943 }
944
945 SDOperand X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) {
946 if (ReturnAddrIndex == 0) {
947 // Set up a frame object for the return address.
948 MachineFunction &MF = DAG.getMachineFunction();
949 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(4, -4);
950 }
951
952 return DAG.getFrameIndex(ReturnAddrIndex, MVT::i32);
953 }
954
955
956
957 std::pair X86TargetLowering::
958 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
959 SelectionDAG &DAG) {
960 SDOperand Result;
961 if (Depth) // Depths > 0 not supported yet!
962 Result = DAG.getConstant(0, getPointerTy());
963 else {
964 SDOperand RetAddrFI = getReturnAddressFrameIndex(DAG);
965 if (!isFrameAddress)
966 // Just load the return address
967 Result = DAG.getLoad(MVT::i32, DAG.getEntryNode(), RetAddrFI,
968 DAG.getSrcValue(NULL));
969 else
970 Result = DAG.getNode(ISD::SUB, MVT::i32, RetAddrFI,
971 DAG.getConstant(4, MVT::i32));
972 }
973 return std::make_pair(Result, Chain);
974 }
975
976 //===----------------------------------------------------------------------===//
977 // X86 Custom Lowering Hooks
978 //===----------------------------------------------------------------------===//
979
980 /// LowerOperation - Provide custom lowering hooks for some operations.
981 ///
982 SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
983 switch (Op.getOpcode()) {
984 default: assert(0 && "Should not custom lower this!");
985 case ISD::SINT_TO_FP: {
986 assert(Op.getValueType() == MVT::f64 &&
987 Op.getOperand(0).getValueType() == MVT::i64 &&
988 "Unknown SINT_TO_FP to lower!");
989 // We lower sint64->FP into a store to a temporary stack slot, followed by a
990 // FILD64m node.
991 MachineFunction &MF = DAG.getMachineFunction();
992 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
993 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
994 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
995 Op.getOperand(0), StackSlot, DAG.getSrcValue(NULL));
996 std::vector RTs;
997 RTs.push_back(MVT::f64);
998 RTs.push_back(MVT::Other);
999 std::vector Ops;
1000 Ops.push_back(Store);
1001 Ops.push_back(StackSlot);
1002 return DAG.getNode(X86ISD::FILD64m, RTs, Ops);
1003 }
1004 case ISD::FP_TO_SINT: {
1005 assert(Op.getValueType() <= MVT::i64 && Op.getValueType() >= MVT::i16 &&
1006 Op.getOperand(0).getValueType() == MVT::f64 &&
1007 "Unknown FP_TO_SINT to lower!");
1008 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary
1009 // stack slot.
1010 MachineFunction &MF = DAG.getMachineFunction();
1011 unsigned MemSize = MVT::getSizeInBits(Op.getValueType())/8;
1012 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize);
1013 SDOperand StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
1014
1015 unsigned Opc;
1016 switch (Op.getValueType()) {
1017 default: assert(0 && "Invalid FP_TO_SINT to lower!");
1018 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break;
1019 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break;
1020 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break;
1021 }
1022
1023 // Build the FP_TO_INT*_IN_MEM
1024 std::vector Ops;
1025 Ops.push_back(DAG.getEntryNode());
1026 Ops.push_back(Op.getOperand(0));
1027 Ops.push_back(StackSlot);
1028 SDOperand FIST = DAG.getNode(Opc, MVT::Other, Ops);
1029
1030 // Load the result.
1031 return DAG.getLoad(Op.getValueType(), FIST, StackSlot,
1032 DAG.getSrcValue(NULL));
1033 }
1034 }
1035 }
1036
103738
103839 //===----------------------------------------------------------------------===//
103940 // Pattern Matcher Implementation
46343635 }
46353636
46363637
4637 /// createX86PatternInstructionSelector - This pass converts an LLVM function
3638 /// createX86ISelPattern - This pass converts an LLVM function
46383639 /// into a machine code representation using pattern matching and a machine
46393640 /// description file.
46403641 ///
4641 FunctionPass *llvm::createX86PatternInstructionSelector(TargetMachine &TM) {
3642 FunctionPass *llvm::createX86ISelPattern(TargetMachine &TM) {
46423643 return new ISel(TM);
46433644 }
123123 PM.add(createUnreachableBlockEliminationPass());
124124
125125 // Install an instruction selector.
126 PM.add(createX86PatternInstructionSelector(*this));
126 PM.add(createX86ISelPattern(*this));
127127
128128 // Run optional SSA-based machine code optimizations next...
129129 if (!NoSSAPeephole)
191191 PM.add(createUnreachableBlockEliminationPass());
192192
193193 // Install an instruction selector.
194 PM.add(createX86PatternInstructionSelector(TM));
194 PM.add(createX86ISelPattern(TM));
195195
196196 // Run optional SSA-based machine code optimizations next...
197197 if (!NoSSAPeephole)