llvm.org GIT mirror llvm / db9fa46
[x86] Allow segment and address-size overrides for LODS[BWLQ] (PR9385) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199803 91177308-0d34-0410-b5e6-96231b3b80d8 David Woodhouse 6 years ago
17 changed file(s) with 280 addition(s) and 45 deletion(s). Raw diff Collapse all Expand all
550550 return 0;
551551 }
552552
553 X86Operand *DefaultMemSIOperand(SMLoc Loc);
553554 X86Operand *ParseOperand();
554555 X86Operand *ParseATTOperand();
555556 X86Operand *ParseIntelOperand();
919920 bool isAbsMem() const {
920921 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
921922 !getMemIndexReg() && getMemScale() == 1;
923 }
924
925 bool isSrcIdx() const {
926 return !getMemIndexReg() && getMemScale() == 1 &&
927 (getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
928 getMemBaseReg() == X86::SI) && isa(getMemDisp()) &&
929 cast(getMemDisp())->getValue() == 0;
930 }
931 bool isSrcIdx8() const {
932 return isMem8() && isSrcIdx();
933 }
934 bool isSrcIdx16() const {
935 return isMem16() && isSrcIdx();
936 }
937 bool isSrcIdx32() const {
938 return isMem32() && isSrcIdx();
939 }
940 bool isSrcIdx64() const {
941 return isMem64() && isSrcIdx();
922942 }
923943
924944 bool isMemOffs8() const {
10131033 Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
10141034 }
10151035
1036 void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
1037 assert((N == 2) && "Invalid number of operands!");
1038 Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
1039 Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
1040 }
1041
10161042 void addMemOffsOperands(MCInst &Inst, unsigned N) const {
10171043 assert((N == 2) && "Invalid number of operands!");
10181044 // Add as immediates when possible.
12271253
12281254 Parser.Lex(); // Eat identifier token.
12291255 return false;
1256 }
1257
1258 X86Operand *X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
1259 unsigned basereg =
1260 is64BitMode() ? X86::RSI : (is32BitMode() ? X86::ESI : X86::SI);
1261 const MCExpr *Disp = MCConstantExpr::Create(0, getContext());
1262 return X86Operand::CreateMem(/*SegReg=*/0, Disp, /*BaseReg=*/basereg,
1263 /*IndexReg=*/0, /*Scale=*/1, Loc, Loc, 0);
12301264 }
12311265
12321266 X86Operand *X86AsmParser::ParseOperand() {
22772311 delete &Op2;
22782312 }
22792313 }
2280 // Transform "lods[bwl] %ds:(%esi),{%al,%ax,%eax,%rax}" into "lods[bwl]"
2281 if (Name.startswith("lods") && Operands.size() == 3 &&
2314 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2315 // values of $SIREG according to the mode. It would be nice if this
2316 // could be achieved with InstAlias in the tables.
2317 if (Name.startswith("lods") && Operands.size() == 1 &&
22822318 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
2283 Name == "lodsl" || (is64BitMode() && Name == "lodsq"))) {
2284 X86Operand *Op1 = static_cast(Operands[1]);
2285 X86Operand *Op2 = static_cast(Operands[2]);
2286 if (isSrcOp(*Op1) && Op2->isReg()) {
2287 const char *ins;
2288 unsigned reg = Op2->getReg();
2289 bool isLods = Name == "lods";
2290 if (reg == X86::AL && (isLods || Name == "lodsb"))
2291 ins = "lodsb";
2292 else if (reg == X86::AX && (isLods || Name == "lodsw"))
2293 ins = "lodsw";
2294 else if (reg == X86::EAX && (isLods || Name == "lodsl"))
2295 ins = "lodsl";
2296 else if (reg == X86::RAX && (isLods || Name == "lodsq"))
2297 ins = "lodsq";
2298 else
2299 ins = NULL;
2300 if (ins != NULL) {
2301 Operands.pop_back();
2302 Operands.pop_back();
2303 delete Op1;
2304 delete Op2;
2305 if (Name != ins)
2306 static_cast(Operands[0])->setTokenValue(ins);
2307 }
2308 }
2309 }
2319 Name == "lodsl" || Name == "lodsd" || Name == "lodsq"))
2320 Operands.push_back(DefaultMemSIOperand(NameLoc));
2321
23102322 // Transform "stos[bwl] {%al,%ax,%eax,%rax},%es:(%edi)" into "stos[bwl]"
23112323 if (Name.startswith("stos") && Operands.size() == 3 &&
23122324 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
231231 X86::FS,
232232 X86::GS
233233 };
234
235 /// translateSrcIndex - Appends a source index operand to an MCInst.
236 ///
237 /// @param mcInst - The MCInst to append to.
238 /// @param operand - The operand, as stored in the descriptor table.
239 /// @param insn - The internal instruction.
240 static bool translateSrcIndex(MCInst &mcInst, InternalInstruction &insn) {
241 unsigned baseRegNo;
242
243 if (insn.mode == MODE_64BIT)
244 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::RSI;
245 else if (insn.mode == MODE_32BIT)
246 baseRegNo = insn.prefixPresent[0x67] ? X86::SI : X86::ESI;
247 else if (insn.mode == MODE_16BIT)
248 baseRegNo = insn.prefixPresent[0x67] ? X86::ESI : X86::SI;
249 MCOperand baseReg = MCOperand::CreateReg(baseRegNo);
250 mcInst.addOperand(baseReg);
251
252 MCOperand segmentReg;
253 segmentReg = MCOperand::CreateReg(segmentRegnums[insn.segmentOverride]);
254 mcInst.addOperand(segmentReg);
255 return false;
256 }
234257
235258 /// translateImmediate - Appends an immediate operand to an MCInst.
236259 ///
693716 insn,
694717 Dis);
695718 return false;
719 case ENCODING_SI:
720 return translateSrcIndex(mcInst, insn);
696721 case ENCODING_RB:
697722 case ENCODING_RW:
698723 case ENCODING_RD:
16811681 for (index = 0; index < X86_MAX_OPERANDS; ++index) {
16821682 switch (x86OperandSets[insn->spec->operands][index].encoding) {
16831683 case ENCODING_NONE:
1684 case ENCODING_SI:
16841685 break;
16851686 case ENCODING_REG:
16861687 case ENCODING_RM:
408408 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
409409 "opcode byte") \
410410 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
411 "in type")
411 "in type") \
412 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix")
412413
413414 #define ENUM_ENTRY(n, d) n,
414415 typedef enum {
459460 ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \
460461 ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \
461462 ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \
463 ENUM_ENTRY(TYPE_SRCIDX8, "1-byte memory at source index") \
464 ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \
465 ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \
466 ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \
462467 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \
463468 "base)") \
464469 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \
225225 O << markup(">");
226226 }
227227
228 void X86ATTInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
229 raw_ostream &O) {
230 const MCOperand &SegReg = MI->getOperand(Op+1);
231
232 O << markup("
233
234 // If this has a segment register, print it.
235 if (SegReg.getReg()) {
236 printOperand(MI, Op+1, O);
237 O << ':';
238 }
239
240 O << "(";
241 printOperand(MI, Op, O);
242 O << ")";
243
244 O << markup(">");
245 }
246
228247 void X86ATTInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
229248 raw_ostream &O) {
230249 const MCOperand &DispSpec = MI->getOperand(Op);
4141 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
4242 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &OS);
4343 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
44 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
4445 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
4546 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
4647
8889 printMemReference(MI, OpNo, O);
8990 }
9091
92 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
93 printSrcIdx(MI, OpNo, O);
94 }
95 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
96 printSrcIdx(MI, OpNo, O);
97 }
98 void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
99 printSrcIdx(MI, OpNo, O);
100 }
101 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
102 printSrcIdx(MI, OpNo, O);
103 }
91104 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
92105 printMemOffset(MI, OpNo, O);
93106 }
211211 O << ']';
212212 }
213213
214 void X86IntelInstPrinter::printSrcIdx(const MCInst *MI, unsigned Op,
215 raw_ostream &O) {
216 const MCOperand &SegReg = MI->getOperand(Op+1);
217
218 // If this has a segment register, print it.
219 if (SegReg.getReg()) {
220 printOperand(MI, Op+1, O);
221 O << ':';
222 }
223 O << '[';
224 printOperand(MI, Op, O);
225 O << ']';
226 }
227
214228 void X86IntelInstPrinter::printMemOffset(const MCInst *MI, unsigned Op,
215229 raw_ostream &O) {
216230 const MCOperand &DispSpec = MI->getOperand(Op);
3939 void printAVXCC(const MCInst *MI, unsigned Op, raw_ostream &O);
4040 void printPCRelImm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4141 void printMemOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printSrcIdx(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4243 void printRoundingControl(const MCInst *MI, unsigned Op, raw_ostream &OS);
4344
4445 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
99100 printMemReference(MI, OpNo, O);
100101 }
101102
103
104 void printSrcIdx8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
105 O << "byte ptr ";
106 printSrcIdx(MI, OpNo, O);
107 }
108 void printSrcIdx16(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
109 O << "word ptr ";
110 printSrcIdx(MI, OpNo, O);
111 }
112 void printSrcIdx32(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
113 O << "dword ptr ";
114 printSrcIdx(MI, OpNo, O);
115 }
116 void printSrcIdx64(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
117 O << "qword ptr ";
118 printSrcIdx(MI, OpNo, O);
119 }
102120 void printMemOffs8(const MCInst *MI, unsigned OpNo, raw_ostream &O) {
103121 O << "byte ptr ";
104122 printMemOffset(MI, OpNo, O);
257257 /// RawFrmMemOffs - This form is for instructions that store an absolute
258258 /// memory offset as an immediate with a possible segment override.
259259 RawFrmMemOffs = 7,
260
261 /// RawFrmSrc - This form is for instructions that use the source index
262 /// register SI/ESI/RSI with a possible segment override.
263 RawFrmSrc = 8,
260264
261265 /// MRM[0-7][rm] - These forms are used to represent instructions that use
262266 /// a Mod/RM byte, and use the middle field to hold extended opcode
611615 case X86II::RawFrmImm8:
612616 case X86II::RawFrmImm16:
613617 case X86II::RawFrmMemOffs:
618 case X86II::RawFrmSrc:
614619 return -1;
615620 case X86II::MRMDestMem:
616621 return 0;
13161316 llvm_unreachable("Unknown FormMask value in X86MCCodeEmitter!");
13171317 case X86II::Pseudo:
13181318 llvm_unreachable("Pseudo instruction shouldn't be emitted");
1319 case X86II::RawFrmSrc: {
1320 unsigned siReg = MI.getOperand(0).getReg();
1321 // Emit segment override opcode prefix as needed (not for %ds).
1322 if (MI.getOperand(1).getReg() != X86::DS)
1323 EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
1324 // Emit OpSize prefix as needed.
1325 if ((!is32BitMode() && siReg == X86::ESI) ||
1326 (is32BitMode() && siReg == X86::SI))
1327 EmitByte(0x67, CurByte, OS);
1328 CurOp += 2; // Consume operands.
1329 EmitByte(BaseOpcode, CurByte, OS);
1330 break;
1331 }
13191332 case X86II::RawFrm:
13201333 EmitByte(BaseOpcode, CurByte, OS);
13211334 break;
2121 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
2222 def MRMDestMem : Format<4>; def MRMSrcReg : Format<5>;
2323 def MRMSrcMem : Format<6>; def RawFrmMemOffs : Format<7>;
24 def RawFrmSrc : Format<8>;
2425 def MRM0r : Format<16>; def MRM1r : Format<17>; def MRM2r : Format<18>;
2526 def MRM3r : Format<19>; def MRM4r : Format<20>; def MRM5r : Format<21>;
2627 def MRM6r : Format<22>; def MRM7r : Format<23>;
444444
445445 }
446446
447 def X86SrcIdx8Operand : AsmOperandClass {
448 let Name = "SrcIdx8";
449 let RenderMethod = "addSrcIdxOperands";
450 let SuperClasses = [X86Mem8AsmOperand];
451 }
452 def X86SrcIdx16Operand : AsmOperandClass {
453 let Name = "SrcIdx16";
454 let RenderMethod = "addSrcIdxOperands";
455 let SuperClasses = [X86Mem16AsmOperand];
456 }
457 def X86SrcIdx32Operand : AsmOperandClass {
458 let Name = "SrcIdx32";
459 let RenderMethod = "addSrcIdxOperands";
460 let SuperClasses = [X86Mem32AsmOperand];
461 }
462 def X86SrcIdx64Operand : AsmOperandClass {
463 let Name = "SrcIdx64";
464 let RenderMethod = "addSrcIdxOperands";
465 let SuperClasses = [X86Mem64AsmOperand];
466 }
447467 def X86MemOffs8AsmOperand : AsmOperandClass {
448468 let Name = "MemOffs8";
449469 let RenderMethod = "addMemOffsOperands";
464484 let RenderMethod = "addMemOffsOperands";
465485 let SuperClasses = [X86Mem64AsmOperand];
466486 }
467
468487 let OperandType = "OPERAND_MEMORY" in {
488 def srcidx8 : Operand {
489 let ParserMatchClass = X86SrcIdx8Operand;
490 let MIOperandInfo = (ops ptr_rc, i8imm);
491 let PrintMethod = "printSrcIdx8"; }
492 def srcidx16 : Operand {
493 let ParserMatchClass = X86SrcIdx16Operand;
494 let MIOperandInfo = (ops ptr_rc, i8imm);
495 let PrintMethod = "printSrcIdx16"; }
496 def srcidx32 : Operand {
497 let ParserMatchClass = X86SrcIdx32Operand;
498 let MIOperandInfo = (ops ptr_rc, i8imm);
499 let PrintMethod = "printSrcIdx32"; }
500 def srcidx64 : Operand {
501 let ParserMatchClass = X86SrcIdx64Operand;
502 let MIOperandInfo = (ops ptr_rc, i8imm);
503 let PrintMethod = "printSrcIdx64"; }
469504 def offset8 : Operand {
470505 let ParserMatchClass = X86MemOffs8AsmOperand;
471506 let MIOperandInfo = (ops i64imm, i8imm);
16751710
16761711 // String manipulation instructions
16771712 let SchedRW = [WriteMicrocoded] in {
1678 def LODSB : I<0xAC, RawFrm, (outs), (ins), "lodsb", [], IIC_LODS>;
1679 def LODSW : I<0xAD, RawFrm, (outs), (ins), "lodsw", [], IIC_LODS>, OpSize;
1680 def LODSL : I<0xAD, RawFrm, (outs), (ins), "lods{l|d}", [], IIC_LODS>, OpSize16;
1681 def LODSQ : RI<0xAD, RawFrm, (outs), (ins), "lodsq", [], IIC_LODS>;
1713 def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
1714 "lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
1715 def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
1716 "lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize;
1717 def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
1718 "lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize16;
1719 def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
1720 "lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
16821721 }
16831722
16841723 let SchedRW = [WriteSystem] in {
23282367 def : InstAlias<"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg), 0>;
23292368 def : InstAlias<"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg), 0>;
23302369
2370 // lods aliases. Accept the destination being omitted because it's implicit
2371 // in the mnemonic, or the mnemonic suffix being omitted because it's implicit
2372 // in the destination.
2373 def : InstAlias<"lodsb $src", (LODSB srcidx8:$src), 0>;
2374 def : InstAlias<"lodsw $src", (LODSW srcidx16:$src), 0>;
2375 def : InstAlias<"lods{l|d} $src", (LODSL srcidx32:$src), 0>;
2376 def : InstAlias<"lodsq $src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2377 def : InstAlias<"lods {$src, %al|al, $src}", (LODSB srcidx8:$src), 0>;
2378 def : InstAlias<"lods {$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>;
2379 def : InstAlias<"lods {$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>;
2380 def : InstAlias<"lods {$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>;
2381
23312382 // div and idiv aliases for explicit A register.
23322383 def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>;
23332384 def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>;
0 // RUN: not llvm-mc -triple x86_64-unknown-unknown --show-encoding %s 2> %t.err | FileCheck --check-prefix=64 %s
1 // RUN: FileCheck --check-prefix=ERR64 < %t.err %s
2 // RUN: not llvm-mc -triple i386-unknown-unknown --show-encoding %s 2> %t.err | FileCheck --check-prefix=32 %s
3 // RUN: FileCheck --check-prefix=ERR32 < %t.err %s
4 // RUN: not llvm-mc -triple i386-unknown-unknown-code16 --show-encoding %s 2> %t.err | FileCheck --check-prefix=16 %s
5 // RUN: FileCheck --check-prefix=ERR16 < %t.err %s
6
7 lodsb
8 // 64: lodsb (%rsi), %al # encoding: [0xac]
9 // 32: lodsb (%esi), %al # encoding: [0xac]
10 // 16: lodsb (%si), %al # encoding: [0xac]
11
12 lodsb (%rsi), %al
13 // 64: lodsb (%rsi), %al # encoding: [0xac]
14 // ERR32: 64-bit
15 // ERR16: 64-bit
16
17 lodsb (%esi), %al
18 // 64: lodsb (%esi), %al # encoding: [0x67,0xac]
19 // 32: lodsb (%esi), %al # encoding: [0xac]
20 // 16: lodsb (%esi), %al # encoding: [0x67,0xac]
21
22 lodsb (%si), %al
23 // ERR64: invalid 16-bit base register
24 // 32: lodsb (%si), %al # encoding: [0x67,0xac]
25 // 16: lodsb (%si), %al # encoding: [0xac]
26
27 lodsl %gs:(%esi)
28 // 64: lodsl %gs:(%esi), %eax # encoding: [0x65,0x67,0xad]
29 // 32: lodsl %gs:(%esi), %eax # encoding: [0x65,0xad]
30 // 16: lodsl %gs:(%esi), %eax # encoding: [0x66,0x65,0x67,0xad]
31
32 lodsl (%edi), %eax
33 // ERR64: invalid operand
34 // ERR32: invalid operand
35 // ERR16: invalid operand
36
37 lodsl 44(%edi), %eax
38 // ERR64: invalid operand
39 // ERR32: invalid operand
40 // ERR16: invalid operand
41
42 lods (%esi), %ax
43 // 64: lodsw (%esi), %ax # encoding: [0x66,0x67,0xad]
44 // 32: lodsw (%esi), %ax # encoding: [0x66,0xad]
45 // 16: lodsw (%esi), %ax # encoding: [0x67,0xad]
844844 movsl %ds:(%si), %es:(%di)
845845 movsl (%si), %es:(%di)
846846
847 // CHECK: lodsb # encoding: [0xac]
847 // CHECK: lodsb (%si), %al # encoding: [0xac]
848848 // CHECK: lodsb
849849 // CHECK: lodsb
850850 // CHECK: lodsb
855855 lods %ds:(%si), %al
856856 lods (%si), %al
857857
858 // CHECK: lodsw # encoding: [0xad]
858 // CHECK: lodsw (%si), %ax # encoding: [0xad]
859859 // CHECK: lodsw
860860 // CHECK: lodsw
861861 // CHECK: lodsw
866866 lods %ds:(%si), %ax
867867 lods (%si), %ax
868868
869 // CHECK: lodsl # encoding: [0x66,0xad]
869 // CHECK: lodsl (%si), %eax # encoding: [0x66,0xad]
870870 // CHECK: lodsl
871871 // CHECK: lodsl
872872 // CHECK: lodsl
920920 movsl %ds:(%esi), %es:(%edi)
921921 movsl (%esi), %es:(%edi)
922922
923 // CHECK: lodsb # encoding: [0xac]
923 // CHECK: lodsb (%esi), %al # encoding: [0xac]
924924 // CHECK: lodsb
925925 // CHECK: lodsb
926926 // CHECK: lodsb
931931 lods %ds:(%esi), %al
932932 lods (%esi), %al
933933
934 // CHECK: lodsw # encoding: [0x66,0xad]
934 // CHECK: lodsw (%esi), %ax # encoding: [0x66,0xad]
935935 // CHECK: lodsw
936936 // CHECK: lodsw
937937 // CHECK: lodsw
942942 lods %ds:(%esi), %ax
943943 lods (%esi), %ax
944944
945 // CHECK: lodsl # encoding: [0xad]
945 // CHECK: lodsl (%esi), %eax # encoding: [0xad]
946946 // CHECK: lodsl
947947 // CHECK: lodsl
948948 // CHECK: lodsl
11151115 movsq %ds:(%rsi), %es:(%rdi)
11161116 movsq (%rsi), %es:(%rdi)
11171117
1118 // CHECK: lodsb # encoding: [0xac]
1118 // CHECK: lodsb (%rsi), %al # encoding: [0xac]
11191119 // CHECK: lodsb
11201120 // CHECK: lodsb
11211121 // CHECK: lodsb
11261126 lods %ds:(%rsi), %al
11271127 lods (%rsi), %al
11281128
1129 // CHECK: lodsw # encoding: [0x66,0xad]
1129 // CHECK: lodsw (%rsi), %ax # encoding: [0x66,0xad]
11301130 // CHECK: lodsw
11311131 // CHECK: lodsw
11321132 // CHECK: lodsw
11371137 lods %ds:(%rsi), %ax
11381138 lods (%rsi), %ax
11391139
1140 // CHECK: lodsl # encoding: [0xad]
1140 // CHECK: lodsl (%rsi), %eax # encoding: [0xad]
11411141 // CHECK: lodsl
11421142 // CHECK: lodsl
11431143 // CHECK: lodsl
11481148 lods %ds:(%rsi), %eax
11491149 lods (%rsi), %eax
11501150
1151 // CHECK: lodsq # encoding: [0x48,0xad]
1151 // CHECK: lodsq (%rsi), %rax # encoding: [0x48,0xad]
11521152 // CHECK: lodsq
11531153 // CHECK: lodsq
11541154 // CHECK: lodsq
5959 MRMSrcReg = 5,
6060 MRMSrcMem = 6,
6161 RawFrmMemOffs = 7,
62 RawFrmSrc = 8,
6263 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
6364 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
6465 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
629630
630631 switch (Form) {
631632 default: llvm_unreachable("Unhandled form");
633 case X86Local::RawFrmSrc:
634 HANDLE_OPERAND(relocation);
635 return;
632636 case X86Local::RawFrm:
633637 // Operand 1 (optional) is an address or immediate.
634638 // Operand 2 (optional) is an immediate.
12611265 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
12621266 TYPE("DEBUG_REG", TYPE_DEBUGREG)
12631267 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1268 TYPE("srcidx8", TYPE_SRCIDX8)
1269 TYPE("srcidx16", TYPE_SRCIDX16)
1270 TYPE("srcidx32", TYPE_SRCIDX32)
1271 TYPE("srcidx64", TYPE_SRCIDX64)
12641272 TYPE("offset8", TYPE_MOFFS8)
12651273 TYPE("offset16", TYPE_MOFFS16)
12661274 TYPE("offset32", TYPE_MOFFS32)
14731481 ENCODING("offset16", ENCODING_Ia)
14741482 ENCODING("offset32", ENCODING_Ia)
14751483 ENCODING("offset64", ENCODING_Ia)
1484 ENCODING("srcidx8", ENCODING_SI)
1485 ENCODING("srcidx16", ENCODING_SI)
1486 ENCODING("srcidx32", ENCODING_SI)
1487 ENCODING("srcidx64", ENCODING_SI)
14761488 errs() << "Unhandled relocation encoding " << s << "\n";
14771489 llvm_unreachable("Unhandled relocation encoding");
14781490 }