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MachineFunction: Introduce NoPHIs property I want to compute the SSA property of .mir files automatically in upcoming patches. The problem with this is that some inputs will be reported as static single assignment with some passes claiming not to support SSA form. In reality though those passes do not support PHI instructions => Track the presence of PHI instructions separate from the SSA property. Differential Revision: https://reviews.llvm.org/D22719 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279573 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 4 years ago
10 changed file(s) with 52 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
9191 // Property descriptions:
9292 // IsSSA: True when the machine function is in SSA form and virtual registers
9393 // have a single def.
94 // NoPHIs: The machine function does not contain any PHI instruction.
9495 // TracksLiveness: True when tracking register liveness accurately.
9596 // While this property is set, register liveness information in basic block
9697 // live-in lists and machine instruction operands (e.g. kill flags, implicit
116117 // all sizes attached to them have been eliminated.
117118 enum class Property : unsigned {
118119 IsSSA,
120 NoPHIs,
119121 TracksLiveness,
120122 AllVRegsAllocated,
121123 Legalized,
159159 ///
160160 /// Return null if the name isn't a register bank.
161161 const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);
162
163 void computeFunctionProperties(MachineFunction &MF);
162164 };
163165
164166 } // end namespace llvm
276278 Name, FunctionType::get(Type::getVoidTy(Context), false)));
277279 BasicBlock *BB = BasicBlock::Create(Context, "entry", F);
278280 new UnreachableInst(Context, BB);
281 }
282
283 static bool hasPHI(const MachineFunction &MF) {
284 for (const MachineBasicBlock &MBB : MF)
285 for (const MachineInstr &MI : MBB)
286 if (MI.isPHI())
287 return true;
288 return false;
289 }
290
291 void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
292 if (!hasPHI(MF))
293 MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
279294 }
280295
281296 bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
352367 PFS.SM = &SM;
353368
354369 inferRegisterInfo(PFS, YamlMF);
370
371 computeFunctionProperties(MF);
372
355373 // FIXME: This is a temporary workaround until the reserved registers can be
356374 // serialized.
357375 MF.getRegInfo().freezeReservedRegs(MF);
5959 case P::AllVRegsAllocated: return "AllVRegsAllocated";
6060 case P::IsSSA: return "IsSSA";
6161 case P::Legalized: return "Legalized";
62 case P::NoPHIs: return "NoPHIs";
6263 case P::RegBankSelected: return "RegBankSelected";
6364 case P::Selected: return "Selected";
6465 case P::TracksLiveness: return "TracksLiveness";
856856 errs() << MCID.getNumOperands() << " operands expected, but "
857857 << MI->getNumOperands() << " given.\n";
858858 }
859
860 if (MI->isPHI() && MF->getProperties().hasProperty(
861 MachineFunctionProperties::Property::NoPHIs))
862 report("Found PHI instruction with NoPHIs property set", MI);
859863
860864 // Check the tied operands.
861865 if (MI->isInlineAsm())
173173 LoweredPHIs.clear();
174174 ImpDefs.clear();
175175 VRegPHIUseCount.clear();
176
177 MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
176178
177179 return Changed;
178180 }
104104 /// Perform register allocation.
105105 bool runOnMachineFunction(MachineFunction &mf) override;
106106
107 MachineFunctionProperties getRequiredProperties() const override {
108 return MachineFunctionProperties().set(
109 MachineFunctionProperties::Property::NoPHIs);
110 }
111
107112 // Helper for spilling all live virtual registers currently unified under preg
108113 // that interfere with the most recently queried lvr. Return true if spilling
109114 // was successful, and append any new spilled/split intervals to splitLVRs.
155155 void getAnalysisUsage(AnalysisUsage &AU) const override {
156156 AU.setPreservesCFG();
157157 MachineFunctionPass::getAnalysisUsage(AU);
158 }
159
160 MachineFunctionProperties getRequiredProperties() const override {
161 return MachineFunctionProperties().set(
162 MachineFunctionProperties::Property::NoPHIs);
158163 }
159164
160165 MachineFunctionProperties getSetProperties() const override {
10921097 UsedInInstr.clear();
10931098 UsedInInstr.setUniverse(TRI->getNumRegUnits());
10941099
1095 assert(!MRI->isSSA() && "regalloc requires leaving SSA");
1096
10971100 // initialize the virtual->physical register map to have a 'null'
10981101 // mapping for all virtual registers
10991102 StackSlotForVirtReg.resize(MRI->getNumVirtRegs());
332332
333333 /// Perform register allocation.
334334 bool runOnMachineFunction(MachineFunction &mf) override;
335
336 MachineFunctionProperties getRequiredProperties() const override {
337 return MachineFunctionProperties().set(
338 MachineFunctionProperties::Property::NoPHIs);
339 }
335340
336341 static char ID;
337342
108108 /// Perform register allocation
109109 bool runOnMachineFunction(MachineFunction &MF) override;
110110
111 MachineFunctionProperties getRequiredProperties() const override {
112 return MachineFunctionProperties().set(
113 MachineFunctionProperties::Property::NoPHIs);
114 }
115
111116 private:
112117
113118 typedef std::map LI2NodeMap;
9797 return "SI Load / Store Optimizer";
9898 }
9999
100 MachineFunctionProperties getRequiredProperties() const override {
101 return MachineFunctionProperties().set(
102 MachineFunctionProperties::Property::NoPHIs);
103 }
104
100105 void getAnalysisUsage(AnalysisUsage &AU) const override {
101106 AU.setPreservesCFG();
102107 AU.addPreserved();
424429
425430 DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
426431
427 assert(!MRI->isSSA());
428
429432 bool Modified = false;
430433
431434 for (MachineBasicBlock &MBB : MF)