llvm.org GIT mirror llvm / db807ed
Use movups to spill / restore SSE registers on targets where stacks alignment is less than 16. This is a temporary solution until dynamic stack alignment is implemented. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43703 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
2 changed file(s) with 24 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
5454 // Cache some information.
5555 const X86Subtarget *Subtarget = &TM.getSubtarget();
5656 Is64Bit = Subtarget->is64Bit();
57 StackAlign = TM.getFrameInfo()->getStackAlignment();
5758 if (Is64Bit) {
5859 SlotSize = 8;
5960 StackPtr = X86::RSP;
760761 return MIB;
761762 }
762763
763 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC) {
764 static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
765 unsigned StackAlign) {
764766 unsigned Opc = 0;
765767 if (RC == &X86::GR64RegClass) {
766768 Opc = X86::MOV64mr;
785787 } else if (RC == &X86::FR64RegClass) {
786788 Opc = X86::MOVSDmr;
787789 } else if (RC == &X86::VR128RegClass) {
788 Opc = X86::MOVAPSmr;
790 // FIXME: Use movaps once we are capable of selectively
791 // aligning functions that spill SSE registers on 16-byte boundaries.
792 Opc = StackAlign >= 16 ? X86::MOVAPSmr : X86::MOVUPSmr;
789793 } else if (RC == &X86::VR64RegClass) {
790794 Opc = X86::MMX_MOVQ64mr;
791795 } else {
800804 MachineBasicBlock::iterator MI,
801805 unsigned SrcReg, int FrameIdx,
802806 const TargetRegisterClass *RC) const {
803 unsigned Opc = getStoreRegOpcode(RC);
807 unsigned Opc = getStoreRegOpcode(RC, StackAlign);
804808 addFrameReference(BuildMI(MBB, MI, TII.get(Opc)), FrameIdx)
805809 .addReg(SrcReg, false, false, true);
806810 }
809813 SmallVectorImpl &Addr,
810814 const TargetRegisterClass *RC,
811815 SmallVectorImpl &NewMIs) const {
812 unsigned Opc = getStoreRegOpcode(RC);
816 unsigned Opc = getStoreRegOpcode(RC, StackAlign);
813817 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
814818 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
815819 MIB = X86InstrAddOperand(MIB, Addr[i]);
817821 NewMIs.push_back(MIB);
818822 }
819823
820 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC) {
824 static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
825 unsigned StackAlign) {
821826 unsigned Opc = 0;
822827 if (RC == &X86::GR64RegClass) {
823828 Opc = X86::MOV64rm;
842847 } else if (RC == &X86::FR64RegClass) {
843848 Opc = X86::MOVSDrm;
844849 } else if (RC == &X86::VR128RegClass) {
845 Opc = X86::MOVAPSrm;
850 // FIXME: Use movaps once we are capable of selectively
851 // aligning functions that spill SSE registers on 16-byte boundaries.
852 Opc = StackAlign >= 16 ? X86::MOVAPSrm : X86::MOVUPSrm;
846853 } else if (RC == &X86::VR64RegClass) {
847854 Opc = X86::MMX_MOVQ64rm;
848855 } else {
857864 MachineBasicBlock::iterator MI,
858865 unsigned DestReg, int FrameIdx,
859866 const TargetRegisterClass *RC) const{
860 unsigned Opc = getLoadRegOpcode(RC);
867 unsigned Opc = getLoadRegOpcode(RC, StackAlign);
861868 addFrameReference(BuildMI(MBB, MI, TII.get(Opc), DestReg), FrameIdx);
862869 }
863870
865872 SmallVectorImpl &Addr,
866873 const TargetRegisterClass *RC,
867874 SmallVectorImpl &NewMIs) const {
868 unsigned Opc = getLoadRegOpcode(RC);
875 unsigned Opc = getLoadRegOpcode(RC, StackAlign);
869876 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
870877 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
871878 MIB = X86InstrAddOperand(MIB, Addr[i]);
12831290 SDNode *Load = 0;
12841291 if (FoldedLoad) {
12851292 MVT::ValueType VT = *RC->vt_begin();
1286 Load = DAG.getTargetNode(getLoadRegOpcode(RC), VT, MVT::Other,
1293 Load = DAG.getTargetNode(getLoadRegOpcode(RC, StackAlign), VT, MVT::Other,
12871294 &AddrOps[0], AddrOps.size());
12881295 NewNodes.push_back(Load);
12891296 }
13131320 AddrOps.pop_back();
13141321 AddrOps.push_back(SDOperand(NewNode, 0));
13151322 AddrOps.push_back(Chain);
1316 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC),
1323 SDNode *Store = DAG.getTargetNode(getStoreRegOpcode(DstRC, StackAlign),
13171324 MVT::Other, &AddrOps[0], AddrOps.size());
13181325 NewNodes.push_back(Store);
13191326 }
14451452 // We need to keep the stack aligned properly. To do this, we round the
14461453 // amount of space needed for the outgoing arguments up to the next
14471454 // alignment boundary.
1448 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
1449 Amount = (Amount+Align-1)/Align*Align;
1455 Amount = (Amount+StackAlign-1)/StackAlign*StackAlign;
14501456
14511457 MachineInstr *New = 0;
14521458 if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) {
16651671 void X86RegisterInfo::emitPrologue(MachineFunction &MF) const {
16661672 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
16671673 MachineFrameInfo *MFI = MF.getFrameInfo();
1668 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
16691674 const Function* Fn = MF.getFunction();
16701675 const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget();
16711676 MachineModuleInfo *MMI = MFI->getMachineModuleInfo();
18411846 if (Fn->hasExternalLinkage() && Fn->getName() == "main" &&
18421847 Subtarget->isTargetCygMing()) {
18431848 BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP)
1844 .addReg(X86::ESP).addImm(-Align);
1849 .addReg(X86::ESP).addImm(-StackAlign);
18451850
18461851 // Probe the stack
1847 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(Align);
1852 BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign);
18481853 BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca");
18491854 }
18501855 }
4444 /// SlotSize - Stack slot size in bytes.
4545 ///
4646 unsigned SlotSize;
47
48 /// StackAlign - Default stack alignment.
49 ///
50 unsigned StackAlign;
4751
4852 /// StackPtr - X86 physical register used as stack ptr.
4953 ///