llvm.org GIT mirror llvm / db703aa
MC: Modernize MCOperand API naming. NFC. MCOperand::Create*() methods renamed to MCOperand::create*(). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237275 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 5 years ago
55 changed file(s) with 1213 addition(s) and 1214 deletion(s). Raw diff Collapse all Expand all
107107 InstVal = Val;
108108 }
109109
110 static MCOperand CreateReg(unsigned Reg) {
110 static MCOperand createReg(unsigned Reg) {
111111 MCOperand Op;
112112 Op.Kind = kRegister;
113113 Op.RegVal = Reg;
114114 return Op;
115115 }
116 static MCOperand CreateImm(int64_t Val) {
116 static MCOperand createImm(int64_t Val) {
117117 MCOperand Op;
118118 Op.Kind = kImmediate;
119119 Op.ImmVal = Val;
120120 return Op;
121121 }
122 static MCOperand CreateFPImm(double Val) {
122 static MCOperand createFPImm(double Val) {
123123 MCOperand Op;
124124 Op.Kind = kFPImmediate;
125125 Op.FPImmVal = Val;
126126 return Op;
127127 }
128 static MCOperand CreateExpr(const MCExpr *Val) {
128 static MCOperand createExpr(const MCExpr *Val) {
129129 MCOperand Op;
130130 Op.Kind = kExpr;
131131 Op.ExprVal = Val;
132132 return Op;
133133 }
134 static MCOperand CreateInst(const MCInst *Val) {
134 static MCOperand createInst(const MCInst *Val) {
135135 MCOperand Op;
136136 Op.Kind = kInst;
137137 Op.InstVal = Val;
2929
3030 /// \brief Add a new register operand.
3131 MCInstBuilder &addReg(unsigned Reg) {
32 Inst.addOperand(MCOperand::CreateReg(Reg));
32 Inst.addOperand(MCOperand::createReg(Reg));
3333 return *this;
3434 }
3535
3636 /// \brief Add a new integer immediate operand.
3737 MCInstBuilder &addImm(int64_t Val) {
38 Inst.addOperand(MCOperand::CreateImm(Val));
38 Inst.addOperand(MCOperand::createImm(Val));
3939 return *this;
4040 }
4141
4242 /// \brief Add a new floating point immediate operand.
4343 MCInstBuilder &addFPImm(double Val) {
44 Inst.addOperand(MCOperand::CreateFPImm(Val));
44 Inst.addOperand(MCOperand::createFPImm(Val));
4545 return *this;
4646 }
4747
4848 /// \brief Add a new MCExpr operand.
4949 MCInstBuilder &addExpr(const MCExpr *Val) {
50 Inst.addOperand(MCOperand::CreateExpr(Val));
50 Inst.addOperand(MCOperand::createExpr(Val));
5151 return *this;
5252 }
5353
5454 /// \brief Add a new MCInst operand.
5555 MCInstBuilder &addInst(const MCInst *Val) {
56 Inst.addOperand(MCOperand::CreateInst(Val));
56 Inst.addOperand(MCOperand::createInst(Val));
5757 return *this;
5858 }
5959
135135 if (!Expr)
136136 return false;
137137
138 MI.addOperand(MCOperand::CreateExpr(Expr));
138 MI.addOperand(MCOperand::createExpr(Expr));
139139 return true;
140140 }
141141
466466 case AArch64::TCRETURNri: {
467467 MCInst TmpInst;
468468 TmpInst.setOpcode(AArch64::BR);
469 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
469 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
470470 EmitToStreamer(*OutStreamer, TmpInst);
471471 return;
472472 }
499499
500500 MCInst Adrp;
501501 Adrp.setOpcode(AArch64::ADRP);
502 Adrp.addOperand(MCOperand::CreateReg(AArch64::X0));
502 Adrp.addOperand(MCOperand::createReg(AArch64::X0));
503503 Adrp.addOperand(SymTLSDesc);
504504 EmitToStreamer(*OutStreamer, Adrp);
505505
506506 MCInst Ldr;
507507 Ldr.setOpcode(AArch64::LDRXui);
508 Ldr.addOperand(MCOperand::CreateReg(AArch64::X1));
509 Ldr.addOperand(MCOperand::CreateReg(AArch64::X0));
508 Ldr.addOperand(MCOperand::createReg(AArch64::X1));
509 Ldr.addOperand(MCOperand::createReg(AArch64::X0));
510510 Ldr.addOperand(SymTLSDescLo12);
511 Ldr.addOperand(MCOperand::CreateImm(0));
511 Ldr.addOperand(MCOperand::createImm(0));
512512 EmitToStreamer(*OutStreamer, Ldr);
513513
514514 MCInst Add;
515515 Add.setOpcode(AArch64::ADDXri);
516 Add.addOperand(MCOperand::CreateReg(AArch64::X0));
517 Add.addOperand(MCOperand::CreateReg(AArch64::X0));
516 Add.addOperand(MCOperand::createReg(AArch64::X0));
517 Add.addOperand(MCOperand::createReg(AArch64::X0));
518518 Add.addOperand(SymTLSDescLo12);
519 Add.addOperand(MCOperand::CreateImm(AArch64_AM::getShiftValue(0)));
519 Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
520520 EmitToStreamer(*OutStreamer, Add);
521521
522522 // Emit a relocation-annotation. This expands to no code, but requests
528528
529529 MCInst Blr;
530530 Blr.setOpcode(AArch64::BLR);
531 Blr.addOperand(MCOperand::CreateReg(AArch64::X1));
531 Blr.addOperand(MCOperand::createReg(AArch64::X1));
532532 EmitToStreamer(*OutStreamer, Blr);
533533
534534 return;
23652365
23662366 void AArch64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
23672367 NopInst.setOpcode(AArch64::HINT);
2368 NopInst.addOperand(MCOperand::CreateImm(0));
2368 NopInst.addOperand(MCOperand::createImm(0));
23692369 }
23702370 /// useMachineCombiner - return true when a target supports MachineCombiner
23712371 bool AArch64InstrInfo::useMachineCombiner() const {
7272 if (!MO.isJTI() && MO.getOffset())
7373 Expr = MCBinaryExpr::CreateAdd(
7474 Expr, MCConstantExpr::Create(MO.getOffset(), Ctx), Ctx);
75 return MCOperand::CreateExpr(Expr);
75 return MCOperand::createExpr(Expr);
7676 }
7777
7878 MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
147147 RefKind = static_cast(RefFlags);
148148 Expr = AArch64MCExpr::Create(Expr, RefKind, Ctx);
149149
150 return MCOperand::CreateExpr(Expr);
150 return MCOperand::createExpr(Expr);
151151 }
152152
153153 MCOperand AArch64MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
168168 // Ignore all implicit register operands.
169169 if (MO.isImplicit())
170170 return false;
171 MCOp = MCOperand::CreateReg(MO.getReg());
171 MCOp = MCOperand::createReg(MO.getReg());
172172 break;
173173 case MachineOperand::MO_RegisterMask:
174174 // Regmasks are like implicit defs.
175175 return false;
176176 case MachineOperand::MO_Immediate:
177 MCOp = MCOperand::CreateImm(MO.getImm());
177 MCOp = MCOperand::createImm(MO.getImm());
178178 break;
179179 case MachineOperand::MO_MachineBasicBlock:
180 MCOp = MCOperand::CreateExpr(
180 MCOp = MCOperand::createExpr(
181181 MCSymbolRefExpr::Create(MO.getMBB()->getSymbol(), Ctx));
182182 break;
183183 case MachineOperand::MO_GlobalAddress:
10971097 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
10981098 // Add as immediates when possible. Null MCExpr = 0.
10991099 if (!Expr)
1100 Inst.addOperand(MCOperand::CreateImm(0));
1100 Inst.addOperand(MCOperand::createImm(0));
11011101 else if (const MCConstantExpr *CE = dyn_cast(Expr))
1102 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1102 Inst.addOperand(MCOperand::createImm(CE->getValue()));
11031103 else
1104 Inst.addOperand(MCOperand::CreateExpr(Expr));
1104 Inst.addOperand(MCOperand::createExpr(Expr));
11051105 }
11061106
11071107 void addRegOperands(MCInst &Inst, unsigned N) const {
11081108 assert(N == 1 && "Invalid number of operands!");
1109 Inst.addOperand(MCOperand::CreateReg(getReg()));
1109 Inst.addOperand(MCOperand::createReg(getReg()));
11101110 }
11111111
11121112 void addGPR32as64Operands(MCInst &Inst, unsigned N) const {
11181118 uint32_t Reg = RI->getRegClass(AArch64::GPR32RegClassID).getRegister(
11191119 RI->getEncodingValue(getReg()));
11201120
1121 Inst.addOperand(MCOperand::CreateReg(Reg));
1121 Inst.addOperand(MCOperand::createReg(Reg));
11221122 }
11231123
11241124 void addVectorReg64Operands(MCInst &Inst, unsigned N) const {
11251125 assert(N == 1 && "Invalid number of operands!");
11261126 assert(
11271127 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
1128 Inst.addOperand(MCOperand::CreateReg(AArch64::D0 + getReg() - AArch64::Q0));
1128 Inst.addOperand(MCOperand::createReg(AArch64::D0 + getReg() - AArch64::Q0));
11291129 }
11301130
11311131 void addVectorReg128Operands(MCInst &Inst, unsigned N) const {
11321132 assert(N == 1 && "Invalid number of operands!");
11331133 assert(
11341134 AArch64MCRegisterClasses[AArch64::FPR128RegClassID].contains(getReg()));
1135 Inst.addOperand(MCOperand::CreateReg(getReg()));
1135 Inst.addOperand(MCOperand::createReg(getReg()));
11361136 }
11371137
11381138 void addVectorRegLoOperands(MCInst &Inst, unsigned N) const {
11391139 assert(N == 1 && "Invalid number of operands!");
1140 Inst.addOperand(MCOperand::CreateReg(getReg()));
1140 Inst.addOperand(MCOperand::createReg(getReg()));
11411141 }
11421142
11431143 template
11481148 unsigned FirstReg = FirstRegs[NumRegs - 1];
11491149
11501150 Inst.addOperand(
1151 MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0));
1151 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0));
11521152 }
11531153
11541154 template
11591159 unsigned FirstReg = FirstRegs[NumRegs - 1];
11601160
11611161 Inst.addOperand(
1162 MCOperand::CreateReg(FirstReg + getVectorListStart() - AArch64::Q0));
1162 MCOperand::createReg(FirstReg + getVectorListStart() - AArch64::Q0));
11631163 }
11641164
11651165 void addVectorIndex1Operands(MCInst &Inst, unsigned N) const {
11661166 assert(N == 1 && "Invalid number of operands!");
1167 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1167 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
11681168 }
11691169
11701170 void addVectorIndexBOperands(MCInst &Inst, unsigned N) const {
11711171 assert(N == 1 && "Invalid number of operands!");
1172 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1172 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
11731173 }
11741174
11751175 void addVectorIndexHOperands(MCInst &Inst, unsigned N) const {
11761176 assert(N == 1 && "Invalid number of operands!");
1177 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1177 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
11781178 }
11791179
11801180 void addVectorIndexSOperands(MCInst &Inst, unsigned N) const {
11811181 assert(N == 1 && "Invalid number of operands!");
1182 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1182 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
11831183 }
11841184
11851185 void addVectorIndexDOperands(MCInst &Inst, unsigned N) const {
11861186 assert(N == 1 && "Invalid number of operands!");
1187 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
1187 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
11881188 }
11891189
11901190 void addImmOperands(MCInst &Inst, unsigned N) const {
11991199 assert(N == 2 && "Invalid number of operands!");
12001200 if (isShiftedImm()) {
12011201 addExpr(Inst, getShiftedImmVal());
1202 Inst.addOperand(MCOperand::CreateImm(getShiftedImmShift()));
1202 Inst.addOperand(MCOperand::createImm(getShiftedImmShift()));
12031203 } else {
12041204 addExpr(Inst, getImm());
1205 Inst.addOperand(MCOperand::CreateImm(0));
1205 Inst.addOperand(MCOperand::createImm(0));
12061206 }
12071207 }
12081208
12091209 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
12101210 assert(N == 1 && "Invalid number of operands!");
1211 Inst.addOperand(MCOperand::CreateImm(getCondCode()));
1211 Inst.addOperand(MCOperand::createImm(getCondCode()));
12121212 }
12131213
12141214 void addAdrpLabelOperands(MCInst &Inst, unsigned N) const {
12171217 if (!MCE)
12181218 addExpr(Inst, getImm());
12191219 else
1220 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 12));
1220 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 12));
12211221 }
12221222
12231223 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
12301230 const MCConstantExpr *MCE = dyn_cast(getImm());
12311231
12321232 if (!MCE) {
1233 Inst.addOperand(MCOperand::CreateExpr(getImm()));
1233 Inst.addOperand(MCOperand::createExpr(getImm()));
12341234 return;
12351235 }
1236 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / Scale));
1236 Inst.addOperand(MCOperand::createImm(MCE->getValue() / Scale));
12371237 }
12381238
12391239 void addSImm9Operands(MCInst &Inst, unsigned N) const {
12401240 assert(N == 1 && "Invalid number of operands!");
12411241 const MCConstantExpr *MCE = cast(getImm());
1242 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1242 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
12431243 }
12441244
12451245 void addSImm7s4Operands(MCInst &Inst, unsigned N) const {
12461246 assert(N == 1 && "Invalid number of operands!");
12471247 const MCConstantExpr *MCE = cast(getImm());
1248 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 4));
1248 Inst.addOperand(MCOperand::createImm(MCE->getValue() / 4));
12491249 }
12501250
12511251 void addSImm7s8Operands(MCInst &Inst, unsigned N) const {
12521252 assert(N == 1 && "Invalid number of operands!");
12531253 const MCConstantExpr *MCE = cast(getImm());
1254 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 8));
1254 Inst.addOperand(MCOperand::createImm(MCE->getValue() / 8));
12551255 }
12561256
12571257 void addSImm7s16Operands(MCInst &Inst, unsigned N) const {
12581258 assert(N == 1 && "Invalid number of operands!");
12591259 const MCConstantExpr *MCE = cast(getImm());
1260 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() / 16));
1260 Inst.addOperand(MCOperand::createImm(MCE->getValue() / 16));
12611261 }
12621262
12631263 void addImm0_7Operands(MCInst &Inst, unsigned N) const {
12641264 assert(N == 1 && "Invalid number of operands!");
12651265 const MCConstantExpr *MCE = cast(getImm());
1266 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1266 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
12671267 }
12681268
12691269 void addImm1_8Operands(MCInst &Inst, unsigned N) const {
12701270 assert(N == 1 && "Invalid number of operands!");
12711271 const MCConstantExpr *MCE = cast(getImm());
1272 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1272 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
12731273 }
12741274
12751275 void addImm0_15Operands(MCInst &Inst, unsigned N) const {
12761276 assert(N == 1 && "Invalid number of operands!");
12771277 const MCConstantExpr *MCE = cast(getImm());
1278 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1278 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
12791279 }
12801280
12811281 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
12821282 assert(N == 1 && "Invalid number of operands!");
12831283 const MCConstantExpr *MCE = cast(getImm());
12841284 assert(MCE && "Invalid constant immediate operand!");
1285 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1285 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
12861286 }
12871287
12881288 void addImm0_31Operands(MCInst &Inst, unsigned N) const {
12891289 assert(N == 1 && "Invalid number of operands!");
12901290 const MCConstantExpr *MCE = cast(getImm());
1291 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1291 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
12921292 }
12931293
12941294 void addImm1_31Operands(MCInst &Inst, unsigned N) const {
12951295 assert(N == 1 && "Invalid number of operands!");
12961296 const MCConstantExpr *MCE = cast(getImm());
1297 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1297 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
12981298 }
12991299
13001300 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
13011301 assert(N == 1 && "Invalid number of operands!");
13021302 const MCConstantExpr *MCE = cast(getImm());
1303 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1303 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13041304 }
13051305
13061306 void addImm0_63Operands(MCInst &Inst, unsigned N) const {
13071307 assert(N == 1 && "Invalid number of operands!");
13081308 const MCConstantExpr *MCE = cast(getImm());
1309 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1309 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13101310 }
13111311
13121312 void addImm1_63Operands(MCInst &Inst, unsigned N) const {
13131313 assert(N == 1 && "Invalid number of operands!");
13141314 const MCConstantExpr *MCE = cast(getImm());
1315 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1315 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13161316 }
13171317
13181318 void addImm1_64Operands(MCInst &Inst, unsigned N) const {
13191319 assert(N == 1 && "Invalid number of operands!");
13201320 const MCConstantExpr *MCE = cast(getImm());
1321 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1321 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13221322 }
13231323
13241324 void addImm0_127Operands(MCInst &Inst, unsigned N) const {
13251325 assert(N == 1 && "Invalid number of operands!");
13261326 const MCConstantExpr *MCE = cast(getImm());
1327 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1327 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13281328 }
13291329
13301330 void addImm0_255Operands(MCInst &Inst, unsigned N) const {
13311331 assert(N == 1 && "Invalid number of operands!");
13321332 const MCConstantExpr *MCE = cast(getImm());
1333 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1333 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13341334 }
13351335
13361336 void addImm0_65535Operands(MCInst &Inst, unsigned N) const {
13371337 assert(N == 1 && "Invalid number of operands!");
13381338 const MCConstantExpr *MCE = cast(getImm());
1339 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1339 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13401340 }
13411341
13421342 void addImm32_63Operands(MCInst &Inst, unsigned N) const {
13431343 assert(N == 1 && "Invalid number of operands!");
13441344 const MCConstantExpr *MCE = cast(getImm());
1345 Inst.addOperand(MCOperand::CreateImm(MCE->getValue()));
1345 Inst.addOperand(MCOperand::createImm(MCE->getValue()));
13461346 }
13471347
13481348 void addLogicalImm32Operands(MCInst &Inst, unsigned N) const {
13501350 const MCConstantExpr *MCE = cast(getImm());
13511351 uint64_t encoding =
13521352 AArch64_AM::encodeLogicalImmediate(MCE->getValue() & 0xFFFFFFFF, 32);
1353 Inst.addOperand(MCOperand::CreateImm(encoding));
1353 Inst.addOperand(MCOperand::createImm(encoding));
13541354 }
13551355
13561356 void addLogicalImm64Operands(MCInst &Inst, unsigned N) const {
13571357 assert(N == 1 && "Invalid number of operands!");
13581358 const MCConstantExpr *MCE = cast(getImm());
13591359 uint64_t encoding = AArch64_AM::encodeLogicalImmediate(MCE->getValue(), 64);
1360 Inst.addOperand(MCOperand::CreateImm(encoding));
1360 Inst.addOperand(MCOperand::createImm(encoding));
13611361 }
13621362
13631363 void addLogicalImm32NotOperands(MCInst &Inst, unsigned N) const {
13651365 const MCConstantExpr *MCE = cast(getImm());
13661366 int64_t Val = ~MCE->getValue() & 0xFFFFFFFF;
13671367 uint64_t encoding = AArch64_AM::encodeLogicalImmediate(Val, 32);
1368 Inst.addOperand(MCOperand::CreateImm(encoding));
1368 Inst.addOperand(MCOperand::createImm(encoding));
13691369 }
13701370
13711371 void addLogicalImm64NotOperands(MCInst &Inst, unsigned N) const {
13731373 const MCConstantExpr *MCE = cast(getImm());
13741374 uint64_t encoding =
13751375 AArch64_AM::encodeLogicalImmediate(~MCE->getValue(), 64);
1376 Inst.addOperand(MCOperand::CreateImm(encoding));
1376 Inst.addOperand(MCOperand::createImm(encoding));
13771377 }
13781378
13791379 void addSIMDImmType10Operands(MCInst &Inst, unsigned N) const {
13801380 assert(N == 1 && "Invalid number of operands!");
13811381 const MCConstantExpr *MCE = cast(getImm());
13821382 uint64_t encoding = AArch64_AM::encodeAdvSIMDModImmType10(MCE->getValue());
1383 Inst.addOperand(MCOperand::CreateImm(encoding));
1383 Inst.addOperand(MCOperand::createImm(encoding));
13841384 }
13851385
13861386 void addBranchTarget26Operands(MCInst &Inst, unsigned N) const {
13941394 return;
13951395 }
13961396 assert(MCE && "Invalid constant immediate operand!");
1397 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
1397 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
13981398 }
13991399
14001400 void addPCRelLabel19Operands(MCInst &Inst, unsigned N) const {
14081408 return;
14091409 }
14101410 assert(MCE && "Invalid constant immediate operand!");
1411 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
1411 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
14121412 }
14131413
14141414 void addBranchTarget14Operands(MCInst &Inst, unsigned N) const {
14221422 return;
14231423 }
14241424 assert(MCE && "Invalid constant immediate operand!");
1425 Inst.addOperand(MCOperand::CreateImm(MCE->getValue() >> 2));
1425 Inst.addOperand(MCOperand::createImm(MCE->getValue() >> 2));
14261426 }
14271427
14281428 void addFPImmOperands(MCInst &Inst, unsigned N) const {
14291429 assert(N == 1 && "Invalid number of operands!");
1430 Inst.addOperand(MCOperand::CreateImm(getFPImm()));
1430 Inst.addOperand(MCOperand::createImm(getFPImm()));
14311431 }
14321432
14331433 void addBarrierOperands(MCInst &Inst, unsigned N) const {
14341434 assert(N == 1 && "Invalid number of operands!");
1435 Inst.addOperand(MCOperand::CreateImm(getBarrier()));
1435 Inst.addOperand(MCOperand::createImm(getBarrier()));
14361436 }
14371437
14381438 void addMRSSystemRegisterOperands(MCInst &Inst, unsigned N) const {
14391439 assert(N == 1 && "Invalid number of operands!");
14401440
1441 Inst.addOperand(MCOperand::CreateImm(SysReg.MRSReg));
1441 Inst.addOperand(MCOperand::createImm(SysReg.MRSReg));
14421442 }
14431443
14441444 void addMSRSystemRegisterOperands(MCInst &Inst, unsigned N) const {
14451445 assert(N == 1 && "Invalid number of operands!");
14461446
1447 Inst.addOperand(MCOperand::CreateImm(SysReg.MSRReg));
1447 Inst.addOperand(MCOperand::createImm(SysReg.MSRReg));
14481448 }
14491449
14501450 void addSystemPStateFieldOperands(MCInst &Inst, unsigned N) const {
14511451 assert(N == 1 && "Invalid number of operands!");
14521452
1453 Inst.addOperand(MCOperand::CreateImm(SysReg.PStateField));
1453 Inst.addOperand(MCOperand::createImm(SysReg.PStateField));
14541454 }
14551455
14561456 void addSysCROperands(MCInst &Inst, unsigned N) const {
14571457 assert(N == 1 && "Invalid number of operands!");
1458 Inst.addOperand(MCOperand::CreateImm(getSysCR()));
1458 Inst.addOperand(MCOperand::createImm(getSysCR()));
14591459 }
14601460
14611461 void addPrefetchOperands(MCInst &Inst, unsigned N) const {
14621462 assert(N == 1 && "Invalid number of operands!");
1463 Inst.addOperand(MCOperand::CreateImm(getPrefetch()));
1463 Inst.addOperand(MCOperand::createImm(getPrefetch()));
14641464 }
14651465
14661466 void addShifterOperands(MCInst &Inst, unsigned N) const {
14671467 assert(N == 1 && "Invalid number of operands!");
14681468 unsigned Imm =
14691469 AArch64_AM::getShifterImm(getShiftExtendType(), getShiftExtendAmount());
1470 Inst.addOperand(MCOperand::CreateImm(Imm));
1470 Inst.addOperand(MCOperand::createImm(Imm));
14711471 }
14721472
14731473 void addExtendOperands(MCInst &Inst, unsigned N) const {
14751475 AArch64_AM::ShiftExtendType ET = getShiftExtendType();
14761476 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTW;
14771477 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount());
1478 Inst.addOperand(MCOperand::CreateImm(Imm));
1478 Inst.addOperand(MCOperand::createImm(Imm));
14791479 }
14801480
14811481 void addExtend64Operands(MCInst &Inst, unsigned N) const {
14831483 AArch64_AM::ShiftExtendType ET = getShiftExtendType();
14841484 if (ET == AArch64_AM::LSL) ET = AArch64_AM::UXTX;
14851485 unsigned Imm = AArch64_AM::getArithExtendImm(ET, getShiftExtendAmount());
1486 Inst.addOperand(MCOperand::CreateImm(Imm));
1486 Inst.addOperand(MCOperand::createImm(Imm));
14871487 }
14881488
14891489 void addMemExtendOperands(MCInst &Inst, unsigned N) const {
14901490 assert(N == 2 && "Invalid number of operands!");
14911491 AArch64_AM::ShiftExtendType ET = getShiftExtendType();
14921492 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX;
1493 Inst.addOperand(MCOperand::CreateImm(IsSigned));
1494 Inst.addOperand(MCOperand::CreateImm(getShiftExtendAmount() != 0));
1493 Inst.addOperand(MCOperand::createImm(IsSigned));
1494 Inst.addOperand(MCOperand::createImm(getShiftExtendAmount() != 0));
14951495 }
14961496
14971497 // For 8-bit load/store instructions with a register offset, both the
15021502 assert(N == 2 && "Invalid number of operands!");
15031503 AArch64_AM::ShiftExtendType ET = getShiftExtendType();
15041504 bool IsSigned = ET == AArch64_AM::SXTW || ET == AArch64_AM::SXTX;
1505 Inst.addOperand(MCOperand::CreateImm(IsSigned));
1506 Inst.addOperand(MCOperand::CreateImm(hasShiftExtendAmount()));
1505 Inst.addOperand(MCOperand::createImm(IsSigned));
1506 Inst.addOperand(MCOperand::createImm(hasShiftExtendAmount()));
15071507 }
15081508
15091509 template
15121512
15131513 const MCConstantExpr *CE = cast(getImm());
15141514 uint64_t Value = CE->getValue();
1515 Inst.addOperand(MCOperand::CreateImm((Value >> Shift) & 0xffff));
1515 Inst.addOperand(MCOperand::createImm((Value >> Shift) & 0xffff));
15161516 }
15171517
15181518 template
15211521
15221522 const MCConstantExpr *CE = cast(getImm());
15231523 uint64_t Value = CE->getValue();
1524 Inst.addOperand(MCOperand::CreateImm((~Value >> Shift) & 0xffff));
1524 Inst.addOperand(MCOperand::createImm((~Value >> Shift) & 0xffff));
15251525 }
15261526
15271527 void print(raw_ostream &OS) const override;
41094109
41104110 MCInst Inst;
41114111 Inst.setOpcode(AArch64::TLSDESCCALL);
4112 Inst.addOperand(MCOperand::CreateExpr(Expr));
4112 Inst.addOperand(MCOperand::createExpr(Expr));
41134113
41144114 getParser().getStreamer().EmitInstruction(Inst, STI);
41154115 return false;
260260 return Fail;
261261
262262 unsigned Register = FPR128DecoderTable[RegNo];
263 Inst.addOperand(MCOperand::CreateReg(Register));
263 Inst.addOperand(MCOperand::createReg(Register));
264264 return Success;
265265 }
266266
289289 return Fail;
290290
291291 unsigned Register = FPR64DecoderTable[RegNo];
292 Inst.addOperand(MCOperand::CreateReg(Register));
292 Inst.addOperand(MCOperand::createReg(Register));
293293 return Success;
294294 }
295295
310310 return Fail;
311311
312312 unsigned Register = FPR32DecoderTable[RegNo];
313 Inst.addOperand(MCOperand::CreateReg(Register));
313 Inst.addOperand(MCOperand::createReg(Register));
314314 return Success;
315315 }
316316
331331 return Fail;
332332
333333 unsigned Register = FPR16DecoderTable[RegNo];
334 Inst.addOperand(MCOperand::CreateReg(Register));
334 Inst.addOperand(MCOperand::createReg(Register));
335335 return Success;
336336 }
337337
352352 return Fail;
353353
354354 unsigned Register = FPR8DecoderTable[RegNo];
355 Inst.addOperand(MCOperand::CreateReg(Register));
355 Inst.addOperand(MCOperand::createReg(Register));
356356 return Success;
357357 }
358358
373373 return Fail;
374374
375375 unsigned Register = GPR64DecoderTable[RegNo];
376 Inst.addOperand(MCOperand::CreateReg(Register));
376 Inst.addOperand(MCOperand::createReg(Register));
377377 return Success;
378378 }
379379
385385 unsigned Register = GPR64DecoderTable[RegNo];
386386 if (Register == AArch64::XZR)
387387 Register = AArch64::SP;
388 Inst.addOperand(MCOperand::CreateReg(Register));
388 Inst.addOperand(MCOperand::createReg(Register));
389389 return Success;
390390 }
391391
406406 return Fail;
407407
408408 unsigned Register = GPR32DecoderTable[RegNo];
409 Inst.addOperand(MCOperand::CreateReg(Register));
409 Inst.addOperand(MCOperand::createReg(Register));
410410 return Success;
411411 }
412412
419419 unsigned Register = GPR32DecoderTable[RegNo];
420420 if (Register == AArch64::WZR)
421421 Register = AArch64::WSP;
422 Inst.addOperand(MCOperand::CreateReg(Register));
422 Inst.addOperand(MCOperand::createReg(Register));
423423 return Success;
424424 }
425425
440440 return Fail;
441441
442442 unsigned Register = VectorDecoderTable[RegNo];
443 Inst.addOperand(MCOperand::CreateReg(Register));
443 Inst.addOperand(MCOperand::createReg(Register));
444444 return Success;
445445 }
446446
460460 if (RegNo > 31)
461461 return Fail;
462462 unsigned Register = QQDecoderTable[RegNo];
463 Inst.addOperand(MCOperand::CreateReg(Register));
463 Inst.addOperand(MCOperand::createReg(Register));
464464 return Success;
465465 }
466466
483483 if (RegNo > 31)
484484 return Fail;
485485 unsigned Register = QQQDecoderTable[RegNo];
486 Inst.addOperand(MCOperand::CreateReg(Register));
486 Inst.addOperand(MCOperand::createReg(Register));
487487 return Success;
488488 }
489489
507507 if (RegNo > 31)
508508 return Fail;
509509 unsigned Register = QQQQDecoderTable[RegNo];
510 Inst.addOperand(MCOperand::CreateReg(Register));
510 Inst.addOperand(MCOperand::createReg(Register));
511511 return Success;
512512 }
513513
527527 if (RegNo > 31)
528528 return Fail;
529529 unsigned Register = DDDecoderTable[RegNo];
530 Inst.addOperand(MCOperand::CreateReg(Register));
530 Inst.addOperand(MCOperand::createReg(Register));
531531 return Success;
532532 }
533533
550550 if (RegNo > 31)
551551 return Fail;
552552 unsigned Register = DDDDecoderTable[RegNo];
553 Inst.addOperand(MCOperand::CreateReg(Register));
553 Inst.addOperand(MCOperand::createReg(Register));
554554 return Success;
555555 }
556556
574574 if (RegNo > 31)
575575 return Fail;
576576 unsigned Register = DDDDDecoderTable[RegNo];
577 Inst.addOperand(MCOperand::CreateReg(Register));
577 Inst.addOperand(MCOperand::createReg(Register));
578578 return Success;
579579 }
580580
583583 const void *Decoder) {
584584 // scale{5} is asserted as 1 in tblgen.
585585 Imm |= 0x20;
586 Inst.addOperand(MCOperand::CreateImm(64 - Imm));
586 Inst.addOperand(MCOperand::createImm(64 - Imm));
587587 return Success;
588588 }
589589
590590 static DecodeStatus DecodeFixedPointScaleImm64(llvm::MCInst &Inst, unsigned Imm,
591591 uint64_t Addr,
592592 const void *Decoder) {
593 Inst.addOperand(MCOperand::CreateImm(64 - Imm));
593 Inst.addOperand(MCOperand::createImm(64 - Imm));
594594 return Success;
595595 }
596596
606606
607607 if (!Dis->tryAddingSymbolicOperand(Inst, ImmVal * 4, Addr,
608608 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
609 Inst.addOperand(MCOperand::CreateImm(ImmVal));
609 Inst.addOperand(MCOperand::createImm(ImmVal));
610610 return Success;
611611 }
612612
613613 static DecodeStatus DecodeMemExtend(llvm::MCInst &Inst, unsigned Imm,
614614 uint64_t Address, const void *Decoder) {
615 Inst.addOperand(MCOperand::CreateImm((Imm >> 1) & 1));
616 Inst.addOperand(MCOperand::CreateImm(Imm & 1));
615 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
616 Inst.addOperand(MCOperand::createImm(Imm & 1));
617617 return Success;
618618 }
619619
620620 static DecodeStatus DecodeMRSSystemRegister(llvm::MCInst &Inst, unsigned Imm,
621621 uint64_t Address,
622622 const void *Decoder) {
623 Inst.addOperand(MCOperand::CreateImm(Imm));
623 Inst.addOperand(MCOperand::createImm(Imm));
624624
625625 // Every system register in the encoding space is valid with the syntax
626626 // S____, so decoding system registers always succeeds.
630630 static DecodeStatus DecodeMSRSystemRegister(llvm::MCInst &Inst, unsigned Imm,
631631 uint64_t Address,
632632 const void *Decoder) {
633 Inst.addOperand(MCOperand::CreateImm(Imm));
633 Inst.addOperand(MCOperand::createImm(Imm));
634634
635635 return Success;
636636 }
653653 }
654654
655655 // Add the lane
656 Inst.addOperand(MCOperand::CreateImm(1));
656 Inst.addOperand(MCOperand::createImm(1));
657657
658658 return Success;
659659 }
660660
661661 static DecodeStatus DecodeVecShiftRImm(llvm::MCInst &Inst, unsigned Imm,
662662 unsigned Add) {
663 Inst.addOperand(MCOperand::CreateImm(Add - Imm));
663 Inst.addOperand(MCOperand::createImm(Add - Imm));
664664 return Success;
665665 }
666666
667667 static DecodeStatus DecodeVecShiftLImm(llvm::MCInst &Inst, unsigned Imm,
668668 unsigned Add) {
669 Inst.addOperand(MCOperand::CreateImm((Imm + Add) & (Add - 1)));
669 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
670670 return Success;
671671 }
672672
786786 break;
787787 }
788788
789 Inst.addOperand(MCOperand::CreateImm(shift));
789 Inst.addOperand(MCOperand::createImm(shift));
790790 return Success;
791791 }
792792
818818 Inst.getOpcode() == AArch64::MOVKXi)
819819 Inst.addOperand(Inst.getOperand(0));
820820
821 Inst.addOperand(MCOperand::CreateImm(imm));
822 Inst.addOperand(MCOperand::CreateImm(shift));
821 Inst.addOperand(MCOperand::createImm(imm));
822 Inst.addOperand(MCOperand::createImm(shift));
823823 return Success;
824824 }
825825
837837 return Fail;
838838 case AArch64::PRFMui:
839839 // Rt is an immediate in prefetch.
840 Inst.addOperand(MCOperand::CreateImm(Rt));
840 Inst.addOperand(MCOperand::createImm(Rt));
841841 break;
842842 case AArch64::STRBBui:
843843 case AArch64::LDRBBui:
880880
881881 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
882882 if (!Dis->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 4))
883 Inst.addOperand(MCOperand::CreateImm(offset));
883 Inst.addOperand(MCOperand::createImm(offset));
884884 return Success;
885885 }
886886
955955 return Fail;
956956 case AArch64::PRFUMi:
957957 // Rt is an immediate in prefetch.
958 Inst.addOperand(MCOperand::CreateImm(Rt));
958 Inst.addOperand(MCOperand::createImm(Rt));
959959 break;
960960 case AArch64::STURBBi:
961961 case AArch64::LDURBBi:
10561056 }
10571057
10581058 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1059 Inst.addOperand(MCOperand::CreateImm(offset));
1059 Inst.addOperand(MCOperand::createImm(offset));
10601060
10611061 bool IsLoad = fieldFromInstruction(insn, 22, 1);
10621062 bool IsIndexed = fieldFromInstruction(insn, 10, 2) != 0;
12671267 }
12681268
12691269 DecodeGPR64spRegisterClass(Inst, Rn, Addr, Decoder);
1270 Inst.addOperand(MCOperand::CreateImm(offset));
1270 Inst.addOperand(MCOperand::createImm(offset));
12711271
12721272 // You shouldn't load to the same register twice in an instruction...
12731273 if (IsLoad && Rt == Rt2)
13341334 break;
13351335 }
13361336
1337 Inst.addOperand(MCOperand::CreateImm(extend));
1337 Inst.addOperand(MCOperand::createImm(extend));
13381338 return Success;
13391339 }
13401340
13651365 if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 32))
13661366 return Fail;
13671367 }
1368 Inst.addOperand(MCOperand::CreateImm(imm));
1368 Inst.addOperand(MCOperand::createImm(imm));
13691369 return Success;
13701370 }
13711371
13821382 else
13831383 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
13841384
1385 Inst.addOperand(MCOperand::CreateImm(imm));
1385 Inst.addOperand(MCOperand::createImm(imm));
13861386
13871387 switch (Inst.getOpcode()) {
13881388 default:
13951395 case AArch64::MOVIv4i32:
13961396 case AArch64::MVNIv2i32:
13971397 case AArch64::MVNIv4i32:
1398 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1398 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
13991399 break;
14001400 case AArch64::MOVIv2s_msl:
14011401 case AArch64::MOVIv4s_msl:
14021402 case AArch64::MVNIv2s_msl:
14031403 case AArch64::MVNIv4s_msl:
1404 Inst.addOperand(MCOperand::CreateImm(cmode & 1 ? 0x110 : 0x108));
1404 Inst.addOperand(MCOperand::createImm(cmode & 1 ? 0x110 : 0x108));
14051405 break;
14061406 }
14071407
14201420 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
14211421 DecodeVectorRegisterClass(Inst, Rd, Addr, Decoder);
14221422
1423 Inst.addOperand(MCOperand::CreateImm(imm));
1424 Inst.addOperand(MCOperand::CreateImm((cmode & 6) << 2));
1423 Inst.addOperand(MCOperand::createImm(imm));
1424 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
14251425
14261426 return Success;
14271427 }
14401440
14411441 DecodeGPR64RegisterClass(Inst, Rd, Addr, Decoder);
14421442 if (!Dis->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 4))
1443 Inst.addOperand(MCOperand::CreateImm(imm));
1443 Inst.addOperand(MCOperand::createImm(imm));
14441444
14451445 return Success;
14461446 }
14761476 }
14771477
14781478 if (!Dis->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 4))
1479 Inst.addOperand(MCOperand::CreateImm(ImmVal));
1480 Inst.addOperand(MCOperand::CreateImm(12 * ShifterVal));
1479 Inst.addOperand(MCOperand::createImm(ImmVal));
1480 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
14811481 return Success;
14821482 }
14831483
14931493 imm |= ~((1LL << 26) - 1);
14941494
14951495 if (!Dis->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 4))
1496 Inst.addOperand(MCOperand::CreateImm(imm));
1496 Inst.addOperand(MCOperand::createImm(imm));
14971497
14981498 return Success;
14991499 }
15071507
15081508 uint64_t pstate_field = (op1 << 3) | op2;
15091509
1510 Inst.addOperand(MCOperand::CreateImm(pstate_field));
1511 Inst.addOperand(MCOperand::CreateImm(crm));
1510 Inst.addOperand(MCOperand::createImm(pstate_field));
1511 Inst.addOperand(MCOperand::createImm(crm));
15121512
15131513 bool ValidNamed;
15141514 const AArch64Disassembler *Dis =
15361536 DecodeGPR32RegisterClass(Inst, Rt, Addr, Decoder);
15371537 else
15381538 DecodeGPR64RegisterClass(Inst, Rt, Addr, Decoder);
1539 Inst.addOperand(MCOperand::CreateImm(bit));
1539 Inst.addOperand(MCOperand::createImm(bit));
15401540 if (!Dis->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 4))
1541 Inst.addOperand(MCOperand::CreateImm(dst));
1542
1543 return Success;
1544 }
1541 Inst.addOperand(MCOperand::createImm(dst));
1542
1543 return Success;
1544 }
213213 Expr = MCConstantExpr::Create(0, Ctx);
214214 }
215215
216 MI.addOperand(MCOperand::CreateExpr(Expr));
216 MI.addOperand(MCOperand::createExpr(Expr));
217217
218218 return true;
219219 }
13331333 case ARM::t2MOVi16_ga_pcrel: {
13341334 MCInst TmpInst;
13351335 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1336 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1336 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
13371337
13381338 unsigned TF = MI->getOperand(1).getTargetFlags();
13391339 const GlobalValue *GV = MI->getOperand(1).getGlobal();
13501350 MCBinaryExpr::CreateAdd(LabelSymExpr,
13511351 MCConstantExpr::Create(PCAdj, OutContext),
13521352 OutContext), OutContext), OutContext);
1353 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1353 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
13541354
13551355 // Add predicate operands.
1356 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1357 TmpInst.addOperand(MCOperand::CreateReg(0));
1356 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1357 TmpInst.addOperand(MCOperand::createReg(0));
13581358 // Add 's' bit operand (always reg0 for this)
1359 TmpInst.addOperand(MCOperand::CreateReg(0));
1359 TmpInst.addOperand(MCOperand::createReg(0));
13601360 EmitToStreamer(*OutStreamer, TmpInst);
13611361 return;
13621362 }
13651365 MCInst TmpInst;
13661366 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
13671367 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1368 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1369 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1368 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1369 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
13701370
13711371 unsigned TF = MI->getOperand(2).getTargetFlags();
13721372 const GlobalValue *GV = MI->getOperand(2).getGlobal();
13831383 MCBinaryExpr::CreateAdd(LabelSymExpr,
13841384 MCConstantExpr::Create(PCAdj, OutContext),
13851385 OutContext), OutContext), OutContext);
1386 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1386 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
13871387 // Add predicate operands.
1388 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1389 TmpInst.addOperand(MCOperand::CreateReg(0));
1388 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1389 TmpInst.addOperand(MCOperand::createReg(0));
13901390 // Add 's' bit operand (always reg0 for this)
1391 TmpInst.addOperand(MCOperand::CreateReg(0));
1391 TmpInst.addOperand(MCOperand::createReg(0));
13921392 EmitToStreamer(*OutStreamer, TmpInst);
13931393 return;
13941394 }
15561556 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
15571557 ARM::MOVr : ARM::tMOVr;
15581558 TmpInst.setOpcode(Opc);
1559 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1560 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1559 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1560 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
15611561 // Add predicate operands.
1562 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1563 TmpInst.addOperand(MCOperand::CreateReg(0));
1562 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1563 TmpInst.addOperand(MCOperand::createReg(0));
15641564 // Add 's' bit operand (always reg0 for this)
15651565 if (Opc == ARM::MOVr)
1566 TmpInst.addOperand(MCOperand::CreateReg(0));
1566 TmpInst.addOperand(MCOperand::createReg(0));
15671567 EmitToStreamer(*OutStreamer, TmpInst);
15681568
15691569 // Make sure the Thumb jump table is 4-byte aligned.
15811581 if (MI->getOperand(1).getReg() == 0) {
15821582 // literal offset
15831583 TmpInst.setOpcode(ARM::LDRi12);
1584 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1585 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1586 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1584 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1585 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1586 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
15871587 } else {
15881588 TmpInst.setOpcode(ARM::LDRrs);
1589 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1590 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1591 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1592 TmpInst.addOperand(MCOperand::CreateImm(0));
1589 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1590 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1591 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1592 TmpInst.addOperand(MCOperand::createImm(0));
15931593 }
15941594 // Add predicate operands.
1595 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1596 TmpInst.addOperand(MCOperand::CreateReg(0));
1595 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1596 TmpInst.addOperand(MCOperand::createReg(0));
15971597 EmitToStreamer(*OutStreamer, TmpInst);
15981598
15991599 // Output the data for the jump table itself
3535 void ARMInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
3636 if (hasNOP()) {
3737 NopInst.setOpcode(ARM::HINT);
38 NopInst.addOperand(MCOperand::CreateImm(0));
39 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
40 NopInst.addOperand(MCOperand::CreateReg(0));
38 NopInst.addOperand(MCOperand::createImm(0));
39 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
40 NopInst.addOperand(MCOperand::createReg(0));
4141 } else {
4242 NopInst.setOpcode(ARM::MOVr);
43 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
44 NopInst.addOperand(MCOperand::CreateReg(ARM::R0));
45 NopInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
46 NopInst.addOperand(MCOperand::CreateReg(0));
47 NopInst.addOperand(MCOperand::CreateReg(0));
43 NopInst.addOperand(MCOperand::createReg(ARM::R0));
44 NopInst.addOperand(MCOperand::createReg(ARM::R0));
45 NopInst.addOperand(MCOperand::createImm(ARMCC::AL));
46 NopInst.addOperand(MCOperand::createReg(0));
47 NopInst.addOperand(MCOperand::createReg(0));
4848 }
4949 }
5050
6060 MCConstantExpr::Create(MO.getOffset(),
6161 OutContext),
6262 OutContext);
63 return MCOperand::CreateExpr(Expr);
63 return MCOperand::createExpr(Expr);
6464
6565 }
6666
7373 if (MO.isImplicit() && MO.getReg() != ARM::CPSR)
7474 return false;
7575 assert(!MO.getSubReg() && "Subregs should be eliminated!");
76 MCOp = MCOperand::CreateReg(MO.getReg());
76 MCOp = MCOperand::createReg(MO.getReg());
7777 break;
7878 case MachineOperand::MO_Immediate:
79 MCOp = MCOperand::CreateImm(MO.getImm());
79 MCOp = MCOperand::createImm(MO.getImm());
8080 break;
8181 case MachineOperand::MO_MachineBasicBlock:
82 MCOp = MCOperand::CreateExpr(MCSymbolRefExpr::Create(
82 MCOp = MCOperand::createExpr(MCSymbolRefExpr::Create(
8383 MO.getMBB()->getSymbol(), OutContext));
8484 break;
8585 case MachineOperand::MO_GlobalAddress: {
104104 APFloat Val = MO.getFPImm()->getValueAPF();
105105 bool ignored;
106106 Val.convert(APFloat::IEEEdouble, APFloat::rmTowardZero, &ignored);
107 MCOp = MCOperand::CreateFPImm(Val.convertToDouble());
107 MCOp = MCOperand::createFPImm(Val.convertToDouble());
108108 break;
109109 }
110110 case MachineOperand::MO_RegisterMask:
17481748 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
17491749 // Add as immediates when possible. Null MCExpr = 0.
17501750 if (!Expr)
1751 Inst.addOperand(MCOperand::CreateImm(0));
1751 Inst.addOperand(MCOperand::createImm(0));
17521752 else if (const MCConstantExpr *CE = dyn_cast(Expr))
1753 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1753 Inst.addOperand(MCOperand::createImm(CE->getValue()));
17541754 else
1755 Inst.addOperand(MCOperand::CreateExpr(Expr));
1755 Inst.addOperand(MCOperand::createExpr(Expr));
17561756 }
17571757
17581758 void addCondCodeOperands(MCInst &Inst, unsigned N) const {
17591759 assert(N == 2 && "Invalid number of operands!");
1760 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1760 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
17611761 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR;
1762 Inst.addOperand(MCOperand::CreateReg(RegNum));
1762 Inst.addOperand(MCOperand::createReg(RegNum));
17631763 }
17641764
17651765 void addCoprocNumOperands(MCInst &Inst, unsigned N) const {
17661766 assert(N == 1 && "Invalid number of operands!");
1767 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1767 Inst.addOperand(MCOperand::createImm(getCoproc()));
17681768 }
17691769
17701770 void addCoprocRegOperands(MCInst &Inst, unsigned N) const {
17711771 assert(N == 1 && "Invalid number of operands!");
1772 Inst.addOperand(MCOperand::CreateImm(getCoproc()));
1772 Inst.addOperand(MCOperand::createImm(getCoproc()));
17731773 }
17741774
17751775 void addCoprocOptionOperands(MCInst &Inst, unsigned N) const {
17761776 assert(N == 1 && "Invalid number of operands!");
1777 Inst.addOperand(MCOperand::CreateImm(CoprocOption.Val));
1777 Inst.addOperand(MCOperand::createImm(CoprocOption.Val));
17781778 }
17791779
17801780 void addITMaskOperands(MCInst &Inst, unsigned N) const {
17811781 assert(N == 1 && "Invalid number of operands!");
1782 Inst.addOperand(MCOperand::CreateImm(ITMask.Mask));
1782 Inst.addOperand(MCOperand::createImm(ITMask.Mask));
17831783 }
17841784
17851785 void addITCondCodeOperands(MCInst &Inst, unsigned N) const {
17861786 assert(N == 1 && "Invalid number of operands!");
1787 Inst.addOperand(MCOperand::CreateImm(unsigned(getCondCode())));
1787 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode())));
17881788 }
17891789
17901790 void addCCOutOperands(MCInst &Inst, unsigned N) const {
17911791 assert(N == 1 && "Invalid number of operands!");
1792 Inst.addOperand(MCOperand::CreateReg(getReg()));
1792 Inst.addOperand(MCOperand::createReg(getReg()));
17931793 }
17941794
17951795 void addRegOperands(MCInst &Inst, unsigned N) const {
17961796 assert(N == 1 && "Invalid number of operands!");
1797 Inst.addOperand(MCOperand::CreateReg(getReg()));
1797 Inst.addOperand(MCOperand::createReg(getReg()));
17981798 }
17991799
18001800 void addRegShiftedRegOperands(MCInst &Inst, unsigned N) const {
18011801 assert(N == 3 && "Invalid number of operands!");
18021802 assert(isRegShiftedReg() &&
18031803 "addRegShiftedRegOperands() on non-RegShiftedReg!");
1804 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.SrcReg));
1805 Inst.addOperand(MCOperand::CreateReg(RegShiftedReg.ShiftReg));
1806 Inst.addOperand(MCOperand::CreateImm(
1804 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg));
1805 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg));
1806 Inst.addOperand(MCOperand::createImm(
18071807 ARM_AM::getSORegOpc(RegShiftedReg.ShiftTy, RegShiftedReg.ShiftImm)));
18081808 }
18091809
18111811 assert(N == 2 && "Invalid number of operands!");
18121812 assert(isRegShiftedImm() &&
18131813 "addRegShiftedImmOperands() on non-RegShiftedImm!");
1814 Inst.addOperand(MCOperand::CreateReg(RegShiftedImm.SrcReg));
1814 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg));
18151815 // Shift of #32 is encoded as 0 where permitted
18161816 unsigned Imm = (RegShiftedImm.ShiftImm == 32 ? 0 : RegShiftedImm.ShiftImm);
1817 Inst.addOperand(MCOperand::CreateImm(
1817 Inst.addOperand(MCOperand::createImm(
18181818 ARM_AM::getSORegOpc(RegShiftedImm.ShiftTy, Imm)));
18191819 }
18201820
18211821 void addShifterImmOperands(MCInst &Inst, unsigned N) const {
18221822 assert(N == 1 && "Invalid number of operands!");
1823 Inst.addOperand(MCOperand::CreateImm((ShifterImm.isASR << 5) |
1823 Inst.addOperand(MCOperand::createImm((ShifterImm.isASR << 5) |
18241824 ShifterImm.Imm));
18251825 }
18261826
18291829 const SmallVectorImpl &RegList = getRegList();
18301830 for (SmallVectorImpl::const_iterator
18311831 I = RegList.begin(), E = RegList.end(); I != E; ++I)
1832 Inst.addOperand(MCOperand::CreateReg(*I));
1832 Inst.addOperand(MCOperand::createReg(*I));
18331833 }
18341834
18351835 void addDPRRegListOperands(MCInst &Inst, unsigned N) const {
18431843 void addRotImmOperands(MCInst &Inst, unsigned N) const {
18441844 assert(N == 1 && "Invalid number of operands!");
18451845 // Encoded as val>>3. The printer handles display as 8, 16, 24.
1846 Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
1846 Inst.addOperand(MCOperand::createImm(RotImm.Imm >> 3));
18471847 }
18481848
18491849 void addModImmOperands(MCInst &Inst, unsigned N) const {
18531853 if (isImm())
18541854 return addImmOperands(Inst, N);
18551855
1856 Inst.addOperand(MCOperand::CreateImm(ModImm.Bits | (ModImm.Rot << 7)));
1856 Inst.addOperand(MCOperand::createImm(ModImm.Bits | (ModImm.Rot << 7)));
18571857 }
18581858
18591859 void addModImmNotOperands(MCInst &Inst, unsigned N) const {
18601860 assert(N == 1 && "Invalid number of operands!");
18611861 const MCConstantExpr *CE = dyn_cast(getImm());
18621862 uint32_t Enc = ARM_AM::getSOImmVal(~CE->getValue());
1863 Inst.addOperand(MCOperand::CreateImm(Enc));
1863 Inst.addOperand(MCOperand::createImm(Enc));
18641864 }
18651865
18661866 void addModImmNegOperands(MCInst &Inst, unsigned N) const {
18671867 assert(N == 1 && "Invalid number of operands!");
18681868 const MCConstantExpr *CE = dyn_cast(getImm());
18691869 uint32_t Enc = ARM_AM::getSOImmVal(-CE->getValue());
1870 Inst.addOperand(MCOperand::CreateImm(Enc));
1870 Inst.addOperand(MCOperand::createImm(Enc));
18711871 }
18721872
18731873 void addBitfieldOperands(MCInst &Inst, unsigned N) const {
18781878 // Make a 32-bit mask w/ the referenced bits clear and all other bits set.
18791879 uint32_t Mask = ~(((uint32_t)0xffffffff >> lsb) << (32 - width) >>
18801880 (32 - (lsb + width)));
1881 Inst.addOperand(MCOperand::CreateImm(Mask));
1881 Inst.addOperand(MCOperand::createImm(Mask));
18821882 }
18831883
18841884 void addImmOperands(MCInst &Inst, unsigned N) const {
18891889 void addFBits16Operands(MCInst &Inst, unsigned N) const {
18901890 assert(N == 1 && "Invalid number of operands!");
18911891 const MCConstantExpr *CE = dyn_cast(getImm());
1892 Inst.addOperand(MCOperand::CreateImm(16 - CE->getValue()));
1892 Inst.addOperand(MCOperand::createImm(16 - CE->getValue()));
18931893 }
18941894
18951895 void addFBits32Operands(MCInst &Inst, unsigned N) const {
18961896 assert(N == 1 && "Invalid number of operands!");
18971897 const MCConstantExpr *CE = dyn_cast(getImm());
1898 Inst.addOperand(MCOperand::CreateImm(32 - CE->getValue()));
1898 Inst.addOperand(MCOperand::createImm(32 - CE->getValue()));
18991899 }
19001900
19011901 void addFPImmOperands(MCInst &Inst, unsigned N) const {
19021902 assert(N == 1 && "Invalid number of operands!");
19031903 const MCConstantExpr *CE = dyn_cast(getImm());
19041904 int Val = ARM_AM::getFP32Imm(APInt(32, CE->getValue()));
1905 Inst.addOperand(MCOperand::CreateImm(Val));
1905 Inst.addOperand(MCOperand::createImm(Val));
19061906 }
19071907
19081908 void addImm8s4Operands(MCInst &Inst, unsigned N) const {
19101910 // FIXME: We really want to scale the value here, but the LDRD/STRD
19111911 // instruction don't encode operands that way yet.
19121912 const MCConstantExpr *CE = dyn_cast(getImm());
1913 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
1913 Inst.addOperand(MCOperand::createImm(CE->getValue()));
19141914 }
19151915
19161916 void addImm0_1020s4Operands(MCInst &Inst, unsigned N) const {
19181918 // The immediate is scaled by four in the encoding and is stored
19191919 // in the MCInst as such. Lop off the low two bits here.
19201920 const MCConstantExpr *CE = dyn_cast(getImm());
1921 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1921 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
19221922 }
19231923
19241924 void addImm0_508s4NegOperands(MCInst &Inst, unsigned N) const {
19261926 // The immediate is scaled by four in the encoding and is stored
19271927 // in the MCInst as such. Lop off the low two bits here.
19281928 const MCConstantExpr *CE = dyn_cast(getImm());
1929 Inst.addOperand(MCOperand::CreateImm(-(CE->getValue() / 4)));
1929 Inst.addOperand(MCOperand::createImm(-(CE->getValue() / 4)));
19301930 }
19311931
19321932 void addImm0_508s4Operands(MCInst &Inst, unsigned N) const {
19341934 // The immediate is scaled by four in the encoding and is stored
19351935 // in the MCInst as such. Lop off the low two bits here.
19361936 const MCConstantExpr *CE = dyn_cast(getImm());
1937 Inst.addOperand(MCOperand::CreateImm(CE->getValue() / 4));
1937 Inst.addOperand(MCOperand::createImm(CE->getValue() / 4));
19381938 }
19391939
19401940 void addImm1_16Operands(MCInst &Inst, unsigned N) const {
19421942 // The constant encodes as the immediate-1, and we store in the instruction
19431943 // the bits as encoded, so subtract off one here.
19441944 const MCConstantExpr *CE = dyn_cast(getImm());
1945 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1945 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
19461946 }
19471947
19481948 void addImm1_32Operands(MCInst &Inst, unsigned N) const {
19501950 // The constant encodes as the immediate-1, and we store in the instruction
19511951 // the bits as encoded, so subtract off one here.
19521952 const MCConstantExpr *CE = dyn_cast(getImm());
1953 Inst.addOperand(MCOperand::CreateImm(CE->getValue() - 1));
1953 Inst.addOperand(MCOperand::createImm(CE->getValue() - 1));
19541954 }
19551955
19561956 void addImmThumbSROperands(MCInst &Inst, unsigned N) const {
19591959 // zero.
19601960 const MCConstantExpr *CE = dyn_cast(getImm());
19611961 unsigned Imm = CE->getValue();
1962 Inst.addOperand(MCOperand::CreateImm((Imm == 32 ? 0 : Imm)));
1962 Inst.addOperand(MCOperand::createImm((Imm == 32 ? 0 : Imm)));
19631963 }
19641964
19651965 void addPKHASRImmOperands(MCInst &Inst, unsigned N) const {
19681968 // the instruction as well.
19691969 const MCConstantExpr *CE = dyn_cast(getImm());
19701970 int Val = CE->getValue();
1971 Inst.addOperand(MCOperand::CreateImm(Val == 32 ? 0 : Val));
1971 Inst.addOperand(MCOperand::createImm(Val == 32 ? 0 : Val));
19721972 }
19731973
19741974 void addT2SOImmNotOperands(MCInst &Inst, unsigned N) const {
19761976 // The operand is actually a t2_so_imm, but we have its bitwise
19771977 // negation in the assembly source, so twiddle it here.
19781978 const MCConstantExpr *CE = dyn_cast(getImm());
1979 Inst.addOperand(MCOperand::CreateImm(~CE->getValue()));
1979 Inst.addOperand(MCOperand::createImm(~CE->getValue()));
19801980 }
19811981
19821982 void addT2SOImmNegOperands(MCInst &Inst, unsigned N) const {
19841984 // The operand is actually a t2_so_imm, but we have its
19851985 // negation in the assembly source, so twiddle it here.
19861986 const MCConstantExpr *CE = dyn_cast(getImm());
1987 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1987 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
19881988 }
19891989
19901990 void addImm0_4095NegOperands(MCInst &Inst, unsigned N) const {
19921992 // The operand is actually an imm0_4095, but we have its
19931993 // negation in the assembly source, so twiddle it here.
19941994 const MCConstantExpr *CE = dyn_cast(getImm());
1995 Inst.addOperand(MCOperand::CreateImm(-CE->getValue()));
1995 Inst.addOperand(MCOperand::createImm(-CE->getValue()));
19961996 }
19971997
19981998 void addUnsignedOffset_b8s2Operands(MCInst &Inst, unsigned N) const {
19991999 if(const MCConstantExpr *CE = dyn_cast(getImm())) {
2000 Inst.addOperand(MCOperand::CreateImm(CE->getValue() >> 2));
2000 Inst.addOperand(MCOperand::createImm(CE->getValue() >> 2));
20012001 return;
20022002 }
20032003
20042004 const MCSymbolRefExpr *SR = dyn_cast(Imm.Val);
20052005 assert(SR && "Unknown value type!");
2006 Inst.addOperand(MCOperand::CreateExpr(SR));
2006 Inst.addOperand(MCOperand::createExpr(SR));
20072007 }
20082008
20092009 void addThumbMemPCOperands(MCInst &Inst, unsigned N) const {
20112011 if (isImm()) {
20122012 const MCConstantExpr *CE = dyn_cast(getImm());
20132013 if (CE) {
2014 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
2014 Inst.addOperand(MCOperand::createImm(CE->getValue()));
20152015 return;
20162016 }
20172017
20182018 const MCSymbolRefExpr *SR = dyn_cast(Imm.Val);
20192019 assert(SR && "Unknown value type!");
2020 Inst.addOperand(MCOperand::CreateExpr(SR));
2020 Inst.addOperand(MCOperand::createExpr(SR));
20212021 return;
20222022 }
20232023
20242024 assert(isMem() && "Unknown value type!");
20252025 assert(isa(Memory.OffsetImm) && "Unknown value type!");
2026 Inst.addOperand(MCOperand::CreateImm(Memory.OffsetImm->getValue()));
2026 Inst.addOperand(MCOperand::createImm(Memory.OffsetImm->getValue()));
20272027 }
20282028
20292029 void addMemBarrierOptOperands(MCInst &Inst, unsigned N) const {
20302030 assert(N == 1 && "Invalid number of operands!");
2031 Inst.addOperand(MCOperand::CreateImm(unsigned(getMemBarrierOpt())));
2031 Inst.addOperand(MCOperand::createImm(unsigned(getMemBarrierOpt())));
20322032 }
20332033
20342034 void addInstSyncBarrierOptOperands(MCInst &Inst, unsigned N) const {
20352035 assert(N == 1 && "Invalid number of operands!");
2036 Inst.addOperand(MCOperand::CreateImm(unsigned(getInstSyncBarrierOpt())));
2036 Inst.addOperand(MCOperand::createImm(unsigned(getInstSyncBarrierOpt())));
20372037 }
20382038
20392039 void addMemNoOffsetOperands(MCInst &Inst, unsigned N) const {
20402040 assert(N == 1 && "Invalid number of operands!");
2041 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2041 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
20422042 }
20432043
20442044 void addMemPCRelImm12Operands(MCInst &Inst, unsigned N) const {
20452045 assert(N == 1 && "Invalid number of operands!");
20462046 int32_t Imm = Memory.OffsetImm->getValue();
2047 Inst.addOperand(MCOperand::CreateImm(Imm));
2047 Inst.addOperand(MCOperand::createImm(Imm));
20482048 }
20492049
20502050 void addAdrLabelOperands(MCInst &Inst, unsigned N) const {
20542054 // If we have an immediate that's not a constant, treat it as a label
20552055 // reference needing a fixup.
20562056 if (!isa(getImm())) {
2057 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2057 Inst.addOperand(MCOperand::createExpr(getImm()));
20582058 return;
20592059 }
20602060
20612061 const MCConstantExpr *CE = dyn_cast(getImm());
20622062 int Val = CE->getValue();
2063 Inst.addOperand(MCOperand::CreateImm(Val));
2063 Inst.addOperand(MCOperand::createImm(Val));
20642064 }
20652065
20662066 void addAlignedMemoryOperands(MCInst &Inst, unsigned N) const {
20672067 assert(N == 2 && "Invalid number of operands!");
2068 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2069 Inst.addOperand(MCOperand::CreateImm(Memory.Alignment));
2068 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2069 Inst.addOperand(MCOperand::createImm(Memory.Alignment));
20702070 }
20712071
20722072 void addDupAlignedMemoryNoneOperands(MCInst &Inst, unsigned N) const {
21282128 Val = ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
21292129 Memory.ShiftImm, Memory.ShiftType);
21302130 }
2131 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2132 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2133 Inst.addOperand(MCOperand::CreateImm(Val));
2131 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2132 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2133 Inst.addOperand(MCOperand::createImm(Val));
21342134 }
21352135
21362136 void addAM2OffsetImmOperands(MCInst &Inst, unsigned N) const {
21432143 if (Val == INT32_MIN) Val = 0;
21442144 if (Val < 0) Val = -Val;
21452145 Val = ARM_AM::getAM2Opc(AddSub, Val, ARM_AM::no_shift);
2146 Inst.addOperand(MCOperand::CreateReg(0));
2147 Inst.addOperand(MCOperand::CreateImm(Val));
2146 Inst.addOperand(MCOperand::createReg(0));
2147 Inst.addOperand(MCOperand::createImm(Val));
21482148 }
21492149
21502150 void addAddrMode3Operands(MCInst &Inst, unsigned N) const {
21532153 // reference needing a fixup. If it is a constant, it's something else
21542154 // and we reject it.
21552155 if (isImm()) {
2156 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2157 Inst.addOperand(MCOperand::CreateReg(0));
2158 Inst.addOperand(MCOperand::CreateImm(0));
2156 Inst.addOperand(MCOperand::createExpr(getImm()));
2157 Inst.addOperand(MCOperand::createReg(0));
2158 Inst.addOperand(MCOperand::createImm(0));
21592159 return;
21602160 }
21612161
21712171 // here.
21722172 Val = ARM_AM::getAM3Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add, 0);
21732173 }
2174 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2175 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2176 Inst.addOperand(MCOperand::CreateImm(Val));
2174 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2175 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2176 Inst.addOperand(MCOperand::createImm(Val));
21772177 }
21782178
21792179 void addAM3OffsetOperands(MCInst &Inst, unsigned N) const {
21812181 if (Kind == k_PostIndexRegister) {
21822182 int32_t Val =
21832183 ARM_AM::getAM3Opc(PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub, 0);
2184 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2185 Inst.addOperand(MCOperand::CreateImm(Val));
2184 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2185 Inst.addOperand(MCOperand::createImm(Val));
21862186 return;
21872187 }
21882188
21942194 if (Val == INT32_MIN) Val = 0;
21952195 if (Val < 0) Val = -Val;
21962196 Val = ARM_AM::getAM3Opc(AddSub, Val);
2197 Inst.addOperand(MCOperand::CreateReg(0));
2198 Inst.addOperand(MCOperand::CreateImm(Val));
2197 Inst.addOperand(MCOperand::createReg(0));
2198 Inst.addOperand(MCOperand::createImm(Val));
21992199 }
22002200
22012201 void addAddrMode5Operands(MCInst &Inst, unsigned N) const {
22042204 // reference needing a fixup. If it is a constant, it's something else
22052205 // and we reject it.
22062206 if (isImm()) {
2207 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2208 Inst.addOperand(MCOperand::CreateImm(0));
2207 Inst.addOperand(MCOperand::createExpr(getImm()));
2208 Inst.addOperand(MCOperand::createImm(0));
22092209 return;
22102210 }
22112211
22162216 if (Val == INT32_MIN) Val = 0;
22172217 if (Val < 0) Val = -Val;
22182218 Val = ARM_AM::getAM5Opc(AddSub, Val);
2219 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2220 Inst.addOperand(MCOperand::CreateImm(Val));
2219 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2220 Inst.addOperand(MCOperand::createImm(Val));
22212221 }
22222222
22232223 void addMemImm8s4OffsetOperands(MCInst &Inst, unsigned N) const {
22262226 // reference needing a fixup. If it is a constant, it's something else
22272227 // and we reject it.
22282228 if (isImm()) {
2229 Inst.addOperand(MCOperand::CreateExpr(getImm()));
2230 Inst.addOperand(MCOperand::CreateImm(0));
2229 Inst.addOperand(MCOperand::createExpr(getImm()));
2230 Inst.addOperand(MCOperand::createImm(0));
22312231 return;
22322232 }
22332233
22342234 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2235 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2236 Inst.addOperand(MCOperand::CreateImm(Val));
2235 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2236 Inst.addOperand(MCOperand::createImm(Val));
22372237 }
22382238
22392239 void addMemImm0_1020s4OffsetOperands(MCInst &Inst, unsigned N) const {
22402240 assert(N == 2 && "Invalid number of operands!");
22412241 // The lower two bits are always zero and as such are not encoded.
22422242 int32_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() / 4 : 0;
2243 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2244 Inst.addOperand(MCOperand::CreateImm(Val));
2243 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2244 Inst.addOperand(MCOperand::createImm(Val));
22452245 }
22462246
22472247 void addMemImm8OffsetOperands(MCInst &Inst, unsigned N) const {
22482248 assert(N == 2 && "Invalid number of operands!");
22492249 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2250 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2251 Inst.addOperand(MCOperand::CreateImm(Val));
2250 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2251 Inst.addOperand(MCOperand::createImm(Val));
22522252 }
22532253
22542254 void addMemPosImm8OffsetOperands(MCInst &Inst, unsigned N) const {
22642264 // If this is an immediate, it's a label reference.
22652265 if (isImm()) {
22662266 addExpr(Inst, getImm());
2267 Inst.addOperand(MCOperand::CreateImm(0));
2267 Inst.addOperand(MCOperand::createImm(0));
22682268 return;
22692269 }
22702270
22712271 // Otherwise, it's a normal memory reg+offset.
22722272 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2273 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2274 Inst.addOperand(MCOperand::CreateImm(Val));
2273 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2274 Inst.addOperand(MCOperand::createImm(Val));
22752275 }
22762276
22772277 void addMemImm12OffsetOperands(MCInst &Inst, unsigned N) const {
22792279 // If this is an immediate, it's a label reference.
22802280 if (isImm()) {
22812281 addExpr(Inst, getImm());
2282 Inst.addOperand(MCOperand::CreateImm(0));
2282 Inst.addOperand(MCOperand::createImm(0));
22832283 return;
22842284 }
22852285
22862286 // Otherwise, it's a normal memory reg+offset.
22872287 int64_t Val = Memory.OffsetImm ? Memory.OffsetImm->getValue() : 0;
2288 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2289 Inst.addOperand(MCOperand::CreateImm(Val));
2288 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2289 Inst.addOperand(MCOperand::createImm(Val));
22902290 }
22912291
22922292 void addMemTBBOperands(MCInst &Inst, unsigned N) const {
22932293 assert(N == 2 && "Invalid number of operands!");
2294 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2295 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2294 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2295 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
22962296 }
22972297
22982298 void addMemTBHOperands(MCInst &Inst, unsigned N) const {
22992299 assert(N == 2 && "Invalid number of operands!");
2300 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2301 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2300 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2301 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
23022302 }
23032303
23042304 void addMemRegOffsetOperands(MCInst &Inst, unsigned N) const {
23062306 unsigned Val =
23072307 ARM_AM::getAM2Opc(Memory.isNegative ? ARM_AM::sub : ARM_AM::add,
23082308 Memory.ShiftImm, Memory.ShiftType);
2309 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2310 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2311 Inst.addOperand(MCOperand::CreateImm(Val));
2309 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2310 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2311 Inst.addOperand(MCOperand::createImm(Val));
23122312 }
23132313
23142314 void addT2MemRegOffsetOperands(MCInst &Inst, unsigned N) const {
23152315 assert(N == 3 && "Invalid number of operands!");
2316 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2317 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2318 Inst.addOperand(MCOperand::CreateImm(Memory.ShiftImm));
2316 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2317 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
2318 Inst.addOperand(MCOperand::createImm(Memory.ShiftImm));
23192319 }
23202320
23212321 void addMemThumbRROperands(MCInst &Inst, unsigned N) const {
23222322 assert(N == 2 && "Invalid number of operands!");
2323 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2324 Inst.addOperand(MCOperand::CreateReg(Memory.OffsetRegNum));
2323 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2324 Inst.addOperand(MCOperand::createReg(Memory.OffsetRegNum));
23252325 }
23262326
23272327 void addMemThumbRIs4Operands(MCInst &Inst, unsigned N) const {
23282328 assert(N == 2 && "Invalid number of operands!");
23292329 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2330 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2331 Inst.addOperand(MCOperand::CreateImm(Val));
2330 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2331 Inst.addOperand(MCOperand::createImm(Val));
23322332 }
23332333
23342334 void addMemThumbRIs2Operands(MCInst &Inst, unsigned N) const {
23352335 assert(N == 2 && "Invalid number of operands!");
23362336 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 2) : 0;
2337 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2338 Inst.addOperand(MCOperand::CreateImm(Val));
2337 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2338 Inst.addOperand(MCOperand::createImm(Val));
23392339 }
23402340
23412341 void addMemThumbRIs1Operands(MCInst &Inst, unsigned N) const {
23422342 assert(N == 2 && "Invalid number of operands!");
23432343 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue()) : 0;
2344 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2345 Inst.addOperand(MCOperand::CreateImm(Val));
2344 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2345 Inst.addOperand(MCOperand::createImm(Val));
23462346 }
23472347
23482348 void addMemThumbSPIOperands(MCInst &Inst, unsigned N) const {
23492349 assert(N == 2 && "Invalid number of operands!");
23502350 int64_t Val = Memory.OffsetImm ? (Memory.OffsetImm->getValue() / 4) : 0;
2351 Inst.addOperand(MCOperand::CreateReg(Memory.BaseRegNum));
2352 Inst.addOperand(MCOperand::CreateImm(Val));
2351 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum));
2352 Inst.addOperand(MCOperand::createImm(Val));
23532353 }
23542354
23552355 void addPostIdxImm8Operands(MCInst &Inst, unsigned N) const {
23602360 bool isAdd = Imm >= 0;
23612361 if (Imm == INT32_MIN) Imm = 0;
23622362 Imm = (Imm < 0 ? -Imm : Imm) | (int)isAdd << 8;
2363 Inst.addOperand(MCOperand::CreateImm(Imm));
2363 Inst.addOperand(MCOperand::createImm(Imm));
23642364 }
23652365
23662366 void addPostIdxImm8s4Operands(MCInst &Inst, unsigned N) const {
23722372 if (Imm == INT32_MIN) Imm = 0;
23732373 // Immediate is scaled by 4.
23742374 Imm = ((Imm < 0 ? -Imm : Imm) / 4) | (int)isAdd << 8;
2375 Inst.addOperand(MCOperand::CreateImm(Imm));
2375 Inst.addOperand(MCOperand::createImm(Imm));
23762376 }
23772377
23782378 void addPostIdxRegOperands(MCInst &Inst, unsigned N) const {
23792379 assert(N == 2 && "Invalid number of operands!");
2380 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2381 Inst.addOperand(MCOperand::CreateImm(PostIdxReg.isAdd));
2380 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
2381 Inst.addOperand(MCOperand::createImm(PostIdxReg.isAdd));
23822382 }
23832383
23842384 void addPostIdxRegShiftedOperands(MCInst &Inst, unsigned N) const {
23852385 assert(N == 2 && "Invalid number of operands!");
2386 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum));
2386 Inst.addOperand(MCOperand::createReg(PostIdxReg.RegNum));
23872387 // The sign, shift type, and shift amount are encoded in a single operand
23882388 // using the AM2 encoding helpers.
23892389 ARM_AM::AddrOpc opc = PostIdxReg.isAdd ? ARM_AM::add : ARM_AM::sub;
23902390 unsigned Imm = ARM_AM::getAM2Opc(opc, PostIdxReg.ShiftImm,
23912391 PostIdxReg.ShiftTy);
2392 Inst.addOperand(MCOperand::CreateImm(Imm));
2392 Inst.addOperand(MCOperand::createImm(Imm));
23932393 }
23942394
23952395 void addMSRMaskOperands(MCInst &Inst, unsigned N) const {
23962396 assert(N == 1 && "Invalid number of operands!");
2397 Inst.addOperand(MCOperand::CreateImm(unsigned(getMSRMask())));
2397 Inst.addOperand(MCOperand::createImm(unsigned(getMSRMask())));
23982398 }
23992399
24002400 void addBankedRegOperands(MCInst &Inst, unsigned N) const {
24012401 assert(N == 1 && "Invalid number of operands!");
2402 Inst.addOperand(MCOperand::CreateImm(unsigned(getBankedReg())));
2402 Inst.addOperand(MCOperand::createImm(unsigned(getBankedReg())));
24032403 }
24042404
24052405 void addProcIFlagsOperands(MCInst &Inst, unsigned N) const {
24062406 assert(N == 1 && "Invalid number of operands!");
2407 Inst.addOperand(MCOperand::CreateImm(unsigned(getProcIFlags())));
2407 Inst.addOperand(MCOperand::createImm(unsigned(getProcIFlags())));
24082408 }
24092409
24102410 void addVecListOperands(MCInst &Inst, unsigned N) const {
24112411 assert(N == 1 && "Invalid number of operands!");
2412 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2412 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
24132413 }
24142414
24152415 void addVecListIndexedOperands(MCInst &Inst, unsigned N) const {
24162416 assert(N == 2 && "Invalid number of operands!");
2417 Inst.addOperand(MCOperand::CreateReg(VectorList.RegNum));
2418 Inst.addOperand(MCOperand::CreateImm(VectorList.LaneIndex));
2417 Inst.addOperand(MCOperand::createReg(VectorList.RegNum));
2418 Inst.addOperand(MCOperand::createImm(VectorList.LaneIndex));
24192419 }
24202420
24212421 void addVectorIndex8Operands(MCInst &Inst, unsigned N) const {
24222422 assert(N == 1 && "Invalid number of operands!");
2423 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2423 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
24242424 }
24252425
24262426 void addVectorIndex16Operands(MCInst &Inst, unsigned N) const {
24272427 assert(N == 1 && "Invalid number of operands!");
2428 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2428 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
24292429 }
24302430
24312431 void addVectorIndex32Operands(MCInst &Inst, unsigned N) const {
24322432 assert(N == 1 && "Invalid number of operands!");
2433 Inst.addOperand(MCOperand::CreateImm(getVectorIndex()));
2433 Inst.addOperand(MCOperand::createImm(getVectorIndex()));
24342434 }
24352435
24362436 void addNEONi8splatOperands(MCInst &Inst, unsigned N) const {
24382438 // The immediate encodes the type of constant as well as the value.
24392439 // Mask in that this is an i8 splat.
24402440 const MCConstantExpr *CE = dyn_cast(getImm());
2441 Inst.addOperand(MCOperand::CreateImm(CE->getValue() | 0xe00));
2441 Inst.addOperand(MCOperand::createImm(CE->getValue() | 0xe00));
24422442 }
24432443
24442444 void addNEONi16splatOperands(MCInst &Inst, unsigned N) const {
24472447 const MCConstantExpr *CE = dyn_cast(getImm());
24482448 unsigned Value = CE->getValue();
24492449 Value = ARM_AM::encodeNEONi16splat(Value);
2450 Inst.addOperand(MCOperand::CreateImm(Value));
2450 Inst.addOperand(MCOperand::createImm(Value));
24512451 }
24522452
24532453 void addNEONi16splatNotOperands(MCInst &Inst, unsigned N) const {
24562456 const MCConstantExpr *CE = dyn_cast(getImm());
24572457 unsigned Value = CE->getValue();
24582458 Value = ARM_AM::encodeNEONi16splat(~Value & 0xffff);
2459 Inst.addOperand(MCOperand::CreateImm(Value));
2459 Inst.addOperand(MCOperand::createImm(Value));
24602460 }
24612461
24622462 void addNEONi32splatOperands(MCInst &Inst, unsigned N) const {
24652465 const MCConstantExpr *CE = dyn_cast(getImm());
24662466 unsigned Value = CE->getValue();
24672467 Value = ARM_AM::encodeNEONi32splat(Value);
2468 Inst.addOperand(MCOperand::CreateImm(Value));
2468 Inst.addOperand(MCOperand::createImm(Value));
24692469 }
24702470
24712471 void addNEONi32splatNotOperands(MCInst &Inst, unsigned N) const {
24742474 const MCConstantExpr *CE = dyn_cast(getImm());
24752475 unsigned Value = CE->getValue();
24762476 Value = ARM_AM::encodeNEONi32splat(~Value);
2477 Inst.addOperand(MCOperand::CreateImm(Value));
2477 Inst.addOperand(MCOperand::createImm(Value));
24782478 }
24792479
24802480 void addNEONinvByteReplicateOperands(MCInst &Inst, unsigned N) const {
24882488 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
24892489 unsigned B = ((~Value) & 0xff);
24902490 B |= 0xe00; // cmode = 0b1110
2491 Inst.addOperand(MCOperand::CreateImm(B));
2491 Inst.addOperand(MCOperand::createImm(B));
24922492 }
24932493 void addNEONi32vmovOperands(MCInst &Inst, unsigned N) const {
24942494 assert(N == 1 && "Invalid number of operands!");
25012501 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
25022502 else if (Value > 0xffffff)
25032503 Value = (Value >> 24) | 0x600;
2504 Inst.addOperand(MCOperand::CreateImm(Value));
2504 Inst.addOperand(MCOperand::createImm(Value));
25052505 }
25062506
25072507 void addNEONvmovByteReplicateOperands(MCInst &Inst, unsigned N) const {
25152515 "always must be replaced with VMOVv8i8 or VMOVv16i8.");
25162516 unsigned B = Value & 0xff;
25172517 B |= 0xe00; // cmode = 0b1110
2518 Inst.addOperand(MCOperand::CreateImm(B));
2518 Inst.addOperand(MCOperand::createImm(B));
25192519 }
25202520 void addNEONi32vmovNegOperands(MCInst &Inst, unsigned N) const {
25212521 assert(N == 1 && "Invalid number of operands!");
25282528 Value = (Value >> 16) | ((Value & 0xff) ? 0xd00 : 0x400);
25292529 else if (Value > 0xffffff)
25302530 Value = (Value >> 24) | 0x600;
2531 Inst.addOperand(MCOperand::CreateImm(Value));
2531 Inst.addOperand(MCOperand::createImm(Value));
25322532 }
25332533
25342534 void addNEONi64splatOperands(MCInst &Inst, unsigned N) const {
25402540 for (unsigned i = 0; i < 8; ++i, Value >>= 8) {
25412541 Imm |= (Value & 1) << i;
25422542 }
2543 Inst.addOperand(MCOperand::CreateImm(Imm | 0x1e00));
2543 Inst.addOperand(MCOperand::createImm(Imm | 0x1e00));
25442544 }
25452545
25462546 void print(raw_ostream &OS) const override;
67046704 TmpInst.addOperand(Inst.getOperand(0));
67056705 TmpInst.addOperand(Inst.getOperand(1));
67066706 TmpInst.addOperand(Inst.getOperand(1));
6707 TmpInst.addOperand(MCOperand::CreateReg(0));
6708 TmpInst.addOperand(MCOperand::CreateImm(0));
6707 TmpInst.addOperand(MCOperand::createReg(0));
6708 TmpInst.addOperand(MCOperand::createImm(0));
67096709 TmpInst.addOperand(Inst.getOperand(2));
67106710 TmpInst.addOperand(Inst.getOperand(3));
67116711 Inst = TmpInst;
67226722 TmpInst.addOperand(Inst.getOperand(1));
67236723 TmpInst.addOperand(Inst.getOperand(0));
67246724 TmpInst.addOperand(Inst.getOperand(1));
6725 TmpInst.addOperand(MCOperand::CreateReg(0));
6726 TmpInst.addOperand(MCOperand::CreateImm(0));
6725 TmpInst.addOperand(MCOperand::createReg(0));
6726 TmpInst.addOperand(MCOperand::createImm(0));
67276727 TmpInst.addOperand(Inst.getOperand(2));
67286728 TmpInst.addOperand(Inst.getOperand(3));
67296729 Inst = TmpInst;
67426742 // Immediate (mod_imm) will be in its encoded form, we must unencode it
67436743 // before passing it to the ADR instruction.
67446744 unsigned Enc = Inst.getOperand(2).getImm();
6745 TmpInst.addOperand(MCOperand::CreateImm(
6745 TmpInst.addOperand(MCOperand::createImm(
67466746 ARM_AM::rotr32(Enc & 0xFF, (Enc & 0xF00) >> 7)));
67476747 } else {
67486748 // Turn PC-relative expression into absolute expression.
67596759 getContext());
67606760 const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
67616761 getContext());
6762 TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
6762 TmpInst.addOperand(MCOperand::createExpr(FixupAddr));
67636763 }
67646764 TmpInst.addOperand(Inst.getOperand(3));
67656765 TmpInst.addOperand(Inst.getOperand(4));
68256825 TmpInst.addOperand(Inst.getOperand(3)); // alignment
68266826 TmpInst.addOperand(Inst.getOperand(4)); // Rm
68276827 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6828 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6828 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
68296829 Spacing));
68306830 TmpInst.addOperand(Inst.getOperand(1)); // lane
68316831 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
68496849 TmpInst.addOperand(Inst.getOperand(3)); // alignment
68506850 TmpInst.addOperand(Inst.getOperand(4)); // Rm
68516851 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6852 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6852 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
68536853 Spacing));
6854 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6854 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
68556855 Spacing * 2));
68566856 TmpInst.addOperand(Inst.getOperand(1)); // lane
68576857 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
68756875 TmpInst.addOperand(Inst.getOperand(3)); // alignment
68766876 TmpInst.addOperand(Inst.getOperand(4)); // Rm
68776877 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6878 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6878 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
68796879 Spacing));
6880 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6880 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
68816881 Spacing * 2));
6882 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6882 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
68836883 Spacing * 3));
68846884 TmpInst.addOperand(Inst.getOperand(1)); // lane
68856885 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
68996899 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
69006900 TmpInst.addOperand(Inst.getOperand(2)); // Rn
69016901 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6902 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6902 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
69036903 TmpInst.addOperand(Inst.getOperand(0)); // Vd
69046904 TmpInst.addOperand(Inst.getOperand(1)); // lane
69056905 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
69216921 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
69226922 TmpInst.addOperand(Inst.getOperand(2)); // Rn
69236923 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6924 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6924 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
69256925 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6926 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6926 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
69276927 Spacing));
69286928 TmpInst.addOperand(Inst.getOperand(1)); // lane
69296929 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
69456945 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
69466946 TmpInst.addOperand(Inst.getOperand(2)); // Rn
69476947 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6948 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6948 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
69496949 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6950 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6950 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
69516951 Spacing));
6952 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6952 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
69536953 Spacing * 2));
69546954 TmpInst.addOperand(Inst.getOperand(1)); // lane
69556955 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
69716971 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
69726972 TmpInst.addOperand(Inst.getOperand(2)); // Rn
69736973 TmpInst.addOperand(Inst.getOperand(3)); // alignment
6974 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
6974 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
69756975 TmpInst.addOperand(Inst.getOperand(0)); // Vd
6976 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6976 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
69776977 Spacing));
6978 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6978 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
69796979 Spacing * 2));
6980 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
6980 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
69816981 Spacing * 3));
69826982 TmpInst.addOperand(Inst.getOperand(1)); // lane
69836983 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
70177017 TmpInst.addOperand(Inst.getOperand(2)); // Rn
70187018 TmpInst.addOperand(Inst.getOperand(3)); // alignment
70197019 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7020 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7020 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
70217021 Spacing));
70227022 TmpInst.addOperand(Inst.getOperand(1)); // lane
70237023 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
70397039 TmpInst.addOperand(Inst.getOperand(2)); // Rn
70407040 TmpInst.addOperand(Inst.getOperand(3)); // alignment
70417041 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7042 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7042 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
70437043 Spacing));
7044 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7044 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
70457045 Spacing * 2));
70467046 TmpInst.addOperand(Inst.getOperand(1)); // lane
70477047 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
70637063 TmpInst.addOperand(Inst.getOperand(2)); // Rn
70647064 TmpInst.addOperand(Inst.getOperand(3)); // alignment
70657065 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7066 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7066 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
70677067 Spacing));
7068 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7068 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
70697069 Spacing * 2));
7070 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7070 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
70717071 Spacing * 3));
70727072 TmpInst.addOperand(Inst.getOperand(1)); // lane
70737073 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
71097109 unsigned Spacing;
71107110 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
71117111 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7112 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7112 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71137113 Spacing));
71147114 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
71157115 TmpInst.addOperand(Inst.getOperand(2)); // Rn
71167116 TmpInst.addOperand(Inst.getOperand(3)); // alignment
71177117 TmpInst.addOperand(Inst.getOperand(4)); // Rm
71187118 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7119 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7119 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71207120 Spacing));
71217121 TmpInst.addOperand(Inst.getOperand(1)); // lane
71227122 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
71367136 unsigned Spacing;
71377137 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
71387138 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7139 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7139 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71407140 Spacing));
7141 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7141 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71427142 Spacing * 2));
71437143 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
71447144 TmpInst.addOperand(Inst.getOperand(2)); // Rn
71457145 TmpInst.addOperand(Inst.getOperand(3)); // alignment
71467146 TmpInst.addOperand(Inst.getOperand(4)); // Rm
71477147 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7148 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7148 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71497149 Spacing));
7150 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7150 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71517151 Spacing * 2));
71527152 TmpInst.addOperand(Inst.getOperand(1)); // lane
71537153 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
71677167 unsigned Spacing;
71687168 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
71697169 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7170 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7170 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71717171 Spacing));
7172 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7172 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71737173 Spacing * 2));
7174 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7174 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71757175 Spacing * 3));
71767176 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
71777177 TmpInst.addOperand(Inst.getOperand(2)); // Rn
71787178 TmpInst.addOperand(Inst.getOperand(3)); // alignment
71797179 TmpInst.addOperand(Inst.getOperand(4)); // Rm
71807180 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7181 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7181 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71827182 Spacing));
7183 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7183 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71847184 Spacing * 2));
7185 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7185 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
71867186 Spacing * 3));
71877187 TmpInst.addOperand(Inst.getOperand(1)); // lane
71887188 TmpInst.addOperand(Inst.getOperand(5)); // CondCode
72037203 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
72047204 TmpInst.addOperand(Inst.getOperand(2)); // Rn
72057205 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7206 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7206 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
72077207 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
72087208 TmpInst.addOperand(Inst.getOperand(1)); // lane
72097209 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
72237223 unsigned Spacing;
72247224 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
72257225 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7226 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7226 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72277227 Spacing));
72287228 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
72297229 TmpInst.addOperand(Inst.getOperand(2)); // Rn
72307230 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7231 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7231 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
72327232 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7233 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7233 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72347234 Spacing));
72357235 TmpInst.addOperand(Inst.getOperand(1)); // lane
72367236 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
72507250 unsigned Spacing;
72517251 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
72527252 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7253 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7253 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72547254 Spacing));
7255 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7255 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72567256 Spacing * 2));
72577257 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
72587258 TmpInst.addOperand(Inst.getOperand(2)); // Rn
72597259 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7260 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7260 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
72617261 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7262 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7262 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72637263 Spacing));
7264 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7264 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72657265 Spacing * 2));
72667266 TmpInst.addOperand(Inst.getOperand(1)); // lane
72677267 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
72817281 unsigned Spacing;
72827282 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
72837283 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7284 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7284 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72857285 Spacing));
7286 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7286 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72877287 Spacing * 2));
7288 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7288 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72897289 Spacing * 3));
72907290 TmpInst.addOperand(Inst.getOperand(2)); // Rn_wb
72917291 TmpInst.addOperand(Inst.getOperand(2)); // Rn
72927292 TmpInst.addOperand(Inst.getOperand(3)); // alignment
7293 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7293 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
72947294 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7295 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7295 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72967296 Spacing));
7297 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7297 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
72987298 Spacing * 2));
7299 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7299 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73007300 Spacing * 3));
73017301 TmpInst.addOperand(Inst.getOperand(1)); // lane
73027302 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
73357335 unsigned Spacing;
73367336 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
73377337 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7338 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7338 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73397339 Spacing));
73407340 TmpInst.addOperand(Inst.getOperand(2)); // Rn
73417341 TmpInst.addOperand(Inst.getOperand(3)); // alignment
73427342 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7343 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7343 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73447344 Spacing));
73457345 TmpInst.addOperand(Inst.getOperand(1)); // lane
73467346 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
73607360 unsigned Spacing;
73617361 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
73627362 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7363 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7363 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73647364 Spacing));
7365 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7365 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73667366 Spacing * 2));
73677367 TmpInst.addOperand(Inst.getOperand(2)); // Rn
73687368 TmpInst.addOperand(Inst.getOperand(3)); // alignment
73697369 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7370 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7370 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73717371 Spacing));
7372 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7372 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73737373 Spacing * 2));
73747374 TmpInst.addOperand(Inst.getOperand(1)); // lane
73757375 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
73897389 unsigned Spacing;
73907390 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
73917391 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7392 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7392 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73937393 Spacing));
7394 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7394 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73957395 Spacing * 2));
7396 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7396 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
73977397 Spacing * 3));
73987398 TmpInst.addOperand(Inst.getOperand(2)); // Rn
73997399 TmpInst.addOperand(Inst.getOperand(3)); // alignment
74007400 TmpInst.addOperand(Inst.getOperand(0)); // Tied operand src (== Vd)
7401 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7401 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74027402 Spacing));
7403 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7403 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74047404 Spacing * 2));
7405 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7405 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74067406 Spacing * 3));
74077407 TmpInst.addOperand(Inst.getOperand(1)); // lane
74087408 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
74227422 unsigned Spacing;
74237423 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
74247424 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7425 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7425 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74267426 Spacing));
7427 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7427 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74287428 Spacing * 2));
74297429 TmpInst.addOperand(Inst.getOperand(1)); // Rn
74307430 TmpInst.addOperand(Inst.getOperand(2)); // alignment
74447444 unsigned Spacing;
74457445 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
74467446 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7447 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7447 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74487448 Spacing));
7449 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7449 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74507450 Spacing * 2));
74517451 TmpInst.addOperand(Inst.getOperand(1)); // Rn
74527452 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
74537453 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7454 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7454 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
74557455 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
74567456 TmpInst.addOperand(Inst.getOperand(4));
74577457 Inst = TmpInst;
74687468 unsigned Spacing;
74697469 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
74707470 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7471 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7471 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74727472 Spacing));
7473 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7473 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74747474 Spacing * 2));
74757475 TmpInst.addOperand(Inst.getOperand(1)); // Rn
74767476 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
74937493 unsigned Spacing;
74947494 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
74957495 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7496 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7496 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74977497 Spacing));
7498 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7498 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
74997499 Spacing * 2));
75007500 TmpInst.addOperand(Inst.getOperand(1)); // Rn
75017501 TmpInst.addOperand(Inst.getOperand(2)); // alignment
75157515 unsigned Spacing;
75167516 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
75177517 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7518 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7518 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75197519 Spacing));
7520 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7520 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75217521 Spacing * 2));
75227522 TmpInst.addOperand(Inst.getOperand(1)); // Rn
75237523 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
75247524 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7525 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7525 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
75267526 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
75277527 TmpInst.addOperand(Inst.getOperand(4));
75287528 Inst = TmpInst;
75397539 unsigned Spacing;
75407540 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
75417541 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7542 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7542 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75437543 Spacing));
7544 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7544 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75457545 Spacing * 2));
75467546 TmpInst.addOperand(Inst.getOperand(1)); // Rn
75477547 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
75647564 unsigned Spacing;
75657565 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
75667566 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7567 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7567 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75687568 Spacing));
7569 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7569 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75707570 Spacing * 2));
7571 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7571 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75727572 Spacing * 3));
75737573 TmpInst.addOperand(Inst.getOperand(1)); // Rn
75747574 TmpInst.addOperand(Inst.getOperand(2)); // alignment
75887588 unsigned Spacing;
75897589 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
75907590 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7591 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7591 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75927592 Spacing));
7593 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7593 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75947594 Spacing * 2));
7595 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7595 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
75967596 Spacing * 3));
75977597 TmpInst.addOperand(Inst.getOperand(1)); // Rn
75987598 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
75997599 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7600 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7600 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
76017601 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
76027602 TmpInst.addOperand(Inst.getOperand(4));
76037603 Inst = TmpInst;
76147614 unsigned Spacing;
76157615 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
76167616 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7617 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7617 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76187618 Spacing));
7619 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7619 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76207620 Spacing * 2));
7621 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7621 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76227622 Spacing * 3));
76237623 TmpInst.addOperand(Inst.getOperand(1)); // Rn
76247624 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
76417641 unsigned Spacing;
76427642 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
76437643 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7644 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7644 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76457645 Spacing));
7646 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7646 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76477647 Spacing * 2));
7648 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7648 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76497649 Spacing * 3));
76507650 TmpInst.addOperand(Inst.getOperand(1)); // Rn
76517651 TmpInst.addOperand(Inst.getOperand(2)); // alignment
76657665 unsigned Spacing;
76667666 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
76677667 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7668 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7668 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76697669 Spacing));
7670 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7670 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76717671 Spacing * 2));
7672 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7672 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76737673 Spacing * 3));
76747674 TmpInst.addOperand(Inst.getOperand(1)); // Rn
76757675 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
76767676 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7677 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7677 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
76787678 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
76797679 TmpInst.addOperand(Inst.getOperand(4));
76807680 Inst = TmpInst;
76917691 unsigned Spacing;
76927692 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
76937693 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7694 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7694 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76957695 Spacing));
7696 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7696 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76977697 Spacing * 2));
7698 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7698 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
76997699 Spacing * 3));
77007700 TmpInst.addOperand(Inst.getOperand(1)); // Rn
77017701 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
77207720 TmpInst.addOperand(Inst.getOperand(1)); // Rn
77217721 TmpInst.addOperand(Inst.getOperand(2)); // alignment
77227722 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7723 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7723 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77247724 Spacing));
7725 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7725 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77267726 Spacing * 2));
77277727 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
77287728 TmpInst.addOperand(Inst.getOperand(4));
77427742 TmpInst.addOperand(Inst.getOperand(1)); // Rn
77437743 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
77447744 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7745 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7745 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
77467746 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7747 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7747 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77487748 Spacing));
7749 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7749 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77507750 Spacing * 2));
77517751 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
77527752 TmpInst.addOperand(Inst.getOperand(4));
77687768 TmpInst.addOperand(Inst.getOperand(2)); // alignment
77697769 TmpInst.addOperand(Inst.getOperand(3)); // Rm
77707770 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7771 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7771 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77727772 Spacing));
7773 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7773 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77747774 Spacing * 2));
77757775 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
77767776 TmpInst.addOperand(Inst.getOperand(5));
77917791 TmpInst.addOperand(Inst.getOperand(1)); // Rn
77927792 TmpInst.addOperand(Inst.getOperand(2)); // alignment
77937793 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7794 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7794 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77957795 Spacing));
7796 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7796 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77977797 Spacing * 2));
7798 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7798 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
77997799 Spacing * 3));
78007800 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
78017801 TmpInst.addOperand(Inst.getOperand(4));
78157815 TmpInst.addOperand(Inst.getOperand(1)); // Rn
78167816 TmpInst.addOperand(Inst.getOperand(1)); // Rn_wb == tied Rn
78177817 TmpInst.addOperand(Inst.getOperand(2)); // alignment
7818 TmpInst.addOperand(MCOperand::CreateReg(0)); // Rm
7818 TmpInst.addOperand(MCOperand::createReg(0)); // Rm
78197819 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7820 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7820 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
78217821 Spacing));
7822 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7822 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
78237823 Spacing * 2));
7824 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7824 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
78257825 Spacing * 3));
78267826 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
78277827 TmpInst.addOperand(Inst.getOperand(4));
78437843 TmpInst.addOperand(Inst.getOperand(2)); // alignment
78447844 TmpInst.addOperand(Inst.getOperand(3)); // Rm
78457845 TmpInst.addOperand(Inst.getOperand(0)); // Vd
7846 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7846 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
78477847 Spacing));
7848 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7848 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
78497849 Spacing * 2));
7850 TmpInst.addOperand(MCOperand::CreateReg(Inst.getOperand(0).getReg() +
7850 TmpInst.addOperand(MCOperand::createReg(Inst.getOperand(0).getReg() +
78517851 Spacing * 3));
78527852 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
78537853 TmpInst.addOperand(Inst.getOperand(5));
79117911 TmpInst.setOpcode(newOpc);
79127912 TmpInst.addOperand(Inst.getOperand(0)); // Rd
79137913 if (isNarrow)
7914 TmpInst.addOperand(MCOperand::CreateReg(
7914 TmpInst.addOperand(MCOperand::createReg(
79157915 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
79167916 TmpInst.addOperand(Inst.getOperand(1)); // Rn
79177917 TmpInst.addOperand(Inst.getOperand(2)); // Rm
79187918 TmpInst.addOperand(Inst.getOperand(4)); // CondCode
79197919 TmpInst.addOperand(Inst.getOperand(5));
79207920 if (!isNarrow)
7921 TmpInst.addOperand(MCOperand::CreateReg(
7921 TmpInst.addOperand(MCOperand::createReg(
79227922 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
79237923 Inst = TmpInst;
79247924 return true;
79487948 TmpInst.setOpcode(newOpc);
79497949 TmpInst.addOperand(Inst.getOperand(0)); // Rd
79507950 if (isNarrow)
7951 TmpInst.addOperand(MCOperand::CreateReg(
7951 TmpInst.addOperand(MCOperand::createReg(
79527952 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
79537953 TmpInst.addOperand(Inst.getOperand(1)); // Rn
79547954 if (newOpc != ARM::t2RRX)
7955 TmpInst.addOperand(MCOperand::CreateImm(Amount));
7955 TmpInst.addOperand(MCOperand::createImm(Amount));
79567956 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
79577957 TmpInst.addOperand(Inst.getOperand(4));
79587958 if (!isNarrow)
7959 TmpInst.addOperand(MCOperand::CreateReg(
7959 TmpInst.addOperand(MCOperand::createReg(
79607960 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
79617961 Inst = TmpInst;
79627962 return true;
79807980 TmpInst.addOperand(Inst.getOperand(0)); // Rd
79817981 TmpInst.addOperand(Inst.getOperand(1)); // Rn
79827982 TmpInst.addOperand(Inst.getOperand(2)); // Rm
7983 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
7983 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
79847984 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
79857985 TmpInst.addOperand(Inst.getOperand(4));
79867986 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
80118011 TmpInst.addOperand(Inst.getOperand(0)); // Rd
80128012 TmpInst.addOperand(Inst.getOperand(1)); // Rn
80138013 if (Opc == ARM::MOVsi)
8014 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8014 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
80158015 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
80168016 TmpInst.addOperand(Inst.getOperand(4));
80178017 TmpInst.addOperand(Inst.getOperand(5)); // cc_out
80248024 TmpInst.setOpcode(ARM::MOVsi);
80258025 TmpInst.addOperand(Inst.getOperand(0)); // Rd
80268026 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8027 TmpInst.addOperand(MCOperand::CreateImm(Shifter)); // Shift value and ty
8027 TmpInst.addOperand(MCOperand::createImm(Shifter)); // Shift value and ty
80288028 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
80298029 TmpInst.addOperand(Inst.getOperand(3));
80308030 TmpInst.addOperand(Inst.getOperand(4)); // cc_out
80418041 TmpInst.addOperand(Inst.getOperand(4)); // Rt
80428042 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
80438043 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8044 TmpInst.addOperand(MCOperand::CreateImm(4));
8044 TmpInst.addOperand(MCOperand::createImm(4));
80458045 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
80468046 TmpInst.addOperand(Inst.getOperand(3));
80478047 Inst = TmpInst;
80578057 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
80588058 TmpInst.addOperand(Inst.getOperand(4)); // Rt
80598059 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8060 TmpInst.addOperand(MCOperand::CreateImm(-4));
8060 TmpInst.addOperand(MCOperand::createImm(-4));
80618061 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
80628062 TmpInst.addOperand(Inst.getOperand(3));
80638063 Inst = TmpInst;
80738073 TmpInst.addOperand(Inst.getOperand(4)); // Rt
80748074 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
80758075 TmpInst.addOperand(Inst.getOperand(1)); // Rn
8076 TmpInst.addOperand(MCOperand::CreateReg(0)); // am2offset
8077 TmpInst.addOperand(MCOperand::CreateImm(4));
8076 TmpInst.addOperand(MCOperand::createReg(0)); // am2offset
8077 TmpInst.addOperand(MCOperand::createImm(4));
80788078 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
80798079 TmpInst.addOperand(Inst.getOperand(3));
80808080 Inst = TmpInst;
80918091 TmpInst.addOperand(Inst.getOperand(0)); // Rn_wb
80928092 TmpInst.addOperand(Inst.getOperand(4)); // Rt
80938093 TmpInst.addOperand(Inst.getOperand(1)); // addrmode_imm12
8094 TmpInst.addOperand(MCOperand::CreateImm(-4));
8094 TmpInst.addOperand(MCOperand::createImm(-4));
80958095 TmpInst.addOperand(Inst.getOperand(2)); // CondCode
80968096 TmpInst.addOperand(Inst.getOperand(3));
80978097 Inst = TmpInst;
81048104 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
81058105 break;
81068106 Inst.setOpcode(ARM::t2ADDri);
8107 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8107 Inst.addOperand(MCOperand::createReg(0)); // cc_out
81088108 break;
81098109 case ARM::t2SUBri12:
81108110 // If the immediate fits for encoding T3 (t2SUBri) and the generic "sub"
81138113 ARM_AM::getT2SOImmVal(Inst.getOperand(2).getImm()) == -1)
81148114 break;
81158115 Inst.setOpcode(ARM::t2SUBri);
8116 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8116 Inst.addOperand(MCOperand::createReg(0)); // cc_out
81178117 break;
81188118 case ARM::tADDi8:
81198119 // If the immediate is in the range 0-7, we want tADDi3 iff Rd was
81868186 // same, we need to use the 32-bit encoding if it's available.
81878187 if (Inst.getOperand(0).getReg() != Inst.getOperand(2).getReg()) {
81888188 Inst.setOpcode(ARM::t2ADDrr);
8189 Inst.addOperand(MCOperand::CreateReg(0)); // cc_out
8189 Inst.addOperand(MCOperand::createReg(0)); // cc_out
81908190 return true;
81918191 }
81928192 break;
82398239 // the writeback tied operand.
82408240 if (hasWritebackToken)
82418241 Inst.insert(Inst.begin(),
8242 MCOperand::CreateReg(Inst.getOperand(0).getReg()));
8242 MCOperand::createReg(Inst.getOperand(0).getReg()));
82438243 return true;
82448244 }
82458245 break;
82688268 assert (isThumbTwo());
82698269 Inst.setOpcode(ARM::t2LDMIA_UPD);
82708270 // Add the base register and writeback operands.
8271 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8272 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8271 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8272 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
82738273 return true;
82748274 }
82758275 case ARM::tPUSH: {
82798279 assert (isThumbTwo());
82808280 Inst.setOpcode(ARM::t2STMDB_UPD);
82818281 // Add the base register and writeback operands.
8282 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8283 Inst.insert(Inst.begin(), MCOperand::CreateReg(ARM::SP));
8282 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
8283 Inst.insert(Inst.begin(), MCOperand::createReg(ARM::SP));
82848284 return true;
82858285 }
82868286 case ARM::t2MOVi: {
581581 if (I == MI.end()) break;
582582 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
583583 if (i > 0 && OpInfo[i-1].isPredicate()) continue;
584 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
584 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
585585 return;
586586 }
587587 }
588588
589 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
589 MI.insert(I, MCOperand::createReg(InITBlock ? 0 : ARM::CPSR));
590590 }
591591
592592 // Most Thumb instructions don't have explicit predicates in the
645645 for (unsigned i = 0; i < NumOps; ++i, ++I) {
646646 if (I == MI.end()) break;
647647 if (OpInfo[i].isPredicate()) {
648 I = MI.insert(I, MCOperand::CreateImm(CC));
648 I = MI.insert(I, MCOperand::createImm(CC));
649649 ++I;
650650 if (CC == ARMCC::AL)
651 MI.insert(I, MCOperand::CreateReg(0));
651 MI.insert(I, MCOperand::createReg(0));
652652 else
653 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
653 MI.insert(I, MCOperand::createReg(ARM::CPSR));
654654 return S;
655655 }
656656 }
657657
658 I = MI.insert(I, MCOperand::CreateImm(CC));
658 I = MI.insert(I, MCOperand::createImm(CC));
659659 ++I;
660660 if (CC == ARMCC::AL)
661 MI.insert(I, MCOperand::CreateReg(0));
661 MI.insert(I, MCOperand::createReg(0));
662662 else
663 MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
663 MI.insert(I, MCOperand::createReg(ARM::CPSR));
664664
665665 return S;
666666 }
893893 return MCDisassembler::Fail;
894894
895895 unsigned Register = GPRDecoderTable[RegNo];
896 Inst.addOperand(MCOperand::CreateReg(Register));
896 Inst.addOperand(MCOperand::createReg(Register));
897897 return MCDisassembler::Success;
898898 }
899899
917917
918918 if (RegNo == 15)
919919 {
920 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
920 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
921921 return MCDisassembler::Success;
922922 }
923923
948948 S = MCDisassembler::SoftFail;
949949
950950 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
951 Inst.addOperand(MCOperand::CreateReg(RegisterPair));
951 Inst.addOperand(MCOperand::createReg(RegisterPair));
952952 return S;
953953 }
954954
978978 return MCDisassembler::Fail;
979979 }
980980
981 Inst.addOperand(MCOperand::CreateReg(Register));
981 Inst.addOperand(MCOperand::createReg(Register));
982982 return MCDisassembler::Success;
983983 }
984984
10081008 return MCDisassembler::Fail;
10091009
10101010 unsigned Register = SPRDecoderTable[RegNo];
1011 Inst.addOperand(MCOperand::CreateReg(Register));
1011 Inst.addOperand(MCOperand::createReg(Register));
10121012 return MCDisassembler::Success;
10131013 }
10141014
10331033 return MCDisassembler::Fail;
10341034
10351035 unsigned Register = DPRDecoderTable[RegNo];
1036 Inst.addOperand(MCOperand::CreateReg(Register));
1036 Inst.addOperand(MCOperand::createReg(Register));
10371037 return MCDisassembler::Success;
10381038 }
10391039
10671067 RegNo >>= 1;
10681068
10691069 unsigned Register = QPRDecoderTable[RegNo];
1070 Inst.addOperand(MCOperand::CreateReg(Register));
1070 Inst.addOperand(MCOperand::createReg(Register));
10711071 return MCDisassembler::Success;
10721072 }
10731073
10861086 return MCDisassembler::Fail;
10871087
10881088 unsigned Register = DPairDecoderTable[RegNo];
1089 Inst.addOperand(MCOperand::CreateReg(Register));
1089 Inst.addOperand(MCOperand::createReg(Register));
10901090 return MCDisassembler::Success;
10911091 }
10921092
11091109 return MCDisassembler::Fail;
11101110
11111111 unsigned Register = DPairSpacedDecoderTable[RegNo];
1112 Inst.addOperand(MCOperand::CreateReg(Register));
1112 Inst.addOperand(MCOperand::createReg(Register));
11131113 return MCDisassembler::Success;
11141114 }
11151115
11191119 // AL predicate is not allowed on Thumb1 branches.
11201120 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
11211121 return MCDisassembler::Fail;
1122 Inst.addOperand(MCOperand::CreateImm(Val));
1122 Inst.addOperand(MCOperand::createImm(Val));
11231123 if (Val == ARMCC::AL) {
1124 Inst.addOperand(MCOperand::CreateReg(0));
1124 Inst.addOperand(MCOperand::createReg(0));
11251125 } else
1126 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1126 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
11271127 return MCDisassembler::Success;
11281128 }
11291129
11301130 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
11311131 uint64_t Address, const void *Decoder) {
11321132 if (Val)
1133 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
1133 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
11341134 else
1135 Inst.addOperand(MCOperand::CreateReg(0));
1135 Inst.addOperand(MCOperand::createReg(0));
11361136 return MCDisassembler::Success;
11371137 }
11381138
11681168 Shift = ARM_AM::rrx;
11691169
11701170 unsigned Op = Shift | (imm << 3);
1171 Inst.addOperand(MCOperand::CreateImm(Op));
1171 Inst.addOperand(MCOperand::createImm(Op));
11721172
11731173 return S;
11741174 }
12031203 break;
12041204 }
12051205
1206 Inst.addOperand(MCOperand::CreateImm(Shift));
1206 Inst.addOperand(MCOperand::createImm(Shift));
12071207
12081208 return S;
12091209 }
13171317 if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
13181318 uint32_t lsb_mask = (1U << lsb) - 1;
13191319
1320 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
1320 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
13211321 return S;
13221322 }
13231323
13771377 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
13781378 return MCDisassembler::Fail;
13791379
1380 Inst.addOperand(MCOperand::CreateImm(coproc));
1381 Inst.addOperand(MCOperand::CreateImm(CRd));
1380 Inst.addOperand(MCOperand::createImm(coproc));
1381 Inst.addOperand(MCOperand::createImm(CRd));
13821382 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
13831383 return MCDisassembler::Fail;
13841384
14161416 case ARM::STC_PRE:
14171417 case ARM::STCL_PRE:
14181418 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
1419 Inst.addOperand(MCOperand::CreateImm(imm));
1419 Inst.addOperand(MCOperand::createImm(imm));
14201420 break;
14211421 case ARM::t2LDC2_POST:
14221422 case ARM::t2LDC2L_POST:
14391439 default:
14401440 // The 'option' variant doesn't encode 'U' in the immediate since
14411441 // the immediate is unsigned [0,255].
1442 Inst.addOperand(MCOperand::CreateImm(imm));
1442 Inst.addOperand(MCOperand::createImm(imm));
14431443 break;
14441444 }
14451445
15631563 Opc = ARM_AM::rrx;
15641564 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
15651565
1566 Inst.addOperand(MCOperand::CreateImm(imm));
1566 Inst.addOperand(MCOperand::createImm(imm));
15671567 } else {
1568 Inst.addOperand(MCOperand::CreateReg(0));
1568 Inst.addOperand(MCOperand::createReg(0));
15691569 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
1570 Inst.addOperand(MCOperand::CreateImm(tmp));
1570 Inst.addOperand(MCOperand::createImm(tmp));
15711571 }
15721572
15731573 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
16141614 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
16151615 else
16161616 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
1617 Inst.addOperand(MCOperand::CreateImm(shift));
1617 Inst.addOperand(MCOperand::createImm(shift));
16181618
16191619 return S;
16201620 }
17971797 return MCDisassembler::Fail;
17981798
17991799 if (type) {
1800 Inst.addOperand(MCOperand::CreateReg(0));
1801 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm));
1800 Inst.addOperand(MCOperand::createReg(0));
1801 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
18021802 } else {
18031803 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
18041804 return MCDisassembler::Fail;
1805 Inst.addOperand(MCOperand::CreateImm(U));
1805 Inst.addOperand(MCOperand::createImm(U));
18061806 }
18071807
18081808 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
18331833 break;
18341834 }
18351835
1836 Inst.addOperand(MCOperand::CreateImm(mode));
1836 Inst.addOperand(MCOperand::createImm(mode));
18371837 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
18381838 return MCDisassembler::Fail;
18391839
19351935 return MCDisassembler::Fail;
19361936
19371937 Inst.addOperand(
1938 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
1938 MCOperand::createImm(fieldFromInstruction(Insn, 0, 4)));
19391939 return S;
19401940 }
19411941
19791979
19801980 if (imod && M) {
19811981 Inst.setOpcode(ARM::CPS3p);
1982 Inst.addOperand(MCOperand::CreateImm(imod));
1983 Inst.addOperand(MCOperand::CreateImm(iflags));
1984 Inst.addOperand(MCOperand::CreateImm(mode));
1982 Inst.addOperand(MCOperand::createImm(imod));
1983 Inst.addOperand(MCOperand::createImm(iflags));
1984 Inst.addOperand(MCOperand::createImm(mode));
19851985 } else if (imod && !M) {
19861986 Inst.setOpcode(ARM::CPS2p);
1987 Inst.addOperand(MCOperand::CreateImm(imod));
1988 Inst.addOperand(MCOperand::CreateImm(iflags));
1987 Inst.addOperand(MCOperand::createImm(imod));
1988 Inst.addOperand(MCOperand::createImm(iflags));
19891989 if (mode) S = MCDisassembler::SoftFail;
19901990 } else if (!imod && M) {
19911991 Inst.setOpcode(ARM::CPS1p);
1992 Inst.addOperand(MCOperand::CreateImm(mode));
1992 Inst.addOperand(MCOperand::createImm(mode));
19931993 if (iflags) S = MCDisassembler::SoftFail;
19941994 } else {
19951995 // imod == '00' && M == '0' --> UNPREDICTABLE
19961996 Inst.setOpcode(ARM::CPS1p);
1997 Inst.addOperand(MCOperand::CreateImm(mode));
1997 Inst.addOperand(MCOperand::createImm(mode));
19981998 S = MCDisassembler::SoftFail;
19991999 }
20002000
20192019
20202020 if (imod && M) {
20212021 Inst.setOpcode(ARM::t2CPS3p);
2022 Inst.addOperand(MCOperand::CreateImm(imod));
2023 Inst.addOperand(MCOperand::CreateImm(iflags));
2024 Inst.addOperand(MCOperand::CreateImm(mode));
2022 Inst.addOperand(MCOperand::createImm(imod));
2023 Inst.addOperand(MCOperand::createImm(iflags));
2024 Inst.addOperand(MCOperand::createImm(mode));
20252025 } else if (imod && !M) {
20262026 Inst.setOpcode(ARM::t2CPS2p);
2027 Inst.addOperand(MCOperand::CreateImm(imod));
2028 Inst.addOperand(MCOperand::CreateImm(iflags));
2027 Inst.addOperand(MCOperand::createImm(imod));
2028 Inst.addOperand(MCOperand::createImm(iflags));
20292029 if (mode) S = MCDisassembler::SoftFail;
20302030 } else if (!imod && M) {
20312031 Inst.setOpcode(ARM::t2CPS1p);
2032 Inst.addOperand(MCOperand::CreateImm(mode));
2032 Inst.addOperand(MCOperand::createImm(mode));
20332033 if (iflags) S = MCDisassembler::SoftFail;
20342034 } else {
20352035 // imod == '00' && M == '0' --> this is a HINT instruction
20372037 // HINT are defined only for immediate in [0..4]
20382038 if(imm > 4) return MCDisassembler::Fail;
20392039 Inst.setOpcode(ARM::t2HINT);
2040 Inst.addOperand(MCOperand::CreateImm(imm));
2040 Inst.addOperand(MCOperand::createImm(imm));
20412041 }
20422042
20432043 return S;
20622062 return MCDisassembler::Fail;
20632063
20642064 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2065 Inst.addOperand(MCOperand::CreateImm(imm));
2065 Inst.addOperand(MCOperand::createImm(imm));
20662066
20672067 return S;
20682068 }
20862086 return MCDisassembler::Fail;
20872087
20882088