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Push methods into base class in preparation for sharing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75020 91177308-0d34-0410-b5e6-96231b3b80d8 David Goodwin 11 years ago
8 changed file(s) with 605 addition(s) and 598 deletion(s). Raw diff Collapse all Expand all
1212
1313 #include "ARM.h"
1414 #include "ARMAddressingModes.h"
15 #include "ARMBaseInstrInfo.h"
1516 #include "ARMBaseRegisterInfo.h"
1617 #include "ARMInstrInfo.h"
1718 #include "ARMMachineFunctionInfo.h"
146147 }
147148 }
148149
149 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const TargetInstrInfo &tii,
150 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
150151 const ARMSubtarget &sti)
151152 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
152153 TII(tii), STI(sti),
860861 return 0;
861862 }
862863
864
865 static inline
866 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
867 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
868 }
869
870 static inline
871 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
872 return MIB.addReg(0);
873 }
874
875 /// emitLoadConstPool - Emits a load from constpool to materialize the
876 /// specified immediate.
877 void ARMBaseRegisterInfo::
878 emitLoadConstPool(MachineBasicBlock &MBB,
879 MachineBasicBlock::iterator &MBBI,
880 const TargetInstrInfo *TII, DebugLoc dl,
881 unsigned DestReg, int Val,
882 ARMCC::CondCodes Pred,
883 unsigned PredReg) const {
884 MachineFunction &MF = *MBB.getParent();
885 MachineConstantPool *ConstantPool = MF.getConstantPool();
886 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
887 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
888
889 BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
890 .addConstantPoolIndex(Idx)
891 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
892 }
893
894 bool ARMBaseRegisterInfo::
895 requiresRegisterScavenging(const MachineFunction &MF) const {
896 return true;
897 }
898
899 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
900 // not required, we reserve argument space for call sites in the function
901 // immediately on entry to the current function. This eliminates the need for
902 // add/sub sp brackets around call sites. Returns true if the call frame is
903 // included as part of the stack frame.
904 bool ARMBaseRegisterInfo::
905 hasReservedCallFrame(MachineFunction &MF) const {
906 const MachineFrameInfo *FFI = MF.getFrameInfo();
907 unsigned CFSize = FFI->getMaxCallFrameSize();
908 // It's not always a good idea to include the call frame as part of the
909 // stack frame. ARM (especially Thumb) has small immediate offset to
910 // address the stack frame. So a large call frame can cause poor codegen
911 // and may even makes it impossible to scavenge a register.
912 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
913 return false;
914
915 return !MF.getFrameInfo()->hasVarSizedObjects();
916 }
917
918 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
919 /// a destreg = basereg + immediate in ARM code.
920 static
921 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
922 MachineBasicBlock::iterator &MBBI,
923 unsigned DestReg, unsigned BaseReg, int NumBytes,
924 ARMCC::CondCodes Pred, unsigned PredReg,
925 const TargetInstrInfo &TII,
926 DebugLoc dl) {
927 bool isSub = NumBytes < 0;
928 if (isSub) NumBytes = -NumBytes;
929
930 while (NumBytes) {
931 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
932 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
933 assert(ThisVal && "Didn't extract field correctly");
934
935 // We will handle these bits from offset, clear them.
936 NumBytes &= ~ThisVal;
937
938 // Get the properly encoded SOImmVal field.
939 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
940 assert(SOImmVal != -1 && "Bit extraction didn't work?");
941
942 // Build the new ADD / SUB.
943 BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
944 .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
945 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
946 BaseReg = DestReg;
947 }
948 }
949
950 static void
951 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
952 const TargetInstrInfo &TII, DebugLoc dl,
953 int NumBytes,
954 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
955 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
956 Pred, PredReg, TII, dl);
957 }
958
959 void ARMBaseRegisterInfo::
960 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
961 MachineBasicBlock::iterator I) const {
962 if (!hasReservedCallFrame(MF)) {
963 // If we have alloca, convert as follows:
964 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
965 // ADJCALLSTACKUP -> add, sp, sp, amount
966 MachineInstr *Old = I;
967 DebugLoc dl = Old->getDebugLoc();
968 unsigned Amount = Old->getOperand(0).getImm();
969 if (Amount != 0) {
970 // We need to keep the stack aligned properly. To do this, we round the
971 // amount of space needed for the outgoing arguments up to the next
972 // alignment boundary.
973 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
974 Amount = (Amount+Align-1)/Align*Align;
975
976 // Replace the pseudo instruction with a new instruction...
977 unsigned Opc = Old->getOpcode();
978 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
979 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
980 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
981 unsigned PredReg = Old->getOperand(2).getReg();
982 emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
983 } else {
984 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
985 unsigned PredReg = Old->getOperand(3).getReg();
986 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
987 emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
988 }
989 }
990 }
991 MBB.erase(I);
992 }
993
994 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
995 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
996 /// register first and then a spilled callee-saved register if that fails.
997 static
998 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
999 ARMFunctionInfo *AFI) {
1000 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
1001 assert (!AFI->isThumbFunction());
1002 if (Reg == 0)
1003 // Try a already spilled CS register.
1004 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
1005
1006 return Reg;
1007 }
1008
1009 void ARMBaseRegisterInfo::
1010 eliminateFrameIndex(MachineBasicBlock::iterator II,
1011 int SPAdj, RegScavenger *RS) const{
1012 unsigned i = 0;
1013 MachineInstr &MI = *II;
1014 MachineBasicBlock &MBB = *MI.getParent();
1015 MachineFunction &MF = *MBB.getParent();
1016 ARMFunctionInfo *AFI = MF.getInfo();
1017 DebugLoc dl = MI.getDebugLoc();
1018
1019 while (!MI.getOperand(i).isFI()) {
1020 ++i;
1021 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
1022 }
1023
1024 unsigned FrameReg = ARM::SP;
1025 int FrameIndex = MI.getOperand(i).getIndex();
1026 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
1027 MF.getFrameInfo()->getStackSize() + SPAdj;
1028
1029 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
1030 Offset -= AFI->getGPRCalleeSavedArea1Offset();
1031 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
1032 Offset -= AFI->getGPRCalleeSavedArea2Offset();
1033 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
1034 Offset -= AFI->getDPRCalleeSavedAreaOffset();
1035 else if (hasFP(MF)) {
1036 assert(SPAdj == 0 && "Unexpected");
1037 // There is alloca()'s in this function, must reference off the frame
1038 // pointer instead.
1039 FrameReg = getFrameRegister(MF);
1040 Offset -= AFI->getFramePtrSpillOffset();
1041 }
1042
1043 unsigned Opcode = MI.getOpcode();
1044 const TargetInstrDesc &Desc = MI.getDesc();
1045 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
1046 bool isSub = false;
1047
1048 // Memory operands in inline assembly always use AddrMode2.
1049 if (Opcode == ARM::INLINEASM)
1050 AddrMode = ARMII::AddrMode2;
1051
1052 if (Opcode == ARM::ADDri) {
1053 Offset += MI.getOperand(i+1).getImm();
1054 if (Offset == 0) {
1055 // Turn it into a move.
1056 MI.setDesc(TII.get(ARM::MOVr));
1057 MI.getOperand(i).ChangeToRegister(FrameReg, false);
1058 MI.RemoveOperand(i+1);
1059 return;
1060 } else if (Offset < 0) {
1061 Offset = -Offset;
1062 isSub = true;
1063 MI.setDesc(TII.get(ARM::SUBri));
1064 }
1065
1066 // Common case: small offset, fits into instruction.
1067 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
1068 if (ImmedOffset != -1) {
1069 // Replace the FrameIndex with sp / fp
1070 MI.getOperand(i).ChangeToRegister(FrameReg, false);
1071 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
1072 return;
1073 }
1074
1075 // Otherwise, we fallback to common code below to form the imm offset with
1076 // a sequence of ADDri instructions. First though, pull as much of the imm
1077 // into this ADDri as possible.
1078 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
1079 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
1080
1081 // We will handle these bits from offset, clear them.
1082 Offset &= ~ThisImmVal;
1083
1084 // Get the properly encoded SOImmVal field.
1085 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
1086 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
1087 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
1088 } else {
1089 unsigned ImmIdx = 0;
1090 int InstrOffs = 0;
1091 unsigned NumBits = 0;
1092 unsigned Scale = 1;
1093 switch (AddrMode) {
1094 case ARMII::AddrMode2: {
1095 ImmIdx = i+2;
1096 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
1097 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1098 InstrOffs *= -1;
1099 NumBits = 12;
1100 break;
1101 }
1102 case ARMII::AddrMode3: {
1103 ImmIdx = i+2;
1104 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
1105 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1106 InstrOffs *= -1;
1107 NumBits = 8;
1108 break;
1109 }
1110 case ARMII::AddrMode5: {
1111 ImmIdx = i+1;
1112 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
1113 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
1114 InstrOffs *= -1;
1115 NumBits = 8;
1116 Scale = 4;
1117 break;
1118 }
1119 default:
1120 LLVM_UNREACHABLE("Unsupported addressing mode!");
1121 break;
1122 }
1123
1124 Offset += InstrOffs * Scale;
1125 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
1126 if (Offset < 0) {
1127 Offset = -Offset;
1128 isSub = true;
1129 }
1130
1131 // Common case: small offset, fits into instruction.
1132 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
1133 int ImmedOffset = Offset / Scale;
1134 unsigned Mask = (1 << NumBits) - 1;
1135 if ((unsigned)Offset <= Mask * Scale) {
1136 // Replace the FrameIndex with sp
1137 MI.getOperand(i).ChangeToRegister(FrameReg, false);
1138 if (isSub)
1139 ImmedOffset |= 1 << NumBits;
1140 ImmOp.ChangeToImmediate(ImmedOffset);
1141 return;
1142 }
1143
1144 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
1145 ImmedOffset = ImmedOffset & Mask;
1146 if (isSub)
1147 ImmedOffset |= 1 << NumBits;
1148 ImmOp.ChangeToImmediate(ImmedOffset);
1149 Offset &= ~(Mask*Scale);
1150 }
1151
1152 // If we get here, the immediate doesn't fit into the instruction. We folded
1153 // as much as possible above, handle the rest, providing a register that is
1154 // SP+LargeImm.
1155 assert(Offset && "This code isn't needed if offset already handled!");
1156
1157 // Insert a set of r12 with the full address: r12 = sp + offset
1158 // If the offset we have is too large to fit into the instruction, we need
1159 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
1160 // out of 'Offset'.
1161 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
1162 if (ScratchReg == 0)
1163 // No register is "free". Scavenge a register.
1164 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
1165 int PIdx = MI.findFirstPredOperandIdx();
1166 ARMCC::CondCodes Pred = (PIdx == -1)
1167 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1168 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
1169 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
1170 isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
1171 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1172 }
1173
1174 /// Move iterator pass the next bunch of callee save load / store ops for
1175 /// the particular spill area (1: integer area 1, 2: integer area 2,
1176 /// 3: fp area, 0: don't care).
1177 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1178 MachineBasicBlock::iterator &MBBI,
1179 int Opc, unsigned Area,
1180 const ARMSubtarget &STI) {
1181 while (MBBI != MBB.end() &&
1182 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1183 if (Area != 0) {
1184 bool Done = false;
1185 unsigned Category = 0;
1186 switch (MBBI->getOperand(0).getReg()) {
1187 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
1188 case ARM::LR:
1189 Category = 1;
1190 break;
1191 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
1192 Category = STI.isTargetDarwin() ? 2 : 1;
1193 break;
1194 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
1195 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1196 Category = 3;
1197 break;
1198 default:
1199 Done = true;
1200 break;
1201 }
1202 if (Done || Category != Area)
1203 break;
1204 }
1205
1206 ++MBBI;
1207 }
1208 }
1209
1210 void ARMBaseRegisterInfo::
1211 emitPrologue(MachineFunction &MF) const {
1212 MachineBasicBlock &MBB = MF.front();
1213 MachineBasicBlock::iterator MBBI = MBB.begin();
1214 MachineFrameInfo *MFI = MF.getFrameInfo();
1215 ARMFunctionInfo *AFI = MF.getInfo();
1216 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1217 unsigned NumBytes = MFI->getStackSize();
1218 const std::vector &CSI = MFI->getCalleeSavedInfo();
1219 DebugLoc dl = (MBBI != MBB.end() ?
1220 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1221
1222 // Determine the sizes of each callee-save spill areas and record which frame
1223 // belongs to which callee-save spill areas.
1224 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1225 int FramePtrSpillFI = 0;
1226
1227 if (VARegSaveSize)
1228 emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
1229
1230 if (!AFI->hasStackFrame()) {
1231 if (NumBytes != 0)
1232 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1233 return;
1234 }
1235
1236 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1237 unsigned Reg = CSI[i].getReg();
1238 int FI = CSI[i].getFrameIdx();
1239 switch (Reg) {
1240 case ARM::R4:
1241 case ARM::R5:
1242 case ARM::R6:
1243 case ARM::R7:
1244 case ARM::LR:
1245 if (Reg == FramePtr)
1246 FramePtrSpillFI = FI;
1247 AFI->addGPRCalleeSavedArea1Frame(FI);
1248 GPRCS1Size += 4;
1249 break;
1250 case ARM::R8:
1251 case ARM::R9:
1252 case ARM::R10:
1253 case ARM::R11:
1254 if (Reg == FramePtr)
1255 FramePtrSpillFI = FI;
1256 if (STI.isTargetDarwin()) {
1257 AFI->addGPRCalleeSavedArea2Frame(FI);
1258 GPRCS2Size += 4;
1259 } else {
1260 AFI->addGPRCalleeSavedArea1Frame(FI);
1261 GPRCS1Size += 4;
1262 }
1263 break;
1264 default:
1265 AFI->addDPRCalleeSavedAreaFrame(FI);
1266 DPRCSSize += 8;
1267 }
1268 }
1269
1270 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1271 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
1272 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1273
1274 // Darwin ABI requires FP to point to the stack slot that contains the
1275 // previous FP.
1276 if (STI.isTargetDarwin() || hasFP(MF)) {
1277 MachineInstrBuilder MIB =
1278 BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
1279 .addFrameIndex(FramePtrSpillFI).addImm(0);
1280 AddDefaultCC(AddDefaultPred(MIB));
1281 }
1282
1283 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1284 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
1285
1286 // Build the new SUBri to adjust SP for FP callee-save spill area.
1287 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1288 emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
1289
1290 // Determine starting offsets of spill areas.
1291 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1292 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1293 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1294 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1295 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1296 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1297 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1298
1299 NumBytes = DPRCSOffset;
1300 if (NumBytes) {
1301 // Insert it after all the callee-save spills.
1302 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1303 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1304 }
1305
1306 if (STI.isTargetELF() && hasFP(MF)) {
1307 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1308 AFI->getFramePtrSpillOffset());
1309 }
1310
1311 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1312 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1313 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1314 }
1315
1316 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1317 for (unsigned i = 0; CSRegs[i]; ++i)
1318 if (Reg == CSRegs[i])
1319 return true;
1320 return false;
1321 }
1322
1323 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1324 return ((MI->getOpcode() == ARM::FLDD ||
1325 MI->getOpcode() == ARM::LDR) &&
1326 MI->getOperand(1).isFI() &&
1327 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1328 }
1329
1330 void ARMBaseRegisterInfo::
1331 emitEpilogue(MachineFunction &MF,
1332 MachineBasicBlock &MBB) const {
1333 MachineBasicBlock::iterator MBBI = prior(MBB.end());
1334 assert(MBBI->getOpcode() == ARM::BX_RET &&
1335 "Can only insert epilog into returning blocks");
1336 DebugLoc dl = MBBI->getDebugLoc();
1337 MachineFrameInfo *MFI = MF.getFrameInfo();
1338 ARMFunctionInfo *AFI = MF.getInfo();
1339 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1340 int NumBytes = (int)MFI->getStackSize();
1341
1342 if (!AFI->hasStackFrame()) {
1343 if (NumBytes != 0)
1344 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1345 } else {
1346 // Unwind MBBI to point to first LDR / FLDD.
1347 const unsigned *CSRegs = getCalleeSavedRegs();
1348 if (MBBI != MBB.begin()) {
1349 do
1350 --MBBI;
1351 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1352 if (!isCSRestore(MBBI, CSRegs))
1353 ++MBBI;
1354 }
1355
1356 // Move SP to start of FP callee save spill area.
1357 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1358 AFI->getGPRCalleeSavedArea2Size() +
1359 AFI->getDPRCalleeSavedAreaSize());
1360
1361 // Darwin ABI requires FP to point to the stack slot that contains the
1362 // previous FP.
1363 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1364 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1365 // Reset SP based on frame pointer only if the stack frame extends beyond
1366 // frame pointer stack slot or target is ELF and the function has FP.
1367 if (AFI->getGPRCalleeSavedArea2Size() ||
1368 AFI->getDPRCalleeSavedAreaSize() ||
1369 AFI->getDPRCalleeSavedAreaOffset()||
1370 hasFP(MF)) {
1371 if (NumBytes)
1372 BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1373 .addImm(NumBytes)
1374 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1375 else
1376 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1377 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1378 }
1379 } else if (NumBytes) {
1380 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1381 }
1382
1383 // Move SP to start of integer callee save spill area 2.
1384 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1385 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
1386
1387 // Move SP to start of integer callee save spill area 1.
1388 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1389 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
1390
1391 // Move SP to SP upon entry to the function.
1392 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1393 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
1394 }
1395
1396 if (VARegSaveSize)
1397 emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);
1398
1399 }
1400
8631401 #include "ARMGenRegisterInfo.inc"
1919
2020 namespace llvm {
2121 class ARMSubtarget;
22 class TargetInstrInfo;
22 class ARMBaseInstrInfo;
2323 class Type;
2424
2525 /// Register allocation hints.
4545
4646 struct ARMBaseRegisterInfo : public ARMGenRegisterInfo {
4747 protected:
48 const TargetInstrInfo &TII;
48 const ARMBaseInstrInfo &TII;
4949 const ARMSubtarget &STI;
5050
5151 /// FramePtr - ARM physical register used as frame ptr.
5252 unsigned FramePtr;
53
54 // Can be only subclassed.
55 explicit ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
56
5357 public:
54 ARMBaseRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
55
5658 /// getRegisterNumbering - Given the enum value for some register, e.g.
5759 /// ARM::LR, return the number that it corresponds to (e.g. 14).
5860 static unsigned getRegisterNumbering(unsigned RegEnum);
6870 getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
6971
7072 BitVector getReservedRegs(const MachineFunction &MF) const;
71
72 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
7373
7474 const TargetRegisterClass *getPointerRegClass() const;
7575
101101
102102 bool isLowRegister(unsigned Reg) const;
103103
104
105 /// emitLoadConstPool - Emits a load from constpool to materialize the
106 /// specified immediate.
107 virtual void emitLoadConstPool(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator &MBBI,
109 const TargetInstrInfo *TII, DebugLoc dl,
110 unsigned DestReg, int Val,
111 ARMCC::CondCodes Pred = ARMCC::AL,
112 unsigned PredReg = 0) const;
113
114 /// Code Generation virtual methods...
115 virtual bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
116
117 virtual bool requiresRegisterScavenging(const MachineFunction &MF) const;
118
119 virtual bool hasReservedCallFrame(MachineFunction &MF) const;
120
121 virtual void eliminateCallFramePseudoInstr(MachineFunction &MF,
122 MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I) const;
124
125 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
126 int SPAdj, RegScavenger *RS = NULL) const;
127
128 virtual void emitPrologue(MachineFunction &MF) const;
129 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
130
104131 private:
105132 unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
106133
3333 #include "llvm/ADT/SmallVector.h"
3434 using namespace llvm;
3535
36 ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
36 ARMRegisterInfo::ARMRegisterInfo(const ARMBaseInstrInfo &tii,
3737 const ARMSubtarget &sti)
3838 : ARMBaseRegisterInfo(tii, sti) {
3939 }
40
41 static inline
42 const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
43 return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
44 }
45
46 static inline
47 const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
48 return MIB.addReg(0);
49 }
50
51 /// emitLoadConstPool - Emits a load from constpool to materialize the
52 /// specified immediate.
53 void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
54 MachineBasicBlock::iterator &MBBI,
55 const TargetInstrInfo *TII, DebugLoc dl,
56 unsigned DestReg, int Val,
57 ARMCC::CondCodes Pred,
58 unsigned PredReg) const {
59 MachineFunction &MF = *MBB.getParent();
60 MachineConstantPool *ConstantPool = MF.getConstantPool();
61 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
62 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
63
64 BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
65 .addConstantPoolIndex(Idx)
66 .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
67 }
68
69 bool
70 ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
71 return true;
72 }
73
74 // hasReservedCallFrame - Under normal circumstances, when a frame pointer is
75 // not required, we reserve argument space for call sites in the function
76 // immediately on entry to the current function. This eliminates the need for
77 // add/sub sp brackets around call sites. Returns true if the call frame is
78 // included as part of the stack frame.
79 bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
80 const MachineFrameInfo *FFI = MF.getFrameInfo();
81 unsigned CFSize = FFI->getMaxCallFrameSize();
82 // It's not always a good idea to include the call frame as part of the
83 // stack frame. ARM (especially Thumb) has small immediate offset to
84 // address the stack frame. So a large call frame can cause poor codegen
85 // and may even makes it impossible to scavenge a register.
86 if (CFSize >= ((1 << 12) - 1) / 2) // Half of imm12
87 return false;
88
89 return !MF.getFrameInfo()->hasVarSizedObjects();
90 }
91
92 /// emitARMRegPlusImmediate - Emits a series of instructions to materialize
93 /// a destreg = basereg + immediate in ARM code.
94 static
95 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator &MBBI,
97 unsigned DestReg, unsigned BaseReg, int NumBytes,
98 ARMCC::CondCodes Pred, unsigned PredReg,
99 const TargetInstrInfo &TII,
100 DebugLoc dl) {
101 bool isSub = NumBytes < 0;
102 if (isSub) NumBytes = -NumBytes;
103
104 while (NumBytes) {
105 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
106 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
107 assert(ThisVal && "Didn't extract field correctly");
108
109 // We will handle these bits from offset, clear them.
110 NumBytes &= ~ThisVal;
111
112 // Get the properly encoded SOImmVal field.
113 int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
114 assert(SOImmVal != -1 && "Bit extraction didn't work?");
115
116 // Build the new ADD / SUB.
117 BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
118 .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
119 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
120 BaseReg = DestReg;
121 }
122 }
123
124 static void
125 emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
126 const TargetInstrInfo &TII, DebugLoc dl,
127 int NumBytes,
128 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
129 emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
130 Pred, PredReg, TII, dl);
131 }
132
133 void ARMRegisterInfo::
134 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
135 MachineBasicBlock::iterator I) const {
136 if (!hasReservedCallFrame(MF)) {
137 // If we have alloca, convert as follows:
138 // ADJCALLSTACKDOWN -> sub, sp, sp, amount
139 // ADJCALLSTACKUP -> add, sp, sp, amount
140 MachineInstr *Old = I;
141 DebugLoc dl = Old->getDebugLoc();
142 unsigned Amount = Old->getOperand(0).getImm();
143 if (Amount != 0) {
144 // We need to keep the stack aligned properly. To do this, we round the
145 // amount of space needed for the outgoing arguments up to the next
146 // alignment boundary.
147 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
148 Amount = (Amount+Align-1)/Align*Align;
149
150 // Replace the pseudo instruction with a new instruction...
151 unsigned Opc = Old->getOpcode();
152 ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
153 if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
154 // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
155 unsigned PredReg = Old->getOperand(2).getReg();
156 emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
157 } else {
158 // Note: PredReg is operand 3 for ADJCALLSTACKUP.
159 unsigned PredReg = Old->getOperand(3).getReg();
160 assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
161 emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
162 }
163 }
164 }
165 MBB.erase(I);
166 }
167
168 /// findScratchRegister - Find a 'free' ARM register. If register scavenger
169 /// is not being used, R12 is available. Otherwise, try for a call-clobbered
170 /// register first and then a spilled callee-saved register if that fails.
171 static
172 unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
173 ARMFunctionInfo *AFI) {
174 unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
175 assert (!AFI->isThumbFunction());
176 if (Reg == 0)
177 // Try a already spilled CS register.
178 Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
179
180 return Reg;
181 }
182
183 void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
184 int SPAdj, RegScavenger *RS) const{
185 unsigned i = 0;
186 MachineInstr &MI = *II;
187 MachineBasicBlock &MBB = *MI.getParent();
188 MachineFunction &MF = *MBB.getParent();
189 ARMFunctionInfo *AFI = MF.getInfo();
190 DebugLoc dl = MI.getDebugLoc();
191
192 while (!MI.getOperand(i).isFI()) {
193 ++i;
194 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
195 }
196
197 unsigned FrameReg = ARM::SP;
198 int FrameIndex = MI.getOperand(i).getIndex();
199 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
200 MF.getFrameInfo()->getStackSize() + SPAdj;
201
202 if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
203 Offset -= AFI->getGPRCalleeSavedArea1Offset();
204 else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
205 Offset -= AFI->getGPRCalleeSavedArea2Offset();
206 else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
207 Offset -= AFI->getDPRCalleeSavedAreaOffset();
208 else if (hasFP(MF)) {
209 assert(SPAdj == 0 && "Unexpected");
210 // There is alloca()'s in this function, must reference off the frame
211 // pointer instead.
212 FrameReg = getFrameRegister(MF);
213 Offset -= AFI->getFramePtrSpillOffset();
214 }
215
216 unsigned Opcode = MI.getOpcode();
217 const TargetInstrDesc &Desc = MI.getDesc();
218 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
219 bool isSub = false;
220
221 // Memory operands in inline assembly always use AddrMode2.
222 if (Opcode == ARM::INLINEASM)
223 AddrMode = ARMII::AddrMode2;
224
225 if (Opcode == ARM::ADDri) {
226 Offset += MI.getOperand(i+1).getImm();
227 if (Offset == 0) {
228 // Turn it into a move.
229 MI.setDesc(TII.get(ARM::MOVr));
230 MI.getOperand(i).ChangeToRegister(FrameReg, false);
231 MI.RemoveOperand(i+1);
232 return;
233 } else if (Offset < 0) {
234 Offset = -Offset;
235 isSub = true;
236 MI.setDesc(TII.get(ARM::SUBri));
237 }
238
239 // Common case: small offset, fits into instruction.
240 int ImmedOffset = ARM_AM::getSOImmVal(Offset);
241 if (ImmedOffset != -1) {
242 // Replace the FrameIndex with sp / fp
243 MI.getOperand(i).ChangeToRegister(FrameReg, false);
244 MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
245 return;
246 }
247
248 // Otherwise, we fallback to common code below to form the imm offset with
249 // a sequence of ADDri instructions. First though, pull as much of the imm
250 // into this ADDri as possible.
251 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
252 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
253
254 // We will handle these bits from offset, clear them.
255 Offset &= ~ThisImmVal;
256
257 // Get the properly encoded SOImmVal field.
258 int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
259 assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
260 MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
261 } else {
262 unsigned ImmIdx = 0;
263 int InstrOffs = 0;
264 unsigned NumBits = 0;
265 unsigned Scale = 1;
266 switch (AddrMode) {
267 case ARMII::AddrMode2: {
268 ImmIdx = i+2;
269 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
270 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
271 InstrOffs *= -1;
272 NumBits = 12;
273 break;
274 }
275 case ARMII::AddrMode3: {
276 ImmIdx = i+2;
277 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
278 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
279 InstrOffs *= -1;
280 NumBits = 8;
281 break;
282 }
283 case ARMII::AddrMode5: {
284 ImmIdx = i+1;
285 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
286 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
287 InstrOffs *= -1;
288 NumBits = 8;
289 Scale = 4;
290 break;
291 }
292 default:
293 LLVM_UNREACHABLE("Unsupported addressing mode!");
294 break;
295 }
296
297 Offset += InstrOffs * Scale;
298 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
299 if (Offset < 0) {
300 Offset = -Offset;
301 isSub = true;
302 }
303
304 // Common case: small offset, fits into instruction.
305 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
306 int ImmedOffset = Offset / Scale;
307 unsigned Mask = (1 << NumBits) - 1;
308 if ((unsigned)Offset <= Mask * Scale) {
309 // Replace the FrameIndex with sp
310 MI.getOperand(i).ChangeToRegister(FrameReg, false);
311 if (isSub)
312 ImmedOffset |= 1 << NumBits;
313 ImmOp.ChangeToImmediate(ImmedOffset);
314 return;
315 }
316
317 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
318 ImmedOffset = ImmedOffset & Mask;
319 if (isSub)
320 ImmedOffset |= 1 << NumBits;
321 ImmOp.ChangeToImmediate(ImmedOffset);
322 Offset &= ~(Mask*Scale);
323 }
324
325 // If we get here, the immediate doesn't fit into the instruction. We folded
326 // as much as possible above, handle the rest, providing a register that is
327 // SP+LargeImm.
328 assert(Offset && "This code isn't needed if offset already handled!");
329
330 // Insert a set of r12 with the full address: r12 = sp + offset
331 // If the offset we have is too large to fit into the instruction, we need
332 // to form it with a series of ADDri's. Do this by taking 8-bit chunks
333 // out of 'Offset'.
334 unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
335 if (ScratchReg == 0)
336 // No register is "free". Scavenge a register.
337 ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
338 int PIdx = MI.findFirstPredOperandIdx();
339 ARMCC::CondCodes Pred = (PIdx == -1)
340 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
341 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
342 emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
343 isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
344 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
345 }
346
347 /// Move iterator pass the next bunch of callee save load / store ops for
348 /// the particular spill area (1: integer area 1, 2: integer area 2,
349 /// 3: fp area, 0: don't care).
350 static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
351 MachineBasicBlock::iterator &MBBI,
352 int Opc, unsigned Area,
353 const ARMSubtarget &STI) {
354 while (MBBI != MBB.end() &&
355 MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
356 if (Area != 0) {
357 bool Done = false;
358 unsigned Category = 0;
359 switch (MBBI->getOperand(0).getReg()) {
360 case ARM::R4: case ARM::R5: case ARM::R6: case ARM::R7:
361 case ARM::LR:
362 Category = 1;
363 break;
364 case ARM::R8: case ARM::R9: case ARM::R10: case ARM::R11:
365 Category = STI.isTargetDarwin() ? 2 : 1;
366 break;
367 case ARM::D8: case ARM::D9: case ARM::D10: case ARM::D11:
368 case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
369 Category = 3;
370 break;
371 default:
372 Done = true;
373 break;
374 }
375 if (Done || Category != Area)
376 break;
377 }
378
379 ++MBBI;
380 }
381 }
382
383 void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
384 MachineBasicBlock &MBB = MF.front();
385 MachineBasicBlock::iterator MBBI = MBB.begin();
386 MachineFrameInfo *MFI = MF.getFrameInfo();
387 ARMFunctionInfo *AFI = MF.getInfo();
388 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
389 unsigned NumBytes = MFI->getStackSize();
390 const std::vector &CSI = MFI->getCalleeSavedInfo();
391 DebugLoc dl = (MBBI != MBB.end() ?
392 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
393
394 // Determine the sizes of each callee-save spill areas and record which frame
395 // belongs to which callee-save spill areas.
396 unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
397 int FramePtrSpillFI = 0;
398
399 if (VARegSaveSize)
400 emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
401
402 if (!AFI->hasStackFrame()) {
403 if (NumBytes != 0)
404 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
405 return;
406 }
407
408 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
409 unsigned Reg = CSI[i].getReg();
410 int FI = CSI[i].getFrameIdx();
411 switch (Reg) {
412 case ARM::R4:
413 case ARM::R5:
414 case ARM::R6:
415 case ARM::R7:
416 case ARM::LR:
417 if (Reg == FramePtr)
418 FramePtrSpillFI = FI;
419 AFI->addGPRCalleeSavedArea1Frame(FI);
420 GPRCS1Size += 4;
421 break;
422 case ARM::R8:
423 case ARM::R9:
424 case ARM::R10:
425 case ARM::R11:
426 if (Reg == FramePtr)
427 FramePtrSpillFI = FI;
428 if (STI.isTargetDarwin()) {
429 AFI->addGPRCalleeSavedArea2Frame(FI);
430 GPRCS2Size += 4;
431 } else {
432 AFI->addGPRCalleeSavedArea1Frame(FI);
433 GPRCS1Size += 4;
434 }
435 break;
436 default:
437 AFI->addDPRCalleeSavedAreaFrame(FI);
438 DPRCSSize += 8;
439 }
440 }
441
442 // Build the new SUBri to adjust SP for integer callee-save spill area 1.
443 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
444 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
445
446 // Darwin ABI requires FP to point to the stack slot that contains the
447 // previous FP.
448 if (STI.isTargetDarwin() || hasFP(MF)) {
449 MachineInstrBuilder MIB =
450 BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
451 .addFrameIndex(FramePtrSpillFI).addImm(0);
452 AddDefaultCC(AddDefaultPred(MIB));
453 }
454
455 // Build the new SUBri to adjust SP for integer callee-save spill area 2.
456 emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
457
458 // Build the new SUBri to adjust SP for FP callee-save spill area.
459 movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
460 emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
461
462 // Determine starting offsets of spill areas.
463 unsigned DPRCSOffset = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
464 unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
465 unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
466 AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
467 AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
468 AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
469 AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
470
471 NumBytes = DPRCSOffset;
472 if (NumBytes) {
473 // Insert it after all the callee-save spills.
474 movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
475 emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
476 }
477
478 if (STI.isTargetELF() && hasFP(MF)) {
479 MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
480 AFI->getFramePtrSpillOffset());
481 }
482
483 AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
484 AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
485 AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
486 }
487
488 static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
489 for (unsigned i = 0; CSRegs[i]; ++i)
490 if (Reg == CSRegs[i])
491 return true;
492 return false;
493 }
494
495 static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
496 return ((MI->getOpcode() == ARM::FLDD ||
497 MI->getOpcode() == ARM::LDR) &&
498 MI->getOperand(1).isFI() &&
499 isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
500 }
501
502 void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
503 MachineBasicBlock &MBB) const {
504 MachineBasicBlock::iterator MBBI = prior(MBB.end());
505 assert(MBBI->getOpcode() == ARM::BX_RET &&
506 "Can only insert epilog into returning blocks");
507 DebugLoc dl = MBBI->getDebugLoc();
508 MachineFrameInfo *MFI = MF.getFrameInfo();
509 ARMFunctionInfo *AFI = MF.getInfo();
510 unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
511 int NumBytes = (int)MFI->getStackSize();
512
513 if (!AFI->hasStackFrame()) {
514 if (NumBytes != 0)
515 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
516 } else {
517 // Unwind MBBI to point to first LDR / FLDD.
518 const unsigned *CSRegs = getCalleeSavedRegs();
519 if (MBBI != MBB.begin()) {
520 do
521 --MBBI;
522 while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
523 if (!isCSRestore(MBBI, CSRegs))
524 ++MBBI;
525 }
526
527 // Move SP to start of FP callee save spill area.
528 NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
529 AFI->getGPRCalleeSavedArea2Size() +
530 AFI->getDPRCalleeSavedAreaSize());
531
532 // Darwin ABI requires FP to point to the stack slot that contains the
533 // previous FP.
534 if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
535 NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
536 // Reset SP based on frame pointer only if the stack frame extends beyond
537 // frame pointer stack slot or target is ELF and the function has FP.
538 if (AFI->getGPRCalleeSavedArea2Size() ||
539 AFI->getDPRCalleeSavedAreaSize() ||
540 AFI->getDPRCalleeSavedAreaOffset()||
541 hasFP(MF)) {
542 if (NumBytes)
543 BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
544 .addImm(NumBytes)
545 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
546 else
547 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
548 .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
549 }
550 } else if (NumBytes) {
551 emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
552 }
553
554 // Move SP to start of integer callee save spill area 2.
555 movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
556 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
557
558 // Move SP to start of integer callee save spill area 1.
559 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
560 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
561
562 // Move SP to SP upon entry to the function.
563 movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
564 emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
565 }
566
567 if (VARegSaveSize)
568 emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);
569
570 }
571
1919
2020 namespace llvm {
2121 class ARMSubtarget;
22 class TargetInstrInfo;
22 class ARMBaseInstrInfo;
2323 class Type;
2424
2525 struct ARMRegisterInfo : public ARMBaseRegisterInfo {
2626 public:
27 ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
28
29 /// emitLoadConstPool - Emits a load from constpool to materialize the
30 /// specified immediate.
31 void emitLoadConstPool(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator &MBBI,
33 const TargetInstrInfo *TII, DebugLoc dl,
34 unsigned DestReg, int Val,
35 ARMCC::CondCodes Pred = ARMCC::AL,
36 unsigned PredReg = 0) const;
37
38 /// Code Generation virtual methods...
39 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
40
41 bool requiresRegisterScavenging(const MachineFunction &MF) const;
42
43 bool hasReservedCallFrame(MachineFunction &MF) const;
44
45 void eliminateCallFramePseudoInstr(MachineFunction &MF,
46 MachineBasicBlock &MBB,
47 MachineBasicBlock::iterator I) const;
48
49 void eliminateFrameIndex(MachineBasicBlock::iterator II,
50 int SPAdj, RegScavenger *RS = NULL) const;
51
52 void emitPrologue(MachineFunction &MF) const;
53 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
27 ARMRegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
5428 };
5529
5630 } // end namespace llvm
3737 cl::Hidden,
3838 cl::desc("Enable register scavenging on Thumb"));
3939
40 Thumb1RegisterInfo::Thumb1RegisterInfo(const TargetInstrInfo &tii,
40 Thumb1RegisterInfo::Thumb1RegisterInfo(const ARMBaseInstrInfo &tii,
4141 const ARMSubtarget &sti)
4242 : ARMBaseRegisterInfo(tii, sti) {
4343 }
4646 /// specified immediate.
4747 void Thumb1RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
4848 MachineBasicBlock::iterator &MBBI,
49 const TargetInstrInfo *TII, DebugLoc dl,
4950 unsigned DestReg, int Val,
50 const TargetInstrInfo *TII,
51 DebugLoc dl) const {
51 ARMCC::CondCodes Pred,
52 unsigned PredReg) const {
5253 MachineFunction &MF = *MBB.getParent();
5354 MachineConstantPool *ConstantPool = MF.getConstantPool();
5455 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
129130 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
130131 .addReg(LdReg, RegState::Kill);
131132 } else
132 MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, &TII, dl);
133 MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
133134
134135 // Emit add / sub.
135136 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
503504 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
504505 Offset, false, TII, *this, dl);
505506 else {
506 emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
507 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
507508 UseRR = true;
508509 }
509510 } else
541542 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
542543 Offset, false, TII, *this, dl);
543544 else {
544 emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
545 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
545546 UseRR = true;
546547 }
547548 } else
1919
2020 namespace llvm {
2121 class ARMSubtarget;
22 class TargetInstrInfo;
22 class ARMBaseInstrInfo;
2323 class Type;
2424
2525 struct Thumb1RegisterInfo : public ARMBaseRegisterInfo {
2626 public:
27 Thumb1RegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
27 Thumb1RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
2828
2929 /// emitLoadConstPool - Emits a load from constpool to materialize the
3030 /// specified immediate.
31 void emitLoadConstPool(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator &MBBI,
33 unsigned DestReg, int Val,
34 const TargetInstrInfo *TII,
35 DebugLoc dl) const;
31 void emitLoadConstPool(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator &MBBI,
33 const TargetInstrInfo *TII, DebugLoc dl,
34 unsigned DestReg, int Val,
35 ARMCC::CondCodes Pred = ARMCC::AL,
36 unsigned PredReg = 0) const;
3637
3738 /// Code Generation virtual methods...
3839 const TargetRegisterClass *
3940 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
40
41 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
4241
4342 bool requiresRegisterScavenging(const MachineFunction &MF) const;
4443
3737 cl::Hidden,
3838 cl::desc("Enable register scavenging on Thumb-2"));
3939
40 Thumb2RegisterInfo::Thumb2RegisterInfo(const TargetInstrInfo &tii,
40 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
4141 const ARMSubtarget &sti)
4242 : ARMBaseRegisterInfo(tii, sti) {
4343 }
4646 /// specified immediate.
4747 void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
4848 MachineBasicBlock::iterator &MBBI,
49 const TargetInstrInfo *TII, DebugLoc dl,
4950 unsigned DestReg, int Val,
50 const TargetInstrInfo *TII,
51 DebugLoc dl) const {
51 ARMCC::CondCodes Pred,
52 unsigned PredReg) const {
5253 MachineFunction &MF = *MBB.getParent();
5354 MachineConstantPool *ConstantPool = MF.getConstantPool();
5455 Constant *C = ConstantInt::get(Type::Int32Ty, Val);
129130 BuildMI(MBB, MBBI, dl, TII.get(ARM::tNEG), LdReg)
130131 .addReg(LdReg, RegState::Kill);
131132 } else
132 MRI.emitLoadConstPool(MBB, MBBI, LdReg, NumBytes, &TII, dl);
133 MRI.emitLoadConstPool(MBB, MBBI, &TII, dl, LdReg, NumBytes);
133134
134135 // Emit add / sub.
135136 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr);
503504 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
504505 Offset, false, TII, *this, dl);
505506 else {
506 emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
507 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
507508 UseRR = true;
508509 }
509510 } else
541542 emitThumbRegPlusImmInReg(MBB, II, TmpReg, FrameReg,
542543 Offset, false, TII, *this, dl);
543544 else {
544 emitLoadConstPool(MBB, II, TmpReg, Offset, &TII, dl);
545 emitLoadConstPool(MBB, II, &TII, dl, TmpReg, Offset);
545546 UseRR = true;
546547 }
547548 } else
1919
2020 namespace llvm {
2121 class ARMSubtarget;
22 class TargetInstrInfo;
22 class ARMBaseInstrInfo;
2323 class Type;
2424
2525 struct Thumb2RegisterInfo : public ARMBaseRegisterInfo {
2626 public:
27 Thumb2RegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
27 Thumb2RegisterInfo(const ARMBaseInstrInfo &tii, const ARMSubtarget &STI);
2828
2929 /// emitLoadConstPool - Emits a load from constpool to materialize the
3030 /// specified immediate.
31 void emitLoadConstPool(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator &MBBI,
33 unsigned DestReg, int Val,
34 const TargetInstrInfo *TII,
35 DebugLoc dl) const;
31 void emitLoadConstPool(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator &MBBI,
33 const TargetInstrInfo *TII, DebugLoc dl,
34 unsigned DestReg, int Val,
35 ARMCC::CondCodes Pred = ARMCC::AL,
36 unsigned PredReg = 0) const;
3637
3738 /// Code Generation virtual methods...
3839 const TargetRegisterClass *
3940 getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
40
41 bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
4241
4342 bool requiresRegisterScavenging(const MachineFunction &MF) const;
4443