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[ARM] Armv8-R DFB instruction Implement MC support for the Armv8-R 'Data Full Barrier' instruction. Differential Revision: https://reviews.llvm.org/D41430 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@321256 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Parker 2 years ago
9 changed file(s) with 49 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
8181
8282 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
8383 "Has v7 clrex instruction">;
84
85 def FeatureDFB : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
86 "Has full data barrier (dfb) instruction">;
8487
8588 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
8689 "HasAcquireRelease", "true",
616619 def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
617620 FeatureRClass,
618621 FeatureDB,
622 FeatureDFB,
619623 FeatureDSP,
620624 FeatureCRC,
621625 FeatureMP,
279279 def HasDB : Predicate<"Subtarget->hasDataBarrier()">,
280280 AssemblerPredicate<"FeatureDB",
281281 "data-barriers">;
282 def HasDFB : Predicate<"Subtarget->hasFullDataBarrier()">,
283 AssemblerPredicate<"FeatureDFB",
284 "full-data-barrier">;
282285 def HasV7Clrex : Predicate<"Subtarget->hasV7Clrex()">,
283286 AssemblerPredicate<"FeatureV7Clrex",
284287 "v7 clrex">;
58495852 def : InstAlias<"dmb", (DMB 0xf), 0>, Requires<[IsARM, HasDB]>;
58505853 def : InstAlias<"dsb", (DSB 0xf), 0>, Requires<[IsARM, HasDB]>;
58515854 def : InstAlias<"isb", (ISB 0xf), 0>, Requires<[IsARM, HasDB]>;
5855 // Armv8-R 'Data Full Barrier'
5856 def : InstAlias<"dfb", (DSB 0xc), 1>, Requires<[IsARM, HasDFB]>;
58525857
58535858 // System instructions
58545859 def : MnemonicAlias<"swi", "svc">;
45074507 def : InstAlias<"dmb${p}", (t2DMB 0xf, pred:$p), 0>, Requires<[HasDB]>;
45084508 def : InstAlias<"dsb${p}", (t2DSB 0xf, pred:$p), 0>, Requires<[HasDB]>;
45094509 def : InstAlias<"isb${p}", (t2ISB 0xf, pred:$p), 0>, Requires<[HasDB]>;
4510 // Armv8-R 'Data Full Barrier'
4511 def : InstAlias<"dfb${p}", (t2DSB 0xc, pred:$p), 1>, Requires<[HasDFB]>;
45104512
45114513 // Alias for LDR, LDRB, LDRH, LDRSB, and LDRSH without the ".w" optional
45124514 // width specifier.
235235 /// instructions.
236236 bool HasDataBarrier = false;
237237
238 /// HasFullDataBarrier - True if the subtarget supports DFB data barrier
239 /// instruction.
240 bool HasFullDataBarrier = false;
241
238242 /// HasV7Clrex - True if the subtarget supports CLREX instructions
239243 bool HasV7Clrex = false;
240244
543547 bool hasDivideInThumbMode() const { return HasHardwareDivideInThumb; }
544548 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
545549 bool hasDataBarrier() const { return HasDataBarrier; }
550 bool hasFullDataBarrier() const { return HasFullDataBarrier; }
546551 bool hasV7Clrex() const { return HasV7Clrex; }
547552 bool hasAcquireRelease() const { return HasAcquireRelease; }
548553
55805580 CanAcceptPredicationCode =
55815581 Mnemonic != "cdp2" && Mnemonic != "clrex" && Mnemonic != "mcr2" &&
55825582 Mnemonic != "mcrr2" && Mnemonic != "mrc2" && Mnemonic != "mrrc2" &&
5583 Mnemonic != "dmb" && Mnemonic != "dsb" && Mnemonic != "isb" &&
5584 Mnemonic != "pld" && Mnemonic != "pli" && Mnemonic != "pldw" &&
5585 Mnemonic != "ldc2" && Mnemonic != "ldc2l" && Mnemonic != "stc2" &&
5586 Mnemonic != "stc2l" && !Mnemonic.startswith("rfe") &&
5587 !Mnemonic.startswith("srs");
5583 Mnemonic != "dmb" && Mnemonic != "dfb" && Mnemonic != "dsb" &&
5584 Mnemonic != "isb" && Mnemonic != "pld" && Mnemonic != "pli" &&
5585 Mnemonic != "pldw" && Mnemonic != "ldc2" && Mnemonic != "ldc2l" &&
5586 Mnemonic != "stc2" && Mnemonic != "stc2l" &&
5587 !Mnemonic.startswith("rfe") && !Mnemonic.startswith("srs");
55885588 } else if (isThumbOne()) {
55895589 if (hasV6MOps())
55905590 CanAcceptPredicationCode = Mnemonic != "movs";
0 @ RUN: not llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s 2>&1 | FileCheck %s
1 @ RUN: not llvm-mc -triple thumbv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s 2>&1 | FileCheck %s
2
3 dfb
4 @ CHECK: error: instruction requires: full-data-barrier
5
6 dfb sy
7 dfb #0
8 @ CHECK: error: invalid instruction
9 @ CHECK: error: invalid instruction
0 @ RUN: llvm-mc -triple armv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-ARM
1 @ RUN: llvm-mc -triple thumbv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-THUMB
2
3 dfb
4 @ CHECK-ARM: dfb @ encoding: [0x4c,0xf0,0x7f,0xf5]
5 @ CHECK-THUMB: dfb @ encoding: [0xbf,0xf3,0x4c,0x8f]
0 # RUN: llvm-mc -disassemble -triple armv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DFB
1 # RUN: llvm-mc -disassemble -triple armv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s | FileCheck %s --check-prefix=CHECK-NODFB
2
3 # CHECK-DFB: dfb @ encoding: [0x4c,0xf0,0x7f,0xf5]
4 # CHECK-NODFB: dsb #0xc @ encoding: [0x4c,0xf0,0x7f,0xf5]
5 [0x4c,0xf0,0x7f,0xf5]
0 # RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-DFB
1 # RUN: llvm-mc -disassemble -triple thumbv8-none-eabi -mcpu=cortex-r52 -mattr=-dfb -show-encoding < %s | FileCheck %s --check-prefix=CHECK-NODFB
2
3 # CHECK-DFB: dfb @ encoding: [0xbf,0xf3,0x4c,0x8f]
4 # CHECK-NODFB: dsb #0xc @ encoding: [0xbf,0xf3,0x4c,0x8f]
5 [0xbf,0xf3,0x4c,0x8f]