llvm.org GIT mirror llvm / da96cf2
whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128701 91177308-0d34-0410-b5e6-96231b3b80d8 Andrew Trick 9 years ago
2 changed file(s) with 68 addition(s) and 68 deletion(s). Raw diff Collapse all Expand all
3030
3131 // Open enumeration
3232 OS << "enum {\n";
33
33
3434 // For each record
3535 for (unsigned i = 0, N = DefList.size(); i < N;) {
3636 // Next record
3737 Record *Def = DefList[i];
38
38
3939 // Get and emit name
4040 OS << " " << Def->getName();
41
41
4242 // If bit flags then emit expression (1 << i)
4343 if (isBits) OS << " = " << " 1 << " << i;
4444
4545 // Depending on 'if more in the list' emit comma
4646 if (++i < N) OS << ",";
47
47
4848 OS << "\n";
4949 }
50
50
5151 // Close enumeration
5252 OS << "};\n";
5353 }
6565 // Begin feature table
6666 OS << "// Sorted (by key) array of values for CPU features.\n"
6767 << "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n";
68
68
6969 // For each feature
7070 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
7171 // Next feature
7474 const std::string &Name = Feature->getName();
7575 const std::string &CommandLineName = Feature->getValueAsString("Name");
7676 const std::string &Desc = Feature->getValueAsString("Desc");
77
77
7878 if (CommandLineName.empty()) continue;
79
79
8080 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
8181 OS << " { "
8282 << "\"" << CommandLineName << "\", "
8383 << "\"" << Desc << "\", "
8484 << Name << ", ";
8585
86 const std::vector &ImpliesList =
86 const std::vector &ImpliesList =
8787 Feature->getValueAsListOfDefs("Implies");
88
88
8989 if (ImpliesList.empty()) {
9090 OS << "0";
9191 } else {
9696 }
9797
9898 OS << " }";
99
99
100100 // Depending on 'if more in the list' emit comma
101101 if ((i + 1) < N) OS << ",";
102
102
103103 OS << "\n";
104104 }
105
105
106106 // End feature table
107107 OS << "};\n";
108108
125125 // Begin processor table
126126 OS << "// Sorted (by key) array of values for CPU subtype.\n"
127127 << "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n";
128
128
129129 // For each processor
130130 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
131131 // Next processor
132132 Record *Processor = ProcessorList[i];
133133
134134 const std::string &Name = Processor->getValueAsString("Name");
135 const std::vector &FeatureList =
135 const std::vector &FeatureList =
136136 Processor->getValueAsListOfDefs("Features");
137
137
138138 // Emit as { "cpu", "description", f1 | f2 | ... fn },
139139 OS << " { "
140140 << "\"" << Name << "\", "
141141 << "\"Select the " << Name << " processor\", ";
142
142
143143 if (FeatureList.empty()) {
144144 OS << "0";
145145 } else {
148148 if (++j < M) OS << " | ";
149149 }
150150 }
151
151
152152 // The "0" is for the "implies" section of this data structure.
153153 OS << ", 0 }";
154
154
155155 // Depending on 'if more in the list' emit comma
156156 if (++i < N) OS << ",";
157
157
158158 OS << "\n";
159159 }
160
160
161161 // End processor table
162162 OS << "};\n";
163163
184184 // Assign itinerary class a unique number
185185 ItinClassesMap[ItinClass->getName()] = i;
186186 }
187
187
188188 // Emit size of table
189189 OS<<"\nenum {\n";
190190 OS<<" ItinClassesSize = " << N << "\n";
212212 for (unsigned i = 0; i < N;) {
213213 // Next stage
214214 const Record *Stage = StageList[i];
215
215
216216 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
217217 int Cycles = Stage->getValueAsInt("Cycles");
218218 ItinString += " { " + itostr(Cycles) + ", ";
219
219
220220 // Get unit list
221221 const std::vector &UnitList = Stage->getValueAsListOfDefs("Units");
222
222
223223 // For each unit
224224 for (unsigned j = 0, M = UnitList.size(); j < M;) {
225225 // Add name and bitwise or
226226 ItinString += Name + "FU::" + UnitList[j]->getName();
227227 if (++j < M) ItinString += " | ";
228228 }
229
229
230230 int TimeInc = Stage->getValueAsInt("TimeInc");
231231 ItinString += ", " + itostr(TimeInc);
232232
255255 for (unsigned i = 0; i < N;) {
256256 // Next operand cycle
257257 const int OCycle = OperandCycleList[i];
258
258
259259 ItinString += " " + itostr(OCycle);
260260 if (++i < N) ItinString += ", ";
261261 }
291291 // Gather processor iteraries
292292 std::vector ProcItinList =
293293 Records.getAllDerivedDefinitions("ProcessorItineraries");
294
294
295295 // If just no itinerary then don't bother
296296 if (ProcItinList.size() < 2) return;
297297
331331 // Begin stages table
332332 std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n";
333333 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
334
334
335335 // Begin operand cycle table
336336 std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n";
337337 OperandCycleTable += " 0, // No itinerary\n";
339339 // Begin pipeline bypass table
340340 std::string BypassTable = "static const unsigned ForwardingPathes[] = {\n";
341341 BypassTable += " 0, // No itinerary\n";
342
342
343343 unsigned StageCount = 1, OperandCycleCount = 1;
344344 unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1;
345345 std::map ItinStageMap, ItinOperandMap;
346346 for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) {
347347 // Next record
348348 Record *Proc = ProcItinList[i];
349
349
350350 // Get processor itinerary name
351351 const std::string &Name = Proc->getName();
352
352
353353 // Skip default
354354 if (Name == "NoItineraries") continue;
355
355
356356 // Create and expand processor itinerary to cover all itinerary classes
357357 std::vector ItinList;
358358 ItinList.resize(NItinClasses);
359
359
360360 // Get itinerary data list
361361 std::vector ItinDataList = Proc->getValueAsListOfDefs("IID");
362
362
363363 // For each itinerary data
364364 for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) {
365365 // Next itinerary data
366366 Record *ItinData = ItinDataList[j];
367
367
368368 // Get string and stage count
369369 std::string ItinStageString;
370370 unsigned NStages;
393393 ItinStageEnum++;
394394 }
395395 }
396
396
397397 // Check to see if operand cycle already exists and create if it doesn't
398398 unsigned FindOperandCycle = 0;
399399 if (NOperandCycles > 0) {
401401 FindOperandCycle = ItinOperandMap[ItinOperandString];
402402 if (FindOperandCycle == 0) {
403403 // Emit as cycle, // index
404 OperandCycleTable += ItinOperandCycleString + ", // " +
404 OperandCycleTable += ItinOperandCycleString + ", // " +
405405 itostr(ItinOperandCycleEnum) + "\n";
406406 // Record Itin class number.
407 ItinOperandMap[ItinOperandCycleString] =
407 ItinOperandMap[ItinOperandCycleString] =
408408 FindOperandCycle = OperandCycleCount;
409409
410410 // Emit as bypass, // index
411 BypassTable += ItinBypassString + ", // " +
411 BypassTable += ItinBypassString + ", // " +
412412 itostr(ItinOperandCycleEnum) + "\n";
413413
414414 OperandCycleCount += NOperandCycles;
415415 ItinOperandCycleEnum++;
416416 }
417417 }
418
418
419419 // Locate where to inject into processor itinerary table
420420 const std::string &Name = ItinData->getValueAsDef("TheClass")->getName();
421421 unsigned Find = ItinClassesMap[Name];
422
422
423423 // Set up itinerary as location and location + stage count
424424 unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps");
425425 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
429429 // Inject - empty slots will be 0, 0
430430 ItinList[Find] = Intinerary;
431431 }
432
432
433433 // Add process itinerary to list
434434 ProcList.push_back(ItinList);
435435 }
449449 OS << StageTable;
450450 OS << OperandCycleTable;
451451 OS << BypassTable;
452
452
453453 // Emit size of tables
454454 OS<<"\nenum {\n";
455455 OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n";
465465 // Get an iterator for processor itinerary stages
466466 std::vector >::iterator
467467 ProcListIter = ProcList.begin();
468
468
469469 // For each processor itinerary
470470 std::vector Itins =
471471 Records.getAllDerivedDefinitions("ProcessorItineraries");
475475
476476 // Get processor itinerary name
477477 const std::string &Name = Itin->getName();
478
478
479479 // Skip default
480480 if (Name == "NoItineraries") continue;
481481
482482 // Begin processor itinerary table
483483 OS << "\n";
484484 OS << "static const llvm::InstrItinerary " << Name << "[] = {\n";
485
485
486486 // For each itinerary class
487487 std::vector &ItinList = *ProcListIter++;
488488 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
489489 InstrItinerary &Intinerary = ItinList[j];
490
491 // Emit in the form of
490
491 // Emit in the form of
492492 // { firstStage, lastStage, firstCycle, lastCycle } // index
493493 if (Intinerary.FirstStage == 0) {
494494 OS << " { 1, 0, 0, 0, 0 }";
495495 } else {
496496 OS << " { " <<
497497 Intinerary.NumMicroOps << ", " <<
498 Intinerary.FirstStage << ", " <<
499 Intinerary.LastStage << ", " <<
500 Intinerary.FirstOperandCycle << ", " <<
498 Intinerary.FirstStage << ", " <<
499 Intinerary.LastStage << ", " <<
500 Intinerary.FirstOperandCycle << ", " <<
501501 Intinerary.LastOperandCycle << " }";
502502 }
503
503
504504 OS << ", // " << j << "\n";
505505 }
506
506
507507 // End processor itinerary table
508508 OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n";
509509 OS << "};\n";
523523 OS << "\n";
524524 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
525525 << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n";
526
526
527527 // For each processor
528528 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
529529 // Next processor
532532 const std::string &Name = Processor->getValueAsString("Name");
533533 const std::string &ProcItin =
534534 Processor->getValueAsDef("ProcItin")->getName();
535
535
536536 // Emit as { "cpu", procinit },
537537 OS << " { "
538538 << "\"" << Name << "\", "
539539 << "(void *)&" << ProcItin;
540
540
541541 OS << " }";
542
542
543543 // Depending on ''if more in the list'' emit comma
544544 if (++i < N) OS << ",";
545
545
546546 OS << "\n";
547547 }
548
548
549549 // End processor table
550550 OS << "};\n";
551551
565565 std::vector ItinClassList =
566566 Records.getAllDerivedDefinitions("InstrItinClass");
567567 std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord());
568
568
569569 // Enumerate all the itinerary classes
570570 unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap,
571571 ItinClassList);
572572 // Make sure the rest is worth the effort
573573 HasItineraries = NItinClasses != 1; // Ignore NoItinerary.
574
574
575575 if (HasItineraries) {
576576 std::vector > ProcList;
577577 // Emit the stage data
593593 Records.getAllDerivedDefinitions("SubtargetFeature");
594594 std::sort(Features.begin(), Features.end(), LessRecord());
595595
596 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
597 << "// subtarget options.\n"
596 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
597 << "// subtarget options.\n"
598598 << "std::string llvm::";
599599 OS << Target;
600600 OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n"
617617 OS << " if ((Bits & " << Instance << ") != 0) "
618618 << Attribute << " = " << Value << ";\n";
619619 else
620 OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute <<
620 OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute <<
621621 " < " << Value << ") " << Attribute << " = " << Value << ";\n";
622622 }
623623
2323 namespace llvm {
2424
2525 class SubtargetEmitter : public TableGenBackend {
26
26
2727 RecordKeeper &Records;
2828 std::string Target;
2929 bool HasItineraries;
30
30
3131 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
3232 void FeatureKeyValues(raw_ostream &OS);
3333 void CPUKeyValues(raw_ostream &OS);
5151 void EmitProcessorLookup(raw_ostream &OS);
5252 void EmitData(raw_ostream &OS);
5353 void ParseFeaturesFunction(raw_ostream &OS);
54
54
5555 public:
5656 SubtargetEmitter(RecordKeeper &R) : Records(R), HasItineraries(false) {}
5757