llvm.org GIT mirror llvm / da5e568
[X86][FastISel] Simplify the logic in method X86SelectSIToFP. The target-independent selection algorithm in FastISel already knows how to select a SINT_TO_FP if the target is SSE but not AVX. On targets that have SSE but not AVX, the tablegen'd 'fastEmit' functions for ISD::SINT_TO_FP know how to select instruction X86::CVTSI2SSrr (for an i32 to f32 conversion) and X86::CVTSI2SDrr (for an i32 to f64 conversion). This patch simplifies the logic in method X86SelectSIToFP knowing that the code would not be reachable if the subtarget doesn't have AVX. No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231243 91177308-0d34-0410-b5e6-96231b3b80d8 Andrea Di Biagio 4 years ago
2 changed file(s) with 16 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
20142014 if (OpReg == 0)
20152015 return false;
20162016
2017 bool HasAVX = Subtarget->hasAVX();
20182017 const TargetRegisterClass *RC = nullptr;
20192018 unsigned Opcode;
20202019
2021 if (I->getType()->isDoubleTy() && X86ScalarSSEf64) {
2020 if (I->getType()->isDoubleTy()) {
20222021 // sitofp int -> double
2023 Opcode = HasAVX ? X86::VCVTSI2SDrr : X86::CVTSI2SDrr;
2022 Opcode = X86::VCVTSI2SDrr;
20242023 RC = &X86::FR64RegClass;
2025 } else if (I->getType()->isFloatTy() && X86ScalarSSEf32) {
2024 } else if (I->getType()->isFloatTy()) {
20262025 // sitofp int -> float
2027 Opcode = HasAVX ? X86::VCVTSI2SSrr : X86::CVTSI2SSrr;
2026 Opcode = X86::VCVTSI2SSrr;
20282027 RC = &X86::FR32RegClass;
20292028 } else
20302029 return false;
20312030
2032
2033 unsigned ImplicitDefReg = 0;
2034 if (HasAVX) {
2035 ImplicitDefReg = createResultReg(RC);
2036 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2037 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
2038 }
2039
2040 const MCInstrDesc &II = TII.get(Opcode);
2041 OpReg = constrainOperandRegClass(II, OpReg, (HasAVX ? 2 : 1));
2042
2043 unsigned ResultReg = createResultReg(RC);
2044 MachineInstrBuilder MIB;
2045 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
2046 if (ImplicitDefReg)
2047 MIB.addReg(ImplicitDefReg, RegState::Kill);
2048 MIB.addReg(OpReg);
2031 // The target-independent selection algorithm in FastISel already knows how
2032 // to select a SINT_TO_FP if the target is SSE but not AVX. This code is only
2033 // reachable if the subtarget has AVX.
2034 assert(Subtarget->hasAVX() && "Expected a subtarget with AVX!");
2035
2036 unsigned ImplicitDefReg = createResultReg(RC);
2037 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2038 TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg);
2039 unsigned ResultReg =
2040 fastEmitInst_rr(Opcode, RC, ImplicitDefReg, true, OpReg, false);
20492041 updateValueMap(I, ResultReg);
20502042 return true;
20512043 }
None ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -O0 --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -O0 --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
0 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+sse2 -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=SSE2
1 ; RUN: llc -mtriple=x86_64-unknown-unknown -mcpu=generic -mattr=+avx -fast-isel --fast-isel-abort=1 < %s | FileCheck %s --check-prefix=ALL --check-prefix=AVX
22
33
44 define double @int_to_double_rr(i32 %a) {