llvm.org GIT mirror llvm / da39404
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
7 changed file(s) with 98 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
9999 "Support MOVBE instruction">;
100100 def FeatureRDRAND : SubtargetFeature<"rdrand", "HasRDRAND", "true",
101101 "Support RDRAND instruction">;
102 def FeatureF16C : SubtargetFeature<"f16c", "HasF16C", "true",
103 "Support 16-bit floating point conversion instructions">;
102104
103105 //===----------------------------------------------------------------------===//
104106 // X86 processors supported.
474474 def HasFMA4 : Predicate<"Subtarget->hasFMA4()">;
475475 def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">;
476476 def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">;
477 def HasF16C : Predicate<"Subtarget->hasF16C()">;
477478 def FPStackf32 : Predicate<"!Subtarget->hasXMM()">;
478479 def FPStackf64 : Predicate<"!Subtarget->hasXMMInt()">;
479480 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
67526752 YMM8, YMM9, YMM10, YMM11, YMM12, YMM13, YMM14, YMM15] in {
67536753 // Zero All YMM registers
67546754 def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall",
6755 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
6755 [(int_x86_avx_vzeroall)]>, TB, VEX, VEX_L, Requires<[HasAVX]>;
67566756
67576757 // Zero Upper bits of YMM registers
67586758 def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper",
67596759 [(int_x86_avx_vzeroupper)]>, TB, VEX, Requires<[HasAVX]>;
67606760 }
6761
6762 //===----------------------------------------------------------------------===//
6763 // Half precision conversion instructions
6764 //
6765 let Predicates = [HasF16C] in {
6766 def VCVTPH2PSrm : I<0x13, MRMSrcMem, (outs VR128:$dst), (ins f64mem:$src),
6767 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6768 def VCVTPH2PSrr : I<0x13, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
6769 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6770 def VCVTPH2PSYrm : I<0x13, MRMSrcMem, (outs VR256:$dst), (ins f128mem:$src),
6771 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6772 def VCVTPH2PSYrr : I<0x13, MRMSrcReg, (outs VR256:$dst), (ins VR128:$src),
6773 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, T8, OpSize, VEX;
6774 def VCVTPS2PHmr : Ii8<0x1D, MRMDestMem, (outs f64mem:$dst),
6775 (ins VR128:$src1, i32i8imm:$src2),
6776 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6777 TA, OpSize, VEX;
6778 def VCVTPS2PHrr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
6779 (ins VR128:$src1, i32i8imm:$src2),
6780 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6781 TA, OpSize, VEX;
6782 def VCVTPS2PHYmr : Ii8<0x1D, MRMDestMem, (outs f128mem:$dst),
6783 (ins VR256:$src1, i32i8imm:$src2),
6784 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6785 TA, OpSize, VEX;
6786 def VCVTPS2PHYrr : Ii8<0x1D, MRMDestReg, (outs VR128:$dst),
6787 (ins VR256:$src1, i32i8imm:$src2),
6788 "vcvtps2ph\t{$src2, $src1, $dst|$dst, $src1, $src2}", []>,
6789 TA, OpSize, VEX;
6790 }
205205 HasMOVBE = IsIntel && ((ECX >> 22) & 0x1); ToggleFeature(X86::FeatureMOVBE);
206206 HasPOPCNT = IsIntel && ((ECX >> 23) & 0x1); ToggleFeature(X86::FeaturePOPCNT);
207207 HasAES = IsIntel && ((ECX >> 25) & 0x1); ToggleFeature(X86::FeatureAES);
208 HasF16C = IsIntel && ((ECX >> 29) & 0x1); ToggleFeature(X86::FeatureF16C);
208209 HasRDRAND = IsIntel && ((ECX >> 30) & 0x1); ToggleFeature(X86::FeatureRDRAND);
209210 HasCmpxchg16b = ((ECX >> 13) & 0x1); ToggleFeature(X86::FeatureCMPXCHG16B);
210211
257258 , HasFMA4(false)
258259 , HasMOVBE(false)
259260 , HasRDRAND(false)
261 , HasF16C(false)
260262 , IsBTMemSlow(false)
261263 , IsUAMemFast(false)
262264 , HasVectorUAMem(false)
8989 /// HasFMA4 - Target has 4-operand fused multiply-add
9090 bool HasFMA4;
9191
92 /// HasMOVBE - True if the processor has the MOVBE instruction;
92 /// HasMOVBE - True if the processor has the MOVBE instruction.
9393 bool HasMOVBE;
9494
95 /// HasRDRAND - True if the processor has the RDRAND instruction;
95 /// HasRDRAND - True if the processor has the RDRAND instruction.
9696 bool HasRDRAND;
97
98 /// HasF16C - Processor has 16-bit floating point conversion instructions.
99 bool HasF16C;
97100
98101 /// IsBTMemSlow - True if BT (bit test) of memory instructions are slow.
99102 bool IsBTMemSlow;
179182 bool hasFMA4() const { return HasFMA4; }
180183 bool hasMOVBE() const { return HasMOVBE; }
181184 bool hasRDRAND() const { return HasRDRAND; }
185 bool hasF16C() const { return HasF16C; }
182186 bool isBTMemSlow() const { return IsBTMemSlow; }
183187 bool isUnalignedMemAccessFast() const { return IsUAMemFast; }
184188 bool hasVectorUAMem() const { return HasVectorUAMem; }
431431 # CHECK: xsaveopt (%rax)
432432 0x0f 0xae 0x30
433433
434 # CHECK rdfsbasel %eax
434 # CHECK: rdfsbasel %eax
435435 0xf3 0x0f 0xae 0xc0
436436
437 # CHECK rdgsbasel %eax
437 # CHECK: rdgsbasel %eax
438438 0xf3 0x0f 0xae 0xc8
439439
440 # CHECK wrfsbasel %eax
440 # CHECK: wrfsbasel %eax
441441 0xf3 0x0f 0xae 0xd0
442442
443 # CHECK wrgsbasel %eax
443 # CHECK: wrgsbasel %eax
444444 0xf3 0x0f 0xae 0xd8
445445
446 # CHECK rdfsbaseq %rax
446 # CHECK: rdfsbaseq %rax
447447 0xf3 0x48 0x0f 0xae 0xc0
448448
449 # CHECK rdgsbaseq %rax
449 # CHECK: rdgsbaseq %rax
450450 0xf3 0x48 0x0f 0xae 0xc8
451451
452 # CHECK wrfsbaseq %rax
452 # CHECK: wrfsbaseq %rax
453453 0xf3 0x48 0x0f 0xae 0xd0
454454
455 # CHECK wrgsbaseq %rax
455 # CHECK: wrgsbaseq %rax
456456 0xf3 0x48 0x0f 0xae 0xd8
457
458 # CHECK: vcvtph2ps %xmm0, %xmm0
459 0xc4 0xe2 0x79 0x13 0xc0
460
461 # CHECK: vcvtph2ps (%rax), %xmm0
462 0xc4 0xe2 0x79 0x13 0x00
463
464 # CHECK: vcvtph2ps %xmm0, %ymm0
465 0xc4 0xe2 0x7d 0x13 0xc0
466
467 # CHECK: vcvtph2ps (%rax), %ymm0
468 0xc4 0xe2 0x7d 0x13 0x00
469
470 # CHECK: vcvtps2ph $0, %xmm0, %xmm0
471 0xc4 0xe3 0x79 0x1d 0xc0 0x00
472
473 # CHECK: vcvtps2ph $0, %xmm0, (%rax)
474 0xc4 0xe3 0x79 0x1d 0x00 0x00
475
476 # CHECK: vcvtps2ph $0, %ymm0, %xmm0
477 0xc4 0xe3 0x7d 0x1d 0xc0 0x00
478
479 # CHECK: vcvtps2ph $0, %ymm0, (%rax)
480 0xc4 0xe3 0x7d 0x1d 0x00 0x00
440440
441441 # CHECK: xsaveopt (%eax)
442442 0x0f 0xae 0x30
443
444 # CHECK: vcvtph2ps %xmm0, %xmm0
445 0xc4 0xe2 0x79 0x13 0xc0
446
447 # CHECK: vcvtph2ps (%eax), %xmm0
448 0xc4 0xe2 0x79 0x13 0x00
449
450 # CHECK: vcvtph2ps %xmm0, %ymm0
451 0xc4 0xe2 0x7d 0x13 0xc0
452
453 # CHECK: vcvtph2ps (%eax), %ymm0
454 0xc4 0xe2 0x7d 0x13 0x00
455
456 # CHECK: vcvtps2ph $0, %xmm0, %xmm0
457 0xc4 0xe3 0x79 0x1d 0xc0 0x00
458
459 # CHECK: vcvtps2ph $0, %xmm0, (%eax)
460 0xc4 0xe3 0x79 0x1d 0x00 0x00
461
462 # CHECK: vcvtps2ph $0, %ymm0, %xmm0
463 0xc4 0xe3 0x7d 0x1d 0xc0 0x00
464
465 # CHECK: vcvtps2ph $0, %ymm0, (%eax)
466 0xc4 0xe3 0x7d 0x1d 0x00 0x00