llvm.org GIT mirror llvm / d9b0b02
Fix typos found by http://github.com/lyda/misspell-check git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157885 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 7 years ago
59 changed file(s) with 73 addition(s) and 73 deletion(s). Raw diff Collapse all Expand all
109109

if statement

110110
111111

The exp parameter is the condition. The c parameter is

112 the expected comparision value. If it is equal to 1 (true), the condition is
112 the expected comparison value. If it is equal to 1 (true), the condition is
113113 likely to be true, in other case condition is likely to be false. For example:
114114

115115
330330
331331
LLVM_TABLEGEN:STRING
332332
Full path to a native TableGen executable (usually
333 named tblgen). This is intented for cross-compiling: if the
333 named tblgen). This is intended for cross-compiling: if the
334334 user sets this variable, no native TableGen will be created.
335335
336336
LLVM_LIT_ARGS:STRING
441441 ... log message ...
442442
443443
444 where should be the name of a preceeding reported test,
444 where should be the name of a preceding reported test,
445445 delineator> is a string of '\*' characters *at least* four characters long (the
446446 recommended length is 20), and is an arbitrary (unparsed)
447447 string.
6060 Write out new *LLVMBuild.txt* files based on the loaded components. This is
6161 useful for auto-upgrading the schema of the files. **llvm-build** will try to a
6262 limited extent to preserve the comments which were written in the original
63 source file, although at this time it only preserves block comments that preceed
63 source file, although at this time it only preserves block comments that precede
6464 the section names in the *LLVMBuild* files.
6565
6666
16161616
16171617
16181618

1619 This file demotes all registers to memory references. It is intented to be
1619 This file demotes all registers to memory references. It is intended to be
16201620 the inverse of -mem2reg. By converting to
16211621 load instructions, the only values live across basic blocks are
16221622 alloca instructions and load instructions before
27112711 has address attributes: DW_AT_low_pc, DW_AT_high_pc, DW_AT_ranges or
27122712 DW_AT_entry_pc. It also contains DW_TAG_variable DIEs that have a DW_OP_addr
27132713 in the location (global and static variables). All global and static variables
2714 should be included, including those scoped withing functions and classes. For
2714 should be included, including those scoped within functions and classes. For
27152715 example using the following code:

27162716
27172717

                  
                
1212 research projects.
1313
1414 Similarly, documentation is broken down into several high-level groupings
15 targetted at different audiences:
15 targeted at different audiences:
1616
1717 * **Design & Overview**
1818
12561256
12571257 // FIXME: Redundant storage which, beyond utilizing value of
12581258 // caughtResultStore for unwindException storage, may be alleviated
1259 // alltogether with a block rearrangement
1259 // altogether with a block rearrangement
12601260 builder.CreateStore(caughtResult, caughtResultStorage);
12611261 builder.CreateStore(unwindException, exceptionStorage);
12621262 builder.CreateStore(ourExceptionThrownState, exceptionCaughtFlag);
216216 divBlockFreq(BB, BranchProbability(Numerator, EntryFreq));
217217 }
218218
219 /// doLoop - Propagate block frequency down throught the loop.
219 /// doLoop - Propagate block frequency down through the loop.
220220 void doLoop(BlockT *Head, BlockT *Tail) {
221221 DEBUG(dbgs() << "doLoop(" << getBlockName(Head) << ", "
222222 << getBlockName(Tail) << ")\n");
176176 /// @param OffsetInBits Member offset.
177177 /// @param Flags Flags to encode member attribute, e.g. private
178178 /// @param Ty Parent type.
179 /// @param PropertyName Name of the Objective C property assoicated with
179 /// @param PropertyName Name of the Objective C property associated with
180180 /// this ivar.
181181 /// @param GetterName Name of the Objective C property getter selector.
182182 /// @param SetterName Name of the Objective C property setter selector.
581581 // TRAP - Trapping instruction
582582 TRAP,
583583
584 // DEBUGTRAP - Trap intented to get the attention of a debugger.
584 // DEBUGTRAP - Trap intended to get the attention of a debugger.
585585 DEBUGTRAP,
586586
587587 // PREFETCH - This corresponds to a prefetch intrinsic. It takes chains are
229229 ///
230230 LoopDependencies LoopRegs;
231231
232 /// DbgValues - Remember instruction that preceeds DBG_VALUE.
232 /// DbgValues - Remember instruction that precedes DBG_VALUE.
233233 /// These are generated by buildSchedGraph but persist so they can be
234234 /// referenced when emitting the final schedule.
235235 typedef std::vector >
575575 nextItr = getIndexAfter(mi).listEntry();
576576 prevItr = prior(nextItr);
577577 } else {
578 // Insert mi's index immediately after the preceeding instruction.
578 // Insert mi's index immediately after the preceding instruction.
579579 prevItr = getIndexBefore(mi).listEntry();
580580 nextItr = llvm::next(prevItr);
581581 }
22382238 /// getNumClauses - Get the number of clauses for this landing pad.
22392239 unsigned getNumClauses() const { return getNumOperands() - 1; }
22402240
2241 /// reserveClauses - Grow the size of the operand list to accomodate the new
2241 /// reserveClauses - Grow the size of the operand list to accommodate the new
22422242 /// number of clauses.
22432243 void reserveClauses(unsigned Size) { growOperands(Size); }
22442244
8989
9090 /// @brief Create a Binary from Source, autodetecting the file type.
9191 ///
92 /// @param Source The data to create the Binary from. Ownership is transfered
92 /// @param Source The data to create the Binary from. Ownership is transferred
9393 /// to Result if successful. If an error is returned, Source is destroyed
9494 /// by createBinary before returning.
9595 /// @param Result A pointer to the resulting Binary if no error occured.
216216 }
217217 };
218218
219 /// Elf_Verdaux: This is the structure of auxilary data in the SHT_GNU_verdef
219 /// Elf_Verdaux: This is the structure of auxiliary data in the SHT_GNU_verdef
220220 /// section (.gnu.version_d). This structure is identical for ELF32 and ELF64.
221221 template
222222 struct Elf_Verdaux_Impl {
101101 return (const APInt&)ConstantIntVal->getValue();
102102 }
103103
104 // Propogate APInt operators.
104 // Propagate APInt operators.
105105 // Note, that
106106 // /,/=,>>,>>= are not implemented in APInt.
107107 // <<= is implemented for unsigned RHS, but not implemented for APInt RHS.
21142114 LLVMValueRef LLVMGetNextInstruction(LLVMValueRef Inst);
21152115
21162116 /**
2117 * Obtain the instruction that occured before this one.
2117 * Obtain the instruction that occurred before this one.
21182118 *
21192119 * If the instruction is the first instruction in a basic block, NULL
21202120 * will be returned.
177177
178178 /// \brief Disable SROA for the candidate marked by this cost iterator.
179179 ///
180 /// This markes the candidate as no longer viable for SROA, and adds the cost
180 /// This marks the candidate as no longer viable for SROA, and adds the cost
181181 /// savings associated with it back into the inline cost measurement.
182182 void CallAnalyzer::disableSROA(DenseMap::iterator CostIt) {
183183 // If we're no longer able to perform SROA we need to undo its cost savings
905905 if (!Pair.second) {
906906 if (CacheInfo->Size < Loc.Size) {
907907 // The query's Size is greater than the cached one. Throw out the
908 // cached data and procede with the query at the greater size.
908 // cached data and proceed with the query at the greater size.
909909 CacheInfo->Pair = BBSkipFirstBlockPair();
910910 CacheInfo->Size = Loc.Size;
911911 for (NonLocalDepInfo::iterator DI = CacheInfo->NonLocalDeps.begin(),
18371837
18381838 /// Compute the result of "n choose k", the binomial coefficient. If an
18391839 /// intermediate computation overflows, Overflow will be set and the return will
1840 /// be garbage. Overflow is not cleared on absense of overflow.
1840 /// be garbage. Overflow is not cleared on absence of overflow.
18411841 static uint64_t Choose(uint64_t n, uint64_t k, bool &Overflow) {
18421842 // We use the multiplicative formula:
18431843 // n(n-1)(n-2)...(n-(k-1)) / k(k-1)(k-2)...1 .
14651465 }
14661466
14671467 /// findHoistingInsertPosAndDeps - Find the location to move common instructions
1468 /// in successors to. The location is ususally just before the terminator,
1468 /// in successors to. The location is usually just before the terminator,
14691469 /// however if the terminator is a conditional branch and its previous
14701470 /// instruction is the flag setting instruction, the previous instruction is
14711471 /// the preferred location. This function also gathers uses and defs of the
200200 // fallthrough edge.
201201 if (!Prior->isSuccessor(End))
202202 goto next_pred;
203 // Otherwise we can stop scanning and procede to move the blocks.
203 // Otherwise we can stop scanning and proceed to move the blocks.
204204 break;
205205 }
206206 // If we hit a switch or something complicated, don't move anything
227227 void CriticalAntiDepBreaker::ScanInstruction(MachineInstr *MI,
228228 unsigned Count) {
229229 // Update liveness.
230 // Proceding upwards, registers that are defed but not used in this
230 // Proceeding upwards, registers that are defed but not used in this
231231 // instruction are now dead.
232232
233233 if (!TII->isPredicated(MI)) {
5858
5959 // Pointer to the next DomainValue in a chain. When two DomainValues are
6060 // merged, Victim.Next is set to point to Victor, so old DomainValue
61 // references can be updated by folowing the chain.
61 // references can be updated by following the chain.
6262 DomainValue *Next;
6363
6464 // Twiddleable instructions using or defining these registers.
1010 // structure and branch probability estimates.
1111 //
1212 // The pass strives to preserve the structure of the CFG (that is, retain
13 // a topological ordering of basic blocks) in the absense of a *strong* signal
13 // a topological ordering of basic blocks) in the absence of a *strong* signal
1414 // to the contrary from probabilities. However, within the CFG structure, it
1515 // attempts to choose an ordering which favors placing more likely sequences of
1616 // blocks adjacent to each other.
179179 /// \brief Allocator and owner of BlockChain structures.
180180 ///
181181 /// We build BlockChains lazily by merging together high probability BB
182 /// sequences acording to the "Algo2" in the paper mentioned at the top of
182 /// sequences according to the "Algo2" in the paper mentioned at the top of
183183 /// the file. To reduce malloc traffic, we allocate them using this slab-like
184184 /// allocator, and destroy them after the pass completes.
185185 SpecificBumpPtrAllocator ChainAllocator;
328328 // the MBPI analysis, we manually compute probabilities using the edge
329329 // weights. This is suboptimal as it means that the somewhat subtle
330330 // definition of edge weight semantics is encoded here as well. We should
331 // improve the MBPI interface to effeciently support query patterns such as
331 // improve the MBPI interface to efficiently support query patterns such as
332332 // this.
333333 uint32_t BestWeight = 0;
334334 uint32_t WeightScale = 0;
10521052 ///
10531053 /// A separate pass to compute interesting statistics for evaluating block
10541054 /// placement. This is separate from the actual placement pass so that they can
1055 /// be computed in the absense of any placement transformations or when using
1055 /// be computed in the absence of any placement transformations or when using
10561056 /// alternative placement strategies.
10571057 class MachineBlockPlacementStats : public MachineFunctionPass {
10581058 /// \brief A handle to the branch probability pass.
4949
5050 const TargetMachine &tm = (*IS->MF).getTarget();
5151 ResourcesModel = tm.getInstrInfo()->CreateTargetScheduleState(&tm,NULL);
52 // This hard requirment could be relaxed, but for now
52 // This hard requirement could be relaxed, but for now
5353 // do not let it procede.
5454 assert (ResourcesModel && "Unimplemented CreateTargetScheduleState.");
5555
352352 }
353353
354354 /// Estimates change in reg pressure from this SU.
355 /// It is acheived by trivial tracking of defined
355 /// It is achieved by trivial tracking of defined
356356 /// and used vregs in dependent instructions.
357357 /// The RawPressure flag makes this function to ignore
358358 /// existing reg file sizes, and report raw def/use
843843 }
844844
845845 /// clearDanglingDebugInfo - Clear the dangling debug information
846 /// map. This function is seperated from the clear so that debug
846 /// map. This function is separated from the clear so that debug
847847 /// information that is dangling in a basic block can be properly
848848 /// resolved in a different basic block. This allows the
849849 /// SelectionDAG to resolve dangling debug information attached
28092809 }
28102810
28112811 // Utility for visitShuffleVector - Return true if every element in Mask,
2812 // begining from position Pos and ending in Pos+Size, falls within the
2812 // beginning from position Pos and ending in Pos+Size, falls within the
28132813 // specified sequential range [L, L+Pos). or is undef.
28142814 static bool isSequentialInRange(const SmallVectorImpl &Mask,
28152815 unsigned Pos, unsigned Size, int Low) {
339339 void clear();
340340
341341 /// clearDanglingDebugInfo - Clear the dangling debug information
342 /// map. This function is seperated from the clear so that debug
342 /// map. This function is separated from the clear so that debug
343343 /// information that is dangling in a basic block can be properly
344344 /// resolved in a different basic block. This allows the
345345 /// SelectionDAG to resolve dangling debug information attached
20072007 }
20082008 }
20092009
2010 // Make sure we're not loosing bits from the constant.
2010 // Make sure we're not losing bits from the constant.
20112011 if (MinBits < C1.getBitWidth() && MinBits > C1.getActiveBits()) {
20122012 EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits);
20132013 if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {
144144 // in the relocation list where it's stored.
145145 typedef SmallVector RelocationList;
146146 // Relocations to sections already loaded. Indexed by SectionID which is the
147 // source of the address. The target where the address will be writen is
147 // source of the address. The target where the address will be written is
148148 // SectionID/Offset in the relocation itself.
149149 DenseMap Relocations;
150150
471471 }
472472
473473 /// Process the specified .incbin file by seaching for it in the include paths
474 /// then just emiting the byte contents of the file to the streamer. This
474 /// then just emitting the byte contents of the file to the streamer. This
475475 /// returns true on failure.
476476 bool AsmParser::ProcessIncbinFile(const std::string &Filename) {
477477 std::string IncludedFile;
26972697 multiclass arm_ldst_mult
26982698 InstrItinClass itin, InstrItinClass itin_upd> {
26992699 // IA is the default, so no need for an explicit suffix on the
2700 // mnemonic here. Without it is the cannonical spelling.
2700 // mnemonic here. Without it is the canonical spelling.
27012701 def IA :
27022702 AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
27032703 IndexModeNone, f, itin,
34113411
34123412 // FIXME: The v5 pseudos are only necessary for the additional Constraint
34133413 // property. Remove them when it's possible to add those properties
3414 // on an individual MachineInstr, not just an instuction description.
3414 // on an individual MachineInstr, not just an instruction description.
34153415 let isCommutable = 1, TwoOperandAliasConstraint = "$Rn = $Rd" in {
34163416 def MUL : AsMul1I32<0b0000000, (outs GPRnopc:$Rd),
34173417 (ins GPRnopc:$Rn, GPRnopc:$Rm),
14021402
14031403 // For round-trip assembly/disassembly, we have to handle a CPS instruction
14041404 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1405 // a useful extention and assembles to defined behaviour (the insn does
1405 // a useful extension and assembles to defined behaviour (the insn does
14061406 // nothing).
14071407 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
14081408 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
67886788 case ARM_AM::ror: newOpc = ARM::t2RORri; isNarrow = false; break;
67896789 case ARM_AM::rrx: isNarrow = false; newOpc = ARM::t2RRX; break;
67906790 }
6791 unsigned Ammount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6792 if (Ammount == 32) Ammount = 0;
6791 unsigned Amount = ARM_AM::getSORegOffset(Inst.getOperand(2).getImm());
6792 if (Amount == 32) Amount = 0;
67936793 TmpInst.setOpcode(newOpc);
67946794 TmpInst.addOperand(Inst.getOperand(0)); // Rd
67956795 if (isNarrow)
67976797 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
67986798 TmpInst.addOperand(Inst.getOperand(1)); // Rn
67996799 if (newOpc != ARM::t2RRX)
6800 TmpInst.addOperand(MCOperand::CreateImm(Ammount));
6800 TmpInst.addOperand(MCOperand::CreateImm(Amount));
68016801 TmpInst.addOperand(Inst.getOperand(3)); // CondCode
68026802 TmpInst.addOperand(Inst.getOperand(4));
68036803 if (!isNarrow)
73997399 return Error(IDLoc, "invalid instruction",
74007400 ((ARMOperand*)Operands[0])->getLocRange());
74017401 case Match_ConversionFail:
7402 // The converter function will have already emited a diagnostic.
7402 // The converter function will have already emitted a diagnostic.
74037403 return true;
74047404 case Match_RequiresNotITBlock:
74057405 return Error(IDLoc, "flag setting instruction only valid outside IT block");
490490 TII->get(Hexagon::NEG), CountReg).addReg(CountReg1);
491491 }
492492
493 // Add the Loop instruction to the begining of the loop.
493 // Add the Loop instruction to the beginning of the loop.
494494 BuildMI(*Preheader, InsertPos, InsertPos->getDebugLoc(),
495495 TII->get(Hexagon::LOOP0_r)).addMBB(LoopStart).addReg(CountReg);
496496 } else {
507507
508508 // Build a sequence of copy-to-reg nodes chained together with token
509509 // chain and flag operands which copy the outgoing args into registers.
510 // The InFlag in necessary since all emited instructions must be
510 // The InFlag in necessary since all emitted instructions must be
511511 // stuck together.
512512 SDValue InFlag;
513513 if (!isTailCall) {
527527 // than necessary, because it means that each store effectively depends
528528 // on every argument instead of just those arguments it would clobber.
529529 //
530 // Do not flag preceeding copytoreg stuff together with the following stuff.
530 // Do not flag preceding copytoreg stuff together with the following stuff.
531531 InFlag = SDValue();
532532 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
533533 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
370370 def u64ImmPred : PatLeaf<(i64 imm), [{
371371 // immS16 predicate - True if the immediate fits in a 16-bit sign extended
372372 // field.
373 // Adding "N ||" to supress gcc unused warning.
373 // Adding "N ||" to suppress gcc unused warning.
374374 return (N || true);
375375 }]>;
376376
30283028 (i64 (SXTW (i32 (SXTB (i32 (EXTRACT_SUBREG (i64 DoubleRegs:$src1),
30293029 subreg_loreg))))))>;
30303030
3031 // We want to prevent emiting pnot's as much as possible.
3031 // We want to prevent emitting pnot's as much as possible.
30323032 // Map brcond with an unsupported setcc to a JMP_cNot.
30333033 def : Pat <(brcond (i1 (setne (i32 IntRegs:$src1), (i32 IntRegs:$src2))),
30343034 bb:$offset),
88 //
99 // This implements NewValueJump pass in Hexagon.
1010 // Ideally, we should merge this as a Peephole pass prior to register
11 // allocation, but becuase we have a spill in between the feeder and new value
11 // allocation, but because we have a spill in between the feeder and new value
1212 // jump instructions, we are forced to write after register allocation.
13 // Having said that, we should re-attempt to pull this ealier at some piont
13 // Having said that, we should re-attempt to pull this earlier at some point
1414 // in future.
1515
1616 // The basic approach looks for sequence of predicated jump, compare instruciton
None //===- HexagonRemoveExtendArgs.cpp - Remove unecessary argument sign extends =//
0 //===- HexagonRemoveExtendArgs.cpp - Remove unnecessary argument sign extends //
11 //
22 // The LLVM Compiler Infrastructure
33 //
1515 #include "llvm/MC/MCInstPrinter.h"
1616
1717 namespace llvm {
18 // These enumeration declarations were orignally in MipsInstrInfo.h but
18 // These enumeration declarations were originally in MipsInstrInfo.h but
1919 // had to be moved here to avoid circular dependencies between
2020 // LLVMMipsCodeGen and LLVMMipsAsmPrinter.
2121 namespace Mips {
189189 // We emit only the last instruction here.
190190 //
191191 // GNU linker requires that the first two instructions appear at the beginning
192 // of a funtion and no instructions be inserted before or between them.
192 // of a function and no instructions be inserted before or between them.
193193 // The two instructions are emitted during lowering to MC layer in order to
194194 // avoid any reordering.
195195 //
845845 [(set Float32Regs:$dst, (fadd
846846 (fmul Float32Regs:$a, Float32Regs:$b),
847847 Float32Regs:$c))]>, Requires<[Pred]>;
848 // This is to WAR a wierd bug in Tablegen that does not automatically
848 // This is to WAR a weird bug in Tablegen that does not automatically
849849 // generate the following permutated rule rrr2 from the above rrr.
850850 // So we explicitly add it here. This happens to FMA32 only.
851851 // See the comments at FMAD32 and FMA32 for more information.
129129 // The hardware keeps track of how many FP registers are live, so we have
130130 // to model that exactly. Usually, each live register corresponds to an
131131 // FP register, but when dealing with calls, returns, and inline
132 // assembly, it is sometimes neccesary to have live scratch registers.
132 // assembly, it is sometimes necessary to have live scratch registers.
133133 unsigned Stack[8]; // FP Registers in each stack slot...
134134 unsigned StackTop; // The current top of the FP stack.
135135
31903190 return false;
31913191 }
31923192
3193 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining
3193 /// isSequentialOrUndefInRange - Return true if every element in Mask, beginning
31943194 /// from position Pos and ending in Pos+Size, falls within the specified
31953195 /// sequential range (L, L+Pos]. or is undef.
31963196 static bool isSequentialOrUndefInRange(ArrayRef Mask,
63326332 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG);
63336333
63346334 if (NumElems == 4)
6335 // If we don't care about the second element, procede to use movss.
6335 // If we don't care about the second element, proceed to use movss.
63366336 if (SVOp->getMaskElt(1) != -1)
63376337 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG);
63386338 }
204204 }
205205
206206
207 // The entry MBB for the function may set the inital state to dirty if
207 // The entry MBB for the function may set the initial state to dirty if
208208 // the function receives any YMM incoming arguments
209209 if (MBB == MF.begin()) {
210210 EntryState = ST_CLEAN;
3535 STATISTIC(NumDeleted, "Number of functions deleted because all callers found");
3636 STATISTIC(NumMergedAllocas, "Number of allocas merged together");
3737
38 // This weirdly named statistic tracks the number of times that, when attemting
38 // This weirdly named statistic tracks the number of times that, when attempting
3939 // to inline a function A into B, we analyze the callers of B in order to see
4040 // if those would be more profitable and blocked inline steps.
4141 STATISTIC(NumCallerCallersAnalyzed, "Number of caller-callers analyzed");
21932193 return &LU;
21942194 // This is the formula where all the registers and symbols matched;
21952195 // there aren't going to be any others. Since we declined it, we
2196 // can skip the rest of the formulae and procede to the next LSRUse.
2196 // can skip the rest of the formulae and proceed to the next LSRUse.
21972197 break;
21982198 }
21992199 }
811811 case IC_FusedRetainAutorelease:
812812 case IC_FusedRetainAutoreleaseRV:
813813 // These functions don't access any memory visible to the compiler.
814 // Note that this doesn't include objc_retainBlock, becuase it updates
814 // Note that this doesn't include objc_retainBlock, because it updates
815815 // pointers when it copies block data.
816816 return NoModRef;
817817 default:
11631163 ++Count;
11641164 if (Count == 1)
11651165 continue;
1166 // Move an even number of occurences to Factors.
1166 // Move an even number of occurrences to Factors.
11671167 Count &= ~1U;
11681168 Idx -= Count;
11691169 FactorPowerSum += Count;
66 //
77 //===----------------------------------------------------------------------===//
88 //
9 // This file demotes all registers to memory references. It is intented to be
9 // This file demotes all registers to memory references. It is intended to be
1010 // the inverse of PromoteMemoryToRegister. By converting to loads, the only
1111 // values live across basic blocks are allocas and loads before phi nodes.
1212 // It is intended that this should make CFG hacking much easier.
705705 CollisionMap[PN] = Old;
706706 break;
707707 }
708 // Procede to the next PHI in the list.
708 // Proceed to the next PHI in the list.
709709 OtherPN = I->second;
710710 }
711711 }
130130 /// There are two value maps that are defined and used. VMap is
131131 /// for the values in the current loop instance. LVMap contains
132132 /// the values from the last loop instance. We need the LVMap values
133 /// to update the inital values for the current loop instance.
133 /// to update the initial values for the current loop instance.
134134 ///
135135 static void CloneLoopBlocks(Loop *L,
136136 bool FirstCopy,
17221722 }
17231723
17241724 case IITDescriptor::Argument:
1725 // Two cases here - If this is the second occurrance of an argument, verify
1725 // Two cases here - If this is the second occurrence of an argument, verify
17261726 // that the later instance matches the previous instance.
17271727 if (D.getArgumentNumber() < ArgTys.size())
17281728 return Ty != ArgTys[D.getArgumentNumber()];
344344 EXPECT_EQ(hash_combine_range(arr1, arr1 + 6),
345345 hash_combine(i1, i2, i3, i4, i5, i6));
346346
347 // Hashing a sequence of heterogenous types which *happen* to all produce the
347 // Hashing a sequence of heterogeneous types which *happen* to all produce the
348348 // same data for hashing produces the same as a range-based hash of the
349349 // fundamental values.
350350 const size_t s1 = 1024, s2 = 8888, s3 = 9000000;
323323
324324 Passes.run(M);
325325 // Some passes must be rerun because a pass that modified the
326 // module/function was run inbetween
326 // module/function was run in between
327327 EXPECT_EQ(2, mNDM->run);
328328 EXPECT_EQ(1, mNDNM->run);
329329 EXPECT_EQ(1, mNDM2->run);
109109 if (CoveredBySubRegs && !ExplicitSubRegs.empty())
110110 ExplicitSubRegs.front()->LeadingSuperRegs.push_back(this);
111111
112 // Add ad hoc alias links. This is a symmetric relationship betwen two
112 // Add ad hoc alias links. This is a symmetric relationship between two
113113 // registers, so build a symmetric graph by adding links in both ends.
114114 std::vector Aliases = TheDef->getValueAsListOfDefs("Aliases");
115115 for (unsigned i = 0, e = Aliases.size(); i != e; ++i) {
311311 // dsub_2 -> ssub_0
312312 //
313313 // We pick the latter composition because another register may have [dsub_0,
314 // dsub_1, dsub_2] subregs without neccessarily having a qsub_1 subreg. The
314 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
315315 // dsub_2 -> ssub_0 composition can be shared.
316316 while (!Indices.empty() && !Orphans.empty()) {
317317 CodeGenSubRegIndex *Idx = Indices.pop_back_val();
918918 RC.SubClasses |= SubRC->SubClasses;
919919 }
920920
921 // Sweep up missed clique members. They will be immediately preceeding RC.
921 // Sweep up missed clique members. They will be immediately preceding RC.
922922 for (unsigned s = rci - 1; s && testSubClass(&RC, RegClasses[s - 1]); --s)
923923 RC.SubClasses.set(s - 1);
924924 }
5454 Create the given directory path for installation, including any parents.
5555 """
5656
57 # os.makedirs considers it an error to be called with an existant path.
57 # os.makedirs considers it an error to be called with an existent path.
5858 if not os.path.exists(path):
5959 os.makedirs(path)
6060