llvm.org GIT mirror llvm / d9a3bad
Change encoding of instruction operands in bitcode binaries to be relative to the instruction position. The old encoding would give an absolute ID which counts up within a function, and only resets at the next function. I.e., Instead of having: ... = icmp eq i32 n-1, n-2 br i1 ..., label %bb1, label %bb2 it will now be roughly: ... = icmp eq i32 1, 2 br i1 1, label %bb1, label %bb2 This makes it so that ids remain relatively small and can be encoded in fewer bits. With this encoding, forward reference operands will be given negative-valued IDs. Use signed VBRs for the most common case of forward references, which is phi instructions. To retain backward compatibility we bump the bitcode version from 0 to 1 to distinguish between the different encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165739 91177308-0d34-0410-b5e6-96231b3b80d8 Jan Wen Voung 8 years ago
5 changed file(s) with 238 addition(s) and 93 deletion(s). Raw diff Collapse all Expand all
408408 }
409409
410410 /// EnterSubBlock - Having read the ENTER_SUBBLOCK abbrevid, enter
411 /// the block, and return true if the block is valid.
411 /// the block, and return true if the block has an error.
412412 bool EnterSubBlock(unsigned BlockID, unsigned *NumWordsP = 0) {
413413 // Save the current block's state on BlockScope.
414414 BlockScope.push_back(Block(CurCodeSize));
890890 }
891891 }
892892
893 /// DecodeSignRotatedValue - Decode a signed value stored with the sign bit in
893 /// decodeSignRotatedValue - Decode a signed value stored with the sign bit in
894894 /// the LSB for dense VBR encoding.
895 static uint64_t DecodeSignRotatedValue(uint64_t V) {
895 uint64_t BitcodeReader::decodeSignRotatedValue(uint64_t V) {
896896 if ((V & 1) == 0)
897897 return V >> 1;
898898 if (V != 1)
942942 static APInt ReadWideAPInt(ArrayRef Vals, unsigned TypeBits) {
943943 SmallVector Words(Vals.size());
944944 std::transform(Vals.begin(), Vals.end(), Words.begin(),
945 DecodeSignRotatedValue);
945 BitcodeReader::decodeSignRotatedValue);
946946
947947 return APInt(TypeBits, Words);
948948 }
996996 case bitc::CST_CODE_INTEGER: // INTEGER: [intval]
997997 if (!CurTy->isIntegerTy() || Record.empty())
998998 return Error("Invalid CST_INTEGER record");
999 V = ConstantInt::get(CurTy, DecodeSignRotatedValue(Record[0]));
999 V = ConstantInt::get(CurTy, decodeSignRotatedValue(Record[0]));
10001000 break;
10011001 case bitc::CST_CODE_WIDE_INTEGER: {// WIDE_INTEGER: [n x intval]
10021002 if (!CurTy->isIntegerTy() || Record.empty())
15231523 // Read a record.
15241524 switch (Stream.ReadRecord(Code, Record)) {
15251525 default: break; // Default behavior, ignore unknown content.
1526 case bitc::MODULE_CODE_VERSION: // VERSION: [version#]
1526 case bitc::MODULE_CODE_VERSION: { // VERSION: [version#]
15271527 if (Record.size() < 1)
15281528 return Error("Malformed MODULE_CODE_VERSION");
1529 // Only version #0 is supported so far.
1530 if (Record[0] != 0)
1531 return Error("Unknown bitstream version!");
1532 break;
1529 // Only version #0 and #1 are supported so far.
1530 unsigned module_version = Record[0];
1531 switch (module_version) {
1532 default: return Error("Unknown bitstream version!");
1533 case 0:
1534 UseRelativeIDs = false;
1535 break;
1536 case 1:
1537 UseRelativeIDs = true;
1538 break;
1539 }
1540 break;
1541 }
15331542 case bitc::MODULE_CODE_TRIPLE: { // TRIPLE: [strchr x N]
15341543 std::string S;
15351544 if (ConvertToString(Record, 0, S))
17961805 // Read a record.
17971806 switch (Stream.ReadRecord(Code, Record)) {
17981807 default: break; // Default behavior, ignore unknown content.
1799 case bitc::MODULE_CODE_VERSION: // VERSION: [version#]
1800 if (Record.size() < 1)
1801 return Error("Malformed MODULE_CODE_VERSION");
1802 // Only version #0 is supported so far.
1803 if (Record[0] != 0)
1804 return Error("Unknown bitstream version!");
1805 break;
18061808 case bitc::MODULE_CODE_TRIPLE: { // TRIPLE: [strchr x N]
18071809 std::string S;
18081810 if (ConvertToString(Record, 0, S))
20152017 unsigned OpNum = 0;
20162018 Value *LHS, *RHS;
20172019 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
2018 getValue(Record, OpNum, LHS->getType(), RHS) ||
2020 popValue(Record, OpNum, NextValueNo, LHS->getType(), RHS) ||
20192021 OpNum+1 > Record.size())
20202022 return Error("Invalid BINOP record");
20212023
21302132 unsigned OpNum = 0;
21312133 Value *TrueVal, *FalseVal, *Cond;
21322134 if (getValueTypePair(Record, OpNum, NextValueNo, TrueVal) ||
2133 getValue(Record, OpNum, TrueVal->getType(), FalseVal) ||
2134 getValue(Record, OpNum, Type::getInt1Ty(Context), Cond))
2135 popValue(Record, OpNum, NextValueNo, TrueVal->getType(), FalseVal) ||
2136 popValue(Record, OpNum, NextValueNo, Type::getInt1Ty(Context), Cond))
21352137 return Error("Invalid SELECT record");
21362138
21372139 I = SelectInst::Create(Cond, TrueVal, FalseVal);
21452147 unsigned OpNum = 0;
21462148 Value *TrueVal, *FalseVal, *Cond;
21472149 if (getValueTypePair(Record, OpNum, NextValueNo, TrueVal) ||
2148 getValue(Record, OpNum, TrueVal->getType(), FalseVal) ||
2150 popValue(Record, OpNum, NextValueNo, TrueVal->getType(), FalseVal) ||
21492151 getValueTypePair(Record, OpNum, NextValueNo, Cond))
21502152 return Error("Invalid SELECT record");
21512153
21702172 unsigned OpNum = 0;
21712173 Value *Vec, *Idx;
21722174 if (getValueTypePair(Record, OpNum, NextValueNo, Vec) ||
2173 getValue(Record, OpNum, Type::getInt32Ty(Context), Idx))
2175 popValue(Record, OpNum, NextValueNo, Type::getInt32Ty(Context), Idx))
21742176 return Error("Invalid EXTRACTELT record");
21752177 I = ExtractElementInst::Create(Vec, Idx);
21762178 InstructionList.push_back(I);
21812183 unsigned OpNum = 0;
21822184 Value *Vec, *Elt, *Idx;
21832185 if (getValueTypePair(Record, OpNum, NextValueNo, Vec) ||
2184 getValue(Record, OpNum,
2186 popValue(Record, OpNum, NextValueNo,
21852187 cast(Vec->getType())->getElementType(), Elt) ||
2186 getValue(Record, OpNum, Type::getInt32Ty(Context), Idx))
2188 popValue(Record, OpNum, NextValueNo, Type::getInt32Ty(Context), Idx))
21872189 return Error("Invalid INSERTELT record");
21882190 I = InsertElementInst::Create(Vec, Elt, Idx);
21892191 InstructionList.push_back(I);
21942196 unsigned OpNum = 0;
21952197 Value *Vec1, *Vec2, *Mask;
21962198 if (getValueTypePair(Record, OpNum, NextValueNo, Vec1) ||
2197 getValue(Record, OpNum, Vec1->getType(), Vec2))
2199 popValue(Record, OpNum, NextValueNo, Vec1->getType(), Vec2))
21982200 return Error("Invalid SHUFFLEVEC record");
21992201
22002202 if (getValueTypePair(Record, OpNum, NextValueNo, Mask))
22142216 unsigned OpNum = 0;
22152217 Value *LHS, *RHS;
22162218 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) ||
2217 getValue(Record, OpNum, LHS->getType(), RHS) ||
2219 popValue(Record, OpNum, NextValueNo, LHS->getType(), RHS) ||
22182220 OpNum+1 != Record.size())
22192221 return Error("Invalid CMP record");
22202222
22592261 }
22602262 else {
22612263 BasicBlock *FalseDest = getBasicBlock(Record[1]);
2262 Value *Cond = getFnValueByID(Record[2], Type::getInt1Ty(Context));
2264 Value *Cond = getValue(Record, 2, NextValueNo,
2265 Type::getInt1Ty(Context));
22632266 if (FalseDest == 0 || Cond == 0)
22642267 return Error("Invalid BR record");
22652268 I = BranchInst::Create(TrueDest, FalseDest, Cond);
22752278 Type *OpTy = getTypeByID(Record[1]);
22762279 unsigned ValueBitWidth = cast(OpTy)->getBitWidth();
22772280
2278 Value *Cond = getFnValueByID(Record[2], OpTy);
2281 Value *Cond = getValue(Record, 2, NextValueNo, OpTy);
22792282 BasicBlock *Default = getBasicBlock(Record[3]);
22802283 if (OpTy == 0 || Cond == 0 || Default == 0)
22812284 return Error("Invalid SWITCH record");
23302333 if (Record.size() < 3 || (Record.size() & 1) == 0)
23312334 return Error("Invalid SWITCH record");
23322335 Type *OpTy = getTypeByID(Record[0]);
2333 Value *Cond = getFnValueByID(Record[1], OpTy);
2336 Value *Cond = getValue(Record, 1, NextValueNo, OpTy);
23342337 BasicBlock *Default = getBasicBlock(Record[2]);
23352338 if (OpTy == 0 || Cond == 0 || Default == 0)
23362339 return Error("Invalid SWITCH record");
23542357 if (Record.size() < 2)
23552358 return Error("Invalid INDIRECTBR record");
23562359 Type *OpTy = getTypeByID(Record[0]);
2357 Value *Address = getFnValueByID(Record[1], OpTy);
2360 Value *Address = getValue(Record, 1, NextValueNo, OpTy);
23582361 if (OpTy == 0 || Address == 0)
23592362 return Error("Invalid INDIRECTBR record");
23602363 unsigned NumDests = Record.size()-2;
23962399
23972400 SmallVector Ops;
23982401 for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i, ++OpNum) {
2399 Ops.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i)));
2402 Ops.push_back(getValue(Record, OpNum, NextValueNo,
2403 FTy->getParamType(i)));
24002404 if (Ops.back() == 0) return Error("Invalid INVOKE record");
24012405 }
24022406
24432447 InstructionList.push_back(PN);
24442448
24452449 for (unsigned i = 0, e = Record.size()-1; i != e; i += 2) {
2446 Value *V = getFnValueByID(Record[1+i], Ty);
2450 Value *V;
2451 // With the new function encoding, it is possible that operands have
2452 // negative IDs (for forward references). Use a signed VBR
2453 // representation to keep the encoding small.
2454 if (UseRelativeIDs)
2455 V = getValueSigned(Record, 1+i, NextValueNo, Ty);
2456 else
2457 V = getValue(Record, 1+i, NextValueNo, Ty);
24472458 BasicBlock *BB = getBasicBlock(Record[2+i]);
24482459 if (!V || !BB) return Error("Invalid PHI record");
24492460 PN->addIncoming(V, BB);
25412552 unsigned OpNum = 0;
25422553 Value *Val, *Ptr;
25432554 if (getValueTypePair(Record, OpNum, NextValueNo, Ptr) ||
2544 getValue(Record, OpNum,
2555 popValue(Record, OpNum, NextValueNo,
25452556 cast(Ptr->getType())->getElementType(), Val) ||
25462557 OpNum+2 != Record.size())
25472558 return Error("Invalid STORE record");
25552566 unsigned OpNum = 0;
25562567 Value *Val, *Ptr;
25572568 if (getValueTypePair(Record, OpNum, NextValueNo, Ptr) ||
2558 getValue(Record, OpNum,
2569 popValue(Record, OpNum, NextValueNo,
25592570 cast(Ptr->getType())->getElementType(), Val) ||
25602571 OpNum+4 != Record.size())
25612572 return Error("Invalid STOREATOMIC record");
25782589 unsigned OpNum = 0;
25792590 Value *Ptr, *Cmp, *New;
25802591 if (getValueTypePair(Record, OpNum, NextValueNo, Ptr) ||
2581 getValue(Record, OpNum,
2592 popValue(Record, OpNum, NextValueNo,
25822593 cast(Ptr->getType())->getElementType(), Cmp) ||
2583 getValue(Record, OpNum,
2594 popValue(Record, OpNum, NextValueNo,
25842595 cast(Ptr->getType())->getElementType(), New) ||
25852596 OpNum+3 != Record.size())
25862597 return Error("Invalid CMPXCHG record");
25982609 unsigned OpNum = 0;
25992610 Value *Ptr, *Val;
26002611 if (getValueTypePair(Record, OpNum, NextValueNo, Ptr) ||
2601 getValue(Record, OpNum,
2612 popValue(Record, OpNum, NextValueNo,
26022613 cast(Ptr->getType())->getElementType(), Val) ||
26032614 OpNum+4 != Record.size())
26042615 return Error("Invalid ATOMICRMW record");
26522663 if (FTy->getParamType(i)->isLabelTy())
26532664 Args.push_back(getBasicBlock(Record[OpNum]));
26542665 else
2655 Args.push_back(getFnValueByID(Record[OpNum], FTy->getParamType(i)));
2666 Args.push_back(getValue(Record, OpNum, NextValueNo,
2667 FTy->getParamType(i)));
26562668 if (Args.back() == 0) return Error("Invalid CALL record");
26572669 }
26582670
26812693 if (Record.size() < 3)
26822694 return Error("Invalid VAARG record");
26832695 Type *OpTy = getTypeByID(Record[0]);
2684 Value *Op = getFnValueByID(Record[1], OpTy);
2696 Value *Op = getValue(Record, 1, NextValueNo, OpTy);
26852697 Type *ResTy = getTypeByID(Record[2]);
26862698 if (!OpTy || !Op || !ResTy)
26872699 return Error("Invalid VAARG record");
178178 typedef std::pair BlockAddrRefTy;
179179 DenseMap > BlockAddrFwdRefs;
180180
181 /// UseRelativeIDs - Indicates that we are using a new encoding for
182 /// instrunction operands where most operands in the current
183 /// FUNCTION_BLOCK are encoded relative to the instruction number,
184 /// for a more compact encoding. Some instruction operands are not
185 /// relative to the instruction ID: basic block numbers, and types.
186 /// Once the old style function blocks have been phased out, we would
187 /// not need this flag.
188 bool UseRelativeIDs;
189
181190 public:
182191 explicit BitcodeReader(MemoryBuffer *buffer, LLVMContext &C)
183192 : Context(C), TheModule(0), Buffer(buffer), BufferOwned(false),
184193 LazyStreamer(0), NextUnreadBit(0), SeenValueSymbolTable(false),
185194 ErrorString(0), ValueList(C), MDValueList(C),
186 SeenFirstFunctionBody(false) {
195 SeenFirstFunctionBody(false), UseRelativeIDs(false) {
187196 }
188197 explicit BitcodeReader(DataStreamer *streamer, LLVMContext &C)
189198 : Context(C), TheModule(0), Buffer(0), BufferOwned(false),
190199 LazyStreamer(streamer), NextUnreadBit(0), SeenValueSymbolTable(false),
191200 ErrorString(0), ValueList(C), MDValueList(C),
192 SeenFirstFunctionBody(false) {
201 SeenFirstFunctionBody(false), UseRelativeIDs(false) {
193202 }
194203 ~BitcodeReader() {
195204 FreeState();
222231 /// @brief Cheap mechanism to just extract module triple
223232 /// @returns true if an error occurred.
224233 bool ParseTriple(std::string &Triple);
234
235 static uint64_t decodeSignRotatedValue(uint64_t V);
236
225237 private:
226238 Type *getTypeByID(unsigned ID);
227239 Value *getFnValueByID(unsigned ID, Type *Ty) {
246258 unsigned InstNum, Value *&ResVal) {
247259 if (Slot == Record.size()) return true;
248260 unsigned ValNo = (unsigned)Record[Slot++];
261 // Adjust the ValNo, if it was encoded relative to the InstNum.
262 if (UseRelativeIDs)
263 ValNo = InstNum - ValNo;
249264 if (ValNo < InstNum) {
250265 // If this is not a forward reference, just return the value we already
251266 // have.
254269 } else if (Slot == Record.size()) {
255270 return true;
256271 }
257
272
258273 unsigned TypeNo = (unsigned)Record[Slot++];
259274 ResVal = getFnValueByID(ValNo, getTypeByID(TypeNo));
260275 return ResVal == 0;
261276 }
262 bool getValue(SmallVector &Record, unsigned &Slot,
263 Type *Ty, Value *&ResVal) {
264 if (Slot == Record.size()) return true;
265 unsigned ValNo = (unsigned)Record[Slot++];
266 ResVal = getFnValueByID(ValNo, Ty);
277
278 /// popValue - Read a value out of the specified record from slot 'Slot'.
279 /// Increment Slot past the number of slots used by the value in the record.
280 /// Return true if there is an error.
281 bool popValue(SmallVector &Record, unsigned &Slot,
282 unsigned InstNum, Type *Ty, Value *&ResVal) {
283 if (getValue(Record, Slot, InstNum, Ty, ResVal))
284 return true;
285 // All values currently take a single record slot.
286 ++Slot;
287 return false;
288 }
289
290 /// getValue -- Like popValue, but does not increment the Slot number.
291 bool getValue(SmallVector &Record, unsigned Slot,
292 unsigned InstNum, Type *Ty, Value *&ResVal) {
293 ResVal = getValue(Record, Slot, InstNum, Ty);
267294 return ResVal == 0;
268295 }
269296
270
297 /// getValue -- Version of getValue that returns ResVal directly,
298 /// or 0 if there is an error.
299 Value *getValue(SmallVector &Record, unsigned Slot,
300 unsigned InstNum, Type *Ty) {
301 if (Slot == Record.size()) return 0;
302 unsigned ValNo = (unsigned)Record[Slot];
303 // Adjust the ValNo, if it was encoded relative to the InstNum.
304 if (UseRelativeIDs)
305 ValNo = InstNum - ValNo;
306 return getFnValueByID(ValNo, Ty);
307 }
308
309 /// getValueSigned -- Like getValue, but decodes signed VBRs.
310 Value *getValueSigned(SmallVector &Record, unsigned Slot,
311 unsigned InstNum, Type *Ty) {
312 if (Slot == Record.size()) return 0;
313 unsigned ValNo = (unsigned)decodeSignRotatedValue(Record[Slot]);
314 // Adjust the ValNo, if it was encoded relative to the InstNum.
315 if (UseRelativeIDs)
316 ValNo = InstNum - ValNo;
317 return getFnValueByID(ValNo, Ty);
318 }
319
271320 bool ParseModule(bool Resume);
272321 bool ParseAttributeBlock();
273322 bool ParseTypeTable();
4040 /// These are manifest constants used by the bitcode writer. They do not need to
4141 /// be kept in sync with the reader, but need to be consistent within this file.
4242 enum {
43 CurVersion = 0,
44
4543 // VALUE_SYMTAB_BLOCK abbrev id's.
4644 VST_ENTRY_8_ABBREV = bitc::FIRST_APPLICATION_ABBREV,
4745 VST_ENTRY_7_ABBREV,
721719 Stream.ExitBlock();
722720 }
723721
722 static void emitSignedInt64(SmallVectorImpl &Vals, uint64_t V) {
723 if ((int64_t)V >= 0)
724 Vals.push_back(V << 1);
725 else
726 Vals.push_back((-V << 1) | 1);
727 }
728
724729 static void EmitAPInt(SmallVectorImpl &Vals,
725730 unsigned &Code, unsigned &AbbrevToUse, const APInt &Val,
726731 bool EmitSizeForWideNumbers = false
727732 ) {
728733 if (Val.getBitWidth() <= 64) {
729734 uint64_t V = Val.getSExtValue();
730 if ((int64_t)V >= 0)
731 Vals.push_back(V << 1);
732 else
733 Vals.push_back((-V << 1) | 1);
735 emitSignedInt64(Vals, V);
734736 Code = bitc::CST_CODE_INTEGER;
735737 AbbrevToUse = CONSTANTS_INTEGER_ABBREV;
736738 } else {
746748
747749 const uint64_t *RawWords = Val.getRawData();
748750 for (unsigned i = 0; i != NWords; ++i) {
749 int64_t V = RawWords[i];
750 if (V >= 0)
751 Vals.push_back(V << 1);
752 else
753 Vals.push_back((-V << 1) | 1);
751 emitSignedInt64(Vals, RawWords[i]);
754752 }
755753 Code = bitc::CST_CODE_WIDE_INTEGER;
756754 }
10241022 ///
10251023 /// This function adds V's value ID to Vals. If the value ID is higher than the
10261024 /// instruction ID, then it is a forward reference, and it also includes the
1027 /// type ID.
1025 /// type ID. The value ID that is written is encoded relative to the InstID.
10281026 static bool PushValueAndType(const Value *V, unsigned InstID,
10291027 SmallVector &Vals,
10301028 ValueEnumerator &VE) {
10311029 unsigned ValID = VE.getValueID(V);
1032 Vals.push_back(ValID);
1030 // Make encoding relative to the InstID.
1031 Vals.push_back(InstID - ValID);
10331032 if (ValID >= InstID) {
10341033 Vals.push_back(VE.getTypeID(V->getType()));
10351034 return true;
10361035 }
10371036 return false;
1037 }
1038
1039 /// pushValue - Like PushValueAndType, but where the type of the value is
1040 /// omitted (perhaps it was already encoded in an earlier operand).
1041 static void pushValue(const Value *V, unsigned InstID,
1042 SmallVector &Vals,
1043 ValueEnumerator &VE) {
1044 unsigned ValID = VE.getValueID(V);
1045 Vals.push_back(InstID - ValID);
1046 }
1047
1048 static void pushValue64(const Value *V, unsigned InstID,
1049 SmallVector &Vals,
1050 ValueEnumerator &VE) {
1051 uint64_t ValID = VE.getValueID(V);
1052 Vals.push_back(InstID - ValID);
1053 }
1054
1055 static void pushValueSigned(const Value *V, unsigned InstID,
1056 SmallVector &Vals,
1057 ValueEnumerator &VE) {
1058 unsigned ValID = VE.getValueID(V);
1059 int64_t diff = ((int32_t)InstID - (int32_t)ValID);
1060 emitSignedInt64(Vals, diff);
10381061 }
10391062
10401063 /// WriteInstruction - Emit an instruction to the specified stream.
10571080 Code = bitc::FUNC_CODE_INST_BINOP;
10581081 if (!PushValueAndType(I.getOperand(0), InstID, Vals, VE))
10591082 AbbrevToUse = FUNCTION_INST_BINOP_ABBREV;
1060 Vals.push_back(VE.getValueID(I.getOperand(1)));
1083 pushValue(I.getOperand(1), InstID, Vals, VE);
10611084 Vals.push_back(GetEncodedBinaryOpcode(I.getOpcode()));
10621085 uint64_t Flags = GetOptimizationFlags(&I);
10631086 if (Flags != 0) {
10951118 case Instruction::Select:
10961119 Code = bitc::FUNC_CODE_INST_VSELECT;
10971120 PushValueAndType(I.getOperand(1), InstID, Vals, VE);
1098 Vals.push_back(VE.getValueID(I.getOperand(2)));
1121 pushValue(I.getOperand(2), InstID, Vals, VE);
10991122 PushValueAndType(I.getOperand(0), InstID, Vals, VE);
11001123 break;
11011124 case Instruction::ExtractElement:
11021125 Code = bitc::FUNC_CODE_INST_EXTRACTELT;
11031126 PushValueAndType(I.getOperand(0), InstID, Vals, VE);
1104 Vals.push_back(VE.getValueID(I.getOperand(1)));
1127 pushValue(I.getOperand(1), InstID, Vals, VE);
11051128 break;
11061129 case Instruction::InsertElement:
11071130 Code = bitc::FUNC_CODE_INST_INSERTELT;
11081131 PushValueAndType(I.getOperand(0), InstID, Vals, VE);
1109 Vals.push_back(VE.getValueID(I.getOperand(1)));
1110 Vals.push_back(VE.getValueID(I.getOperand(2)));
1132 pushValue(I.getOperand(1), InstID, Vals, VE);
1133 pushValue(I.getOperand(2), InstID, Vals, VE);
11111134 break;
11121135 case Instruction::ShuffleVector:
11131136 Code = bitc::FUNC_CODE_INST_SHUFFLEVEC;
11141137 PushValueAndType(I.getOperand(0), InstID, Vals, VE);
1115 Vals.push_back(VE.getValueID(I.getOperand(1)));
1116 Vals.push_back(VE.getValueID(I.getOperand(2)));
1138 pushValue(I.getOperand(1), InstID, Vals, VE);
1139 pushValue(I.getOperand(2), InstID, Vals, VE);
11171140 break;
11181141 case Instruction::ICmp:
11191142 case Instruction::FCmp:
11201143 // compare returning Int1Ty or vector of Int1Ty
11211144 Code = bitc::FUNC_CODE_INST_CMP2;
11221145 PushValueAndType(I.getOperand(0), InstID, Vals, VE);
1123 Vals.push_back(VE.getValueID(I.getOperand(1)));
1146 pushValue(I.getOperand(1), InstID, Vals, VE);
11241147 Vals.push_back(cast(I).getPredicate());
11251148 break;
11261149
11461169 Vals.push_back(VE.getValueID(II.getSuccessor(0)));
11471170 if (II.isConditional()) {
11481171 Vals.push_back(VE.getValueID(II.getSuccessor(1)));
1149 Vals.push_back(VE.getValueID(II.getCondition()));
1172 pushValue(II.getCondition(), InstID, Vals, VE);
11501173 }
11511174 }
11521175 break;
11631186 Vals64.push_back(SwitchRecordHeader);
11641187
11651188 Vals64.push_back(VE.getTypeID(SI.getCondition()->getType()));
1166 Vals64.push_back(VE.getValueID(SI.getCondition()));
1189 pushValue64(SI.getCondition(), InstID, Vals64, VE);
11671190 Vals64.push_back(VE.getValueID(SI.getDefaultDest()));
11681191 Vals64.push_back(SI.getNumCases());
11691192 for (SwitchInst::CaseIt i = SI.case_begin(), e = SI.case_end();
12141237 case Instruction::IndirectBr:
12151238 Code = bitc::FUNC_CODE_INST_INDIRECTBR;
12161239 Vals.push_back(VE.getTypeID(I.getOperand(0)->getType()));
1217 for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i)
1240 // Encode the address operand as relative, but not the basic blocks.
1241 pushValue(I.getOperand(0), InstID, Vals, VE);
1242 for (unsigned i = 1, e = I.getNumOperands(); i != e; ++i)
12181243 Vals.push_back(VE.getValueID(I.getOperand(i)));
12191244 break;
12201245
12331258
12341259 // Emit value #'s for the fixed parameters.
12351260 for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
1236 Vals.push_back(VE.getValueID(I.getOperand(i))); // fixed param.
1261 pushValue(I.getOperand(i), InstID, Vals, VE); // fixed param.
12371262
12381263 // Emit type/value pairs for varargs params.
12391264 if (FTy->isVarArg()) {
12551280 case Instruction::PHI: {
12561281 const PHINode &PN = cast(I);
12571282 Code = bitc::FUNC_CODE_INST_PHI;
1258 Vals.push_back(VE.getTypeID(PN.getType()));
1283 // With the newer instruction encoding, forward references could give
1284 // negative valued IDs. This is most common for PHIs, so we use
1285 // signed VBRs.
1286 SmallVector Vals64;
1287 Vals64.push_back(VE.getTypeID(PN.getType()));
12591288 for (unsigned i = 0, e = PN.getNumIncomingValues(); i != e; ++i) {
1260 Vals.push_back(VE.getValueID(PN.getIncomingValue(i)));
1261 Vals.push_back(VE.getValueID(PN.getIncomingBlock(i)));
1262 }
1263 break;
1289 pushValueSigned(PN.getIncomingValue(i), InstID, Vals64, VE);
1290 Vals64.push_back(VE.getValueID(PN.getIncomingBlock(i)));
1291 }
1292 // Emit a Vals64 vector and exit.
1293 Stream.EmitRecord(Code, Vals64, AbbrevToUse);
1294 Vals64.clear();
1295 return;
12641296 }
12651297
12661298 case Instruction::LandingPad: {
13101342 else
13111343 Code = bitc::FUNC_CODE_INST_STORE;
13121344 PushValueAndType(I.getOperand(1), InstID, Vals, VE); // ptrty + ptr
1313 Vals.push_back(VE.getValueID(I.getOperand(0))); // val.
1345 pushValue(I.getOperand(0), InstID, Vals, VE); // val.
13141346 Vals.push_back(Log2_32(cast(I).getAlignment())+1);
13151347 Vals.push_back(cast(I).isVolatile());
13161348 if (cast(I).isAtomic()) {
13211353 case Instruction::AtomicCmpXchg:
13221354 Code = bitc::FUNC_CODE_INST_CMPXCHG;
13231355 PushValueAndType(I.getOperand(0), InstID, Vals, VE); // ptrty + ptr
1324 Vals.push_back(VE.getValueID(I.getOperand(1))); // cmp.
1325 Vals.push_back(VE.getValueID(I.getOperand(2))); // newval.
1356 pushValue(I.getOperand(1), InstID, Vals, VE); // cmp.
1357 pushValue(I.getOperand(2), InstID, Vals, VE); // newval.
13261358 Vals.push_back(cast(I).isVolatile());
13271359 Vals.push_back(GetEncodedOrdering(
13281360 cast(I).getOrdering()));
13321364 case Instruction::AtomicRMW:
13331365 Code = bitc::FUNC_CODE_INST_ATOMICRMW;
13341366 PushValueAndType(I.getOperand(0), InstID, Vals, VE); // ptrty + ptr
1335 Vals.push_back(VE.getValueID(I.getOperand(1))); // val.
1367 pushValue(I.getOperand(1), InstID, Vals, VE); // val.
13361368 Vals.push_back(GetEncodedRMWOperation(
13371369 cast(I).getOperation()));
13381370 Vals.push_back(cast(I).isVolatile());
13571389 PushValueAndType(CI.getCalledValue(), InstID, Vals, VE); // Callee
13581390
13591391 // Emit value #'s for the fixed parameters.
1360 for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i)
1361 Vals.push_back(VE.getValueID(CI.getArgOperand(i))); // fixed param.
1392 for (unsigned i = 0, e = FTy->getNumParams(); i != e; ++i) {
1393 // Check for labels (can happen with asm labels).
1394 if (FTy->getParamType(i)->isLabelTy())
1395 Vals.push_back(VE.getValueID(CI.getArgOperand(i)));
1396 else
1397 pushValue(CI.getArgOperand(i), InstID, Vals, VE); // fixed param.
1398 }
13621399
13631400 // Emit type/value pairs for varargs params.
13641401 if (FTy->isVarArg()) {
13711408 case Instruction::VAArg:
13721409 Code = bitc::FUNC_CODE_INST_VAARG;
13731410 Vals.push_back(VE.getTypeID(I.getOperand(0)->getType())); // valistty
1374 Vals.push_back(VE.getValueID(I.getOperand(0))); // valist.
1411 pushValue(I.getOperand(0), InstID, Vals, VE); // valist.
13751412 Vals.push_back(VE.getTypeID(I.getType())); // restype.
13761413 break;
13771414 }
15131550 // Emit blockinfo, which defines the standard abbreviations etc.
15141551 static void WriteBlockInfo(const ValueEnumerator &VE, BitstreamWriter &Stream) {
15151552 // We only want to emit block info records for blocks that have multiple
1516 // instances: CONSTANTS_BLOCK, FUNCTION_BLOCK and VALUE_SYMTAB_BLOCK. Other
1517 // blocks can defined their abbrevs inline.
1553 // instances: CONSTANTS_BLOCK, FUNCTION_BLOCK and VALUE_SYMTAB_BLOCK.
1554 // Other blocks can defined their abbrevs inline.
15181555 Stream.EnterBlockInfoBlock(2);
15191556
15201557 { // 8-bit fixed-width VST_ENTRY/VST_BBENTRY strings.
17721809 static void WriteModule(const Module *M, BitstreamWriter &Stream) {
17731810 Stream.EnterSubblock(bitc::MODULE_BLOCK_ID, 3);
17741811
1775 // Emit the version number if it is non-zero.
1776 if (CurVersion) {
1777 SmallVector Vals;
1778 Vals.push_back(CurVersion);
1779 Stream.EmitRecord(bitc::MODULE_CODE_VERSION, Vals);
1780 }
1812 SmallVector Vals;
1813 unsigned CurVersion = 1;
1814 Vals.push_back(CurVersion);
1815 Stream.EmitRecord(bitc::MODULE_CODE_VERSION, Vals);
17811816
17821817 // Analyze the module, enumerating globals, functions, etc.
17831818 ValueEnumerator VE(M);
0 ; Basic sanity test to check that instruction operands are encoded with
1 ; relative IDs.
2 ; RUN: llvm-as < %s | llvm-bcanalyzer -dump | FileCheck %s
3
4 ; CHECK: FUNCTION_BLOCK
5 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
6 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
7 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
8 ; CHECK: INST_RET {{.*}}op0=1
9 define i32 @test_int_binops(i32 %a) nounwind {
10 entry:
11 %0 = add i32 %a, %a
12 %1 = sub i32 %0, %0
13 %2 = mul i32 %1, %1
14 ret i32 %2
15 }
16
17
18 ; CHECK: FUNCTION_BLOCK
19 ; CHECK: INST_CAST {{.*}}op0=1
20 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
21 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
22 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
23 ; CHECK: INST_BINOP {{.*}}op0=1 op1=1
24 ; CHECK: INST_RET {{.*}}op0=1
25 define double @test_float_binops(i32 %a) nounwind {
26 %1 = sitofp i32 %a to double
27 %2 = fadd double %1, %1
28 %3 = fsub double %2, %2
29 %4 = fmul double %3, %3
30 %5 = fdiv double %4, %4
31 ret double %5
32 }
33
34
35 ; CHECK: FUNCTION_BLOCK
36 ; skip checking operands of INST_INBOUNDS_GEP since that depends on ordering
37 ; between literals and the formal parameters.
38 ; CHECK: INST_INBOUNDS_GEP {{.*}}
39 ; CHECK: INST_LOAD {{.*}}op0=1 {{.*}}
40 ; CHECK: INST_CMP2 op0=1 {{.*}}
41 ; CHECK: INST_RET {{.*}}op0=1
42 define i1 @test_load(i32 %a, {i32, i32}* %ptr) nounwind {
43 entry:
44 %0 = getelementptr inbounds {i32, i32}* %ptr, i32 %a, i32 0
45 %1 = load i32* %0
46 %2 = icmp eq i32 %1, %a
47 ret i1 %2
48 }