llvm.org GIT mirror llvm / d9a2679
Merging r258901: ------------------------------------------------------------------------ r258901 | Matthew.Arsenault | 2016-01-26 18:17:49 -0800 (Tue, 26 Jan 2016) | 17 lines AMDGPU: Fix default device handling When no device name is specified, default to kaveri for HSA since SI is not supported and it woud fail. Default to "tahiti" instead of "SI" since these are effectively the same, and tahiti is an actual device. Move default device handling to the TargetMachine rather than the AMDGPUSubtarget. The module ISA version is computed from the device name provided with the target machine, so the attributes printed by the AsmPrinter were inconsistent with those computed in the subtarget. Also remove DevName field from subtarget since it's redundant with getCPU() in the superclass. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_38@271588 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 3 years ago
4 changed file(s) with 28 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
4848 FullFS += "+flat-for-global,";
4949 FullFS += FS;
5050
51 if (GPU == "" && TT.getArch() == Triple::amdgcn)
52 GPU = "SI";
53
5451 ParseSubtargetFeatures(GPU, FullFS);
5552
5653 // FIXME: I don't think think Evergreen has any useful support for
6562
6663 AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
6764 TargetMachine &TM)
68 : AMDGPUGenSubtargetInfo(TT, GPU, FS), DevName(GPU),
65 : AMDGPUGenSubtargetInfo(TT, GPU, FS),
6966 DumpCode(false), R600ALUInst(false), HasVertexCache(false),
7067 TexVTXClauseSize(0), Gen(AMDGPUSubtarget::R600), FP64(false),
7168 FP64Denormals(false), FP32Denormals(false), FastFMAF32(false),
5757 };
5858
5959 private:
60 std::string DevName;
6160 bool DumpCode;
6261 bool R600ALUInst;
6362 bool HasVertexCache;
268267 return false;
269268 }
270269
271 StringRef getDeviceName() const {
272 return DevName;
273 }
274
275270 bool enableHugeScratchBuffer() const {
276271 return EnableHugeScratchBuffer;
277272 }
8787 return Ret;
8888 }
8989
90 LLVM_READNONE
91 static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
92 if (!GPU.empty())
93 return GPU;
94
95 // HSA only supports CI+, so change the default GPU to a CI for HSA.
96 if (TT.getArch() == Triple::amdgcn)
97 return (TT.getOS() == Triple::AMDHSA) ? "kaveri" : "tahiti";
98
99 return "";
100 }
101
90102 AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
91103 StringRef CPU, StringRef FS,
92104 TargetOptions Options, Reloc::Model RM,
93105 CodeModel::Model CM,
94106 CodeGenOpt::Level OptLevel)
95 : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, RM, CM,
107 : LLVMTargetMachine(T, computeDataLayout(TT), TT,
108 getGPUOrDefault(TT, CPU), FS, Options, RM, CM,
96109 OptLevel),
97 TLOF(createTLOF(getTargetTriple())), Subtarget(TT, CPU, FS, *this),
110 TLOF(createTLOF(getTargetTriple())),
111 Subtarget(TT, getTargetCPU(), FS, *this),
98112 IntrinsicInfo() {
99113 setRequiresStructuredCFG(true);
100114 initAsmInfo();
0 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
1
2 ; Make sure that with an HSA triple, we don't default to an
3 ; unsupported device.
4
5 ; CHECK: .hsa_code_object_isa 7,0,0,"AMD","AMDGPU"
6 define void @test_kernel(float addrspace(1)* %out0, double addrspace(1)* %out1) nounwind {
7 store float 0.0, float addrspace(1)* %out0
8 ret void
9 }
10