llvm.org GIT mirror llvm / d98d620
Optimize conditional branches in X86FastISel. This replaces sequences like this: sete %al testb %al, %al jne LBB11_1 with this: je LBB11_1 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56969 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 12 years ago
3 changed file(s) with 165 addition(s) and 26 deletion(s). Raw diff Collapse all Expand all
237237 /// from a specified index of a superregister.
238238 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
239239
240 /// FastEmitBranch - Emit an unconditional branch to the given block,
241 /// unless it is the immediate (fall-through) successor, and update
242 /// the CFG.
243 void FastEmitBranch(MachineBasicBlock *MBB);
244
240245 void UpdateValueMap(Value* I, unsigned Reg);
241246
242247 unsigned createResultReg(const TargetRegisterClass *RC);
460460 return SelectOperator(I, I->getOpcode());
461461 }
462462
463 /// FastEmitBranch - Emit an unconditional branch to the given block,
464 /// unless it is the immediate (fall-through) successor, and update
465 /// the CFG.
466 void
467 FastISel::FastEmitBranch(MachineBasicBlock *MSucc) {
468 MachineFunction::iterator NextMBB =
469 next(MachineFunction::iterator(MBB));
470
471 if (MBB->isLayoutSuccessor(MSucc)) {
472 // The unconditional fall-through case, which needs no instructions.
473 } else {
474 // The unconditional branch case.
475 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector());
476 }
477 MBB->addSuccessor(MSucc);
478 }
479
463480 bool
464481 FastISel::SelectOperator(User *I, unsigned Opcode) {
465482 switch (Opcode) {
507524 BranchInst *BI = cast(I);
508525
509526 if (BI->isUnconditional()) {
510 MachineFunction::iterator NextMBB =
511 next(MachineFunction::iterator(MBB));
512527 BasicBlock *LLVMSucc = BI->getSuccessor(0);
513528 MachineBasicBlock *MSucc = MBBMap[LLVMSucc];
514
515 if (NextMBB != MF.end() && MSucc == NextMBB) {
516 // The unconditional fall-through case, which needs no instructions.
517 } else {
518 // The unconditional branch case.
519 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector());
520 }
521 MBB->addSuccessor(MSucc);
529 FastEmitBranch(MSucc);
522530 return true;
523531 }
524532
8989 bool X86SelectSelect(Instruction *I);
9090
9191 bool X86SelectTrunc(Instruction *I);
92
93 unsigned X86ChooseCmpOpcode(MVT VT);
9294
9395 bool X86SelectFPExt(Instruction *I);
9496 bool X86SelectFPTrunc(Instruction *I);
506508 return false;
507509 }
508510
511 unsigned X86FastISel::X86ChooseCmpOpcode(MVT VT) {
512 switch (VT.getSimpleVT()) {
513 case MVT::i8: return X86::CMP8rr;
514 case MVT::i16: return X86::CMP16rr;
515 case MVT::i32: return X86::CMP32rr;
516 case MVT::i64: return X86::CMP64rr;
517 case MVT::f32: return X86::UCOMISSrr;
518 case MVT::f64: return X86::UCOMISDrr;
519 default: break;
520 }
521 return 0;
522 }
523
509524 bool X86FastISel::X86SelectCmp(Instruction *I) {
510525 CmpInst *CI = cast(I);
511526
518533 unsigned Op1Reg = getRegForValue(CI->getOperand(1));
519534 if (Op1Reg == 0) return false;
520535
521 unsigned Opc;
522 switch (VT.getSimpleVT()) {
523 case MVT::i8: Opc = X86::CMP8rr; break;
524 case MVT::i16: Opc = X86::CMP16rr; break;
525 case MVT::i32: Opc = X86::CMP32rr; break;
526 case MVT::i64: Opc = X86::CMP64rr; break;
527 case MVT::f32: Opc = X86::UCOMISSrr; break;
528 case MVT::f64: Opc = X86::UCOMISDrr; break;
529 default: return false;
530 }
536 unsigned Opc = X86ChooseCmpOpcode(VT);
531537
532538 unsigned ResultReg = createResultReg(&X86::GR8RegClass);
533539 switch (CI->getPredicate()) {
660666 }
661667
662668 bool X86FastISel::X86SelectBranch(Instruction *I) {
669 // Unconditional branches are selected by tablegen-generated code.
670 // Handle a conditional branch.
663671 BranchInst *BI = cast(I);
664 // Unconditional branches are selected by tablegen-generated code.
672 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
673 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
674
675 // Fold the common case of a conditional branch with a comparison.
676 if (CmpInst *CI = dyn_cast(BI->getCondition())) {
677 if (CI->hasOneUse()) {
678 MVT VT = TLI.getValueType(CI->getOperand(0)->getType());
679 unsigned Opc = X86ChooseCmpOpcode(VT);
680 if (Opc == 0) return false;
681
682 // Try to take advantage of fallthrough opportunities.
683 CmpInst::Predicate Predicate = CI->getPredicate();
684 if (MBB->isLayoutSuccessor(TrueMBB)) {
685 std::swap(TrueMBB, FalseMBB);
686 Predicate = CmpInst::getInversePredicate(Predicate);
687 }
688
689 unsigned Op0Reg = getRegForValue(CI->getOperand(0));
690 if (Op0Reg == 0) return false;
691 unsigned Op1Reg = getRegForValue(CI->getOperand(1));
692 if (Op1Reg == 0) return false;
693
694 switch (Predicate) {
695 case CmpInst::FCMP_OGT:
696 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
697 BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB);
698 break;
699 case CmpInst::FCMP_OGE:
700 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
701 BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB);
702 break;
703 case CmpInst::FCMP_OLT:
704 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
705 BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB);
706 break;
707 case CmpInst::FCMP_OLE:
708 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
709 BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB);
710 break;
711 case CmpInst::FCMP_ONE:
712 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
713 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
714 break;
715 case CmpInst::FCMP_ORD:
716 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
717 BuildMI(MBB, TII.get(X86::JNP)).addMBB(TrueMBB);
718 break;
719 case CmpInst::FCMP_UNO:
720 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
721 BuildMI(MBB, TII.get(X86::JP)).addMBB(TrueMBB);
722 break;
723 case CmpInst::FCMP_UEQ:
724 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
725 BuildMI(MBB, TII.get(X86::JE)).addMBB(TrueMBB);
726 break;
727 case CmpInst::FCMP_UGT:
728 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
729 BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB);
730 break;
731 case CmpInst::FCMP_UGE:
732 BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
733 BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB);
734 break;
735 case CmpInst::FCMP_ULT:
736 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
737 BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB);
738 break;
739 case CmpInst::FCMP_ULE:
740 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
741 BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB);
742 break;
743 case CmpInst::ICMP_EQ:
744 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
745 BuildMI(MBB, TII.get(X86::JE)).addMBB(TrueMBB);
746 break;
747 case CmpInst::ICMP_NE:
748 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
749 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
750 break;
751 case CmpInst::ICMP_UGT:
752 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
753 BuildMI(MBB, TII.get(X86::JA)).addMBB(TrueMBB);
754 break;
755 case CmpInst::ICMP_UGE:
756 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
757 BuildMI(MBB, TII.get(X86::JAE)).addMBB(TrueMBB);
758 break;
759 case CmpInst::ICMP_ULT:
760 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
761 BuildMI(MBB, TII.get(X86::JB)).addMBB(TrueMBB);
762 break;
763 case CmpInst::ICMP_ULE:
764 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
765 BuildMI(MBB, TII.get(X86::JBE)).addMBB(TrueMBB);
766 break;
767 case CmpInst::ICMP_SGT:
768 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
769 BuildMI(MBB, TII.get(X86::JG)).addMBB(TrueMBB);
770 break;
771 case CmpInst::ICMP_SGE:
772 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
773 BuildMI(MBB, TII.get(X86::JGE)).addMBB(TrueMBB);
774 break;
775 case CmpInst::ICMP_SLT:
776 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
777 BuildMI(MBB, TII.get(X86::JL)).addMBB(TrueMBB);
778 break;
779 case CmpInst::ICMP_SLE:
780 BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
781 BuildMI(MBB, TII.get(X86::JLE)).addMBB(TrueMBB);
782 break;
783 default:
784 return false;
785 }
786 MBB->addSuccessor(TrueMBB);
787 FastEmitBranch(FalseMBB);
788 return true;
789 }
790 }
791
792 // Otherwise do a clumsy setcc and re-test it.
665793 unsigned OpReg = getRegForValue(BI->getCondition());
666794 if (OpReg == 0) return false;
667 MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
668 MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
669795
670796 BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
797
671798 BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
672 BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
673
674799 MBB->addSuccessor(TrueMBB);
675 MBB->addSuccessor(FalseMBB);
800
801 FastEmitBranch(FalseMBB);
676802
677803 return true;
678804 }