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[AArch64][GlobalISel] Select immediate forms of cmp instructions. A simple re-use of the immediate operand matcher and renderer functions. rdar://43795178 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@362896 91177308-0d34-0410-b5e6-96231b3b80d8 Amara Emerson 4 months ago
3 changed file(s) with 92 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
18571857 return false;
18581858 }
18591859
1860 // Try to match immediate forms.
1861 auto ImmFns = selectArithImmed(I.getOperand(3));
1862 if (ImmFns)
1863 CmpOpc = CmpOpc == AArch64::SUBSWrr ? AArch64::SUBSWri : AArch64::SUBSXri;
1864
18601865 // CSINC increments the result by one when the condition code is false.
18611866 // Therefore, we have to invert the predicate to get an increment by 1 when
18621867 // the predicate is true.
18641869 changeICMPPredToAArch64CC(CmpInst::getInversePredicate(
18651870 (CmpInst::Predicate)I.getOperand(1).getPredicate()));
18661871
1867 MachineInstr &CmpMI = *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
1868 .addDef(ZReg)
1869 .addUse(I.getOperand(2).getReg())
1870 .addUse(I.getOperand(3).getReg());
1872 auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
1873 .addDef(ZReg)
1874 .addUse(I.getOperand(2).getReg());
1875
1876 // If we matched a valid constant immediate, add those operands.
1877 if (ImmFns) {
1878 for (auto &RenderFn : *ImmFns)
1879 RenderFn(CmpMI);
1880 } else {
1881 CmpMI.addUse(I.getOperand(3).getReg());
1882 }
18711883
18721884 MachineInstr &CSetMI =
18731885 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::CSINCWr))
18761888 .addUse(AArch64::WZR)
18771889 .addImm(invCC);
18781890
1879 constrainSelectedInstRegOperands(CmpMI, TII, TRI, RBI);
1891 constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
18801892 constrainSelectedInstRegOperands(CSetMI, TII, TRI, RBI);
18811893
18821894 I.eraseFromParent();
6060
6161 ; CHECK-LABEL: name: using_icmp
6262 ; CHECK: liveins: $s0, $w0
63 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
63 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
6464 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s0
65 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 0
66 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
67 ; CHECK: $wzr = SUBSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
65 ; CHECK: [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
66 ; CHECK: $wzr = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
6867 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
6968 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[CSINCWr]]
7069 ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY [[COPY2]]
0 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
1 # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
2 ---
3 name: cmp_imm_32
4 legalized: true
5 regBankSelected: true
6 tracksRegLiveness: true
7 body: |
8 bb.1:
9 liveins: $w0
10
11 ; CHECK-LABEL: name: cmp_imm_32
12 ; CHECK: liveins: $w0
13 ; CHECK: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0
14 ; CHECK: $wzr = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv
15 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
16 ; CHECK: $w0 = COPY [[CSINCWr]]
17 ; CHECK: RET_ReallyLR implicit $w0
18 %0:gpr(s32) = COPY $w0
19 %1:gpr(s32) = G_CONSTANT i32 42
20 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %1
21 $w0 = COPY %5(s32)
22 RET_ReallyLR implicit $w0
23
24 ...
25 ---
26 name: cmp_imm_64
27 legalized: true
28 regBankSelected: true
29 tracksRegLiveness: true
30 body: |
31 bb.1:
32 liveins: $x0
33
34 ; CHECK-LABEL: name: cmp_imm_64
35 ; CHECK: liveins: $x0
36 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
37 ; CHECK: $xzr = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv
38 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
39 ; CHECK: $w0 = COPY [[CSINCWr]]
40 ; CHECK: RET_ReallyLR implicit $w0
41 %0:gpr(s64) = COPY $x0
42 %1:gpr(s64) = G_CONSTANT i64 42
43 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
44 $w0 = COPY %5(s32)
45 RET_ReallyLR implicit $w0
46
47 ...
48 ---
49 name: cmp_imm_out_of_range
50 legalized: true
51 regBankSelected: true
52 tracksRegLiveness: true
53 body: |
54 bb.1:
55 liveins: $x0
56
57 ; CHECK-LABEL: name: cmp_imm_out_of_range
58 ; CHECK: liveins: $x0
59 ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
60 ; CHECK: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm 13132
61 ; CHECK: $xzr = SUBSXrr [[COPY]], [[MOVi64imm]], implicit-def $nzcv
62 ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
63 ; CHECK: $w0 = COPY [[CSINCWr]]
64 ; CHECK: RET_ReallyLR implicit $w0
65 %0:gpr(s64) = COPY $x0
66 %1:gpr(s64) = G_CONSTANT i64 13132
67 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1
68 $w0 = COPY %5(s32)
69 RET_ReallyLR implicit $w0
70
71 ...