llvm.org GIT mirror llvm / d94b6a1
Move some more functionality from MRegisterInfo to TargetInstrInfo. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45603 91177308-0d34-0410-b5e6-96231b3b80d8 Owen Anderson 12 years ago
13 changed file(s) with 130 addition(s) and 121 deletion(s). Raw diff Collapse all Expand all
4545 (void) llvm::createAliasDebugger();
4646 (void) llvm::createAndersensPass();
4747 (void) llvm::createArgumentPromotionPass();
48 (void) llvm::createAutoVectorizePass();
4849 (void) llvm::createBasicAliasAnalysisPass();
4950 (void) llvm::createBasicVNPass();
5051 (void) llvm::createBlockPlacementPass();
2424 namespace llvm {
2525
2626 class BitVector;
27 class CalleeSavedInfo;
2827 class MachineFunction;
2928 class MachineInstr;
3029 class MachineLocation;
469468 // immediates and memory. FIXME: Move these to TargetInstrInfo.h.
470469 //
471470
472 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
473 /// saved registers and returns true if it isn't possible / profitable to do
474 /// so by issuing a series of store instructions via
475 /// storeRegToStackSlot(). Returns false otherwise.
476 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
477 MachineBasicBlock::iterator MI,
478 const std::vector &CSI) const {
479 return false;
480 }
481
482 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
483 /// saved registers and returns true if it isn't possible / profitable to do
484 /// so by issuing a series of load instructions via loadRegToStackSlot().
485 /// Returns false otherwise.
486 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
487 MachineBasicBlock::iterator MI,
488 const std::vector &CSI) const {
489 return false;
490 }
491
492471 /// getCrossCopyRegClass - Returns a legal register class to copy a register
493472 /// in the specified class to or from. Returns NULL if it is possible to copy
494473 /// between a two registers of the specified class.
2525 class TargetMachine;
2626 class TargetRegisterClass;
2727 class LiveVariables;
28 class CalleeSavedInfo;
2829
2930 template class SmallVectorImpl;
3031
496497 assert(0 && "Target didn't implement TargetInstrInfo::loadRegFromAddr!");
497498 }
498499
500 /// spillCalleeSavedRegisters - Issues instruction(s) to spill all callee
501 /// saved registers and returns true if it isn't possible / profitable to do
502 /// so by issuing a series of store instructions via
503 /// storeRegToStackSlot(). Returns false otherwise.
504 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
505 MachineBasicBlock::iterator MI,
506 const std::vector &CSI) const {
507 return false;
508 }
509
510 /// restoreCalleeSavedRegisters - Issues instruction(s) to restore all callee
511 /// saved registers and returns true if it isn't possible / profitable to do
512 /// so by issuing a series of load instructions via loadRegToStackSlot().
513 /// Returns false otherwise.
514 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator MI,
516 const std::vector &CSI) const {
517 return false;
518 }
519
499520 /// BlockHasNoFallThrough - Return true if the specified block does not
500521 /// fall-through into its successor block. This is primarily used when a
501522 /// branch is unanalyzable. It is useful for things like unconditional
331331
332332 //===----------------------------------------------------------------------===//
333333 //
334 // AutoVectorize - This pass performs vectorization of straight-line code
335 //
336 FunctionPass *createAutoVectorizePass();
337
338 //===----------------------------------------------------------------------===//
339 //
334340 // GVN - This pass performs global value numbering and redundant load
335341 // elimination cotemporaneously.
336342 //
1717 #include "ARMMachineFunctionInfo.h"
1818 #include "llvm/ADT/STLExtras.h"
1919 #include "llvm/CodeGen/LiveVariables.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
2021 #include "llvm/CodeGen/MachineInstrBuilder.h"
2122 #include "llvm/CodeGen/MachineJumpTableInfo.h"
2223 #include "llvm/Target/TargetAsmInfo.h"
597598 return;
598599 }
599600
601 bool ARMInstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
602 MachineBasicBlock::iterator MI,
603 const std::vector &CSI) const {
604 MachineFunction &MF = *MBB.getParent();
605 ARMFunctionInfo *AFI = MF.getInfo();
606 if (!AFI->isThumbFunction() || CSI.empty())
607 return false;
608
609 MachineInstrBuilder MIB = BuildMI(MBB, MI, get(ARM::tPUSH));
610 for (unsigned i = CSI.size(); i != 0; --i) {
611 unsigned Reg = CSI[i-1].getReg();
612 // Add the callee-saved register as live-in. It's killed at the spill.
613 MBB.addLiveIn(Reg);
614 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
615 }
616 return true;
617 }
618
619 bool ARMInstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
620 MachineBasicBlock::iterator MI,
621 const std::vector &CSI) const {
622 MachineFunction &MF = *MBB.getParent();
623 ARMFunctionInfo *AFI = MF.getInfo();
624 if (!AFI->isThumbFunction() || CSI.empty())
625 return false;
626
627 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
628 MachineInstr *PopMI = new MachineInstr(get(ARM::tPOP));
629 MBB.insert(MI, PopMI);
630 for (unsigned i = CSI.size(); i != 0; --i) {
631 unsigned Reg = CSI[i-1].getReg();
632 if (Reg == ARM::LR) {
633 // Special epilogue for vararg functions. See emitEpilogue
634 if (isVarArg)
635 continue;
636 Reg = ARM::PC;
637 PopMI->setInstrDescriptor(get(ARM::tPOP_RET));
638 MBB.erase(MI);
639 }
640 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
641 }
642 return true;
643 }
644
600645 bool ARMInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
601646 if (MBB.empty()) return false;
602647
183183 SmallVectorImpl &Addr,
184184 const TargetRegisterClass *RC,
185185 SmallVectorImpl &NewMIs) const;
186 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
187 MachineBasicBlock::iterator MI,
188 const std::vector &CSI) const;
189 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
190 MachineBasicBlock::iterator MI,
191 const std::vector &CSI) const;
186192 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
187193 virtual bool ReverseBranchCondition(std::vector &Cond) const;
188194
8585 : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
8686 TII(tii), STI(sti),
8787 FramePtr((STI.useThumbBacktraces() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
88 }
89
90 bool ARMRegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
91 MachineBasicBlock::iterator MI,
92 const std::vector &CSI) const {
93 MachineFunction &MF = *MBB.getParent();
94 ARMFunctionInfo *AFI = MF.getInfo();
95 if (!AFI->isThumbFunction() || CSI.empty())
96 return false;
97
98 MachineInstrBuilder MIB = BuildMI(MBB, MI, TII.get(ARM::tPUSH));
99 for (unsigned i = CSI.size(); i != 0; --i) {
100 unsigned Reg = CSI[i-1].getReg();
101 // Add the callee-saved register as live-in. It's killed at the spill.
102 MBB.addLiveIn(Reg);
103 MIB.addReg(Reg, false/*isDef*/,false/*isImp*/,true/*isKill*/);
104 }
105 return true;
106 }
107
108 bool ARMRegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
109 MachineBasicBlock::iterator MI,
110 const std::vector &CSI) const {
111 MachineFunction &MF = *MBB.getParent();
112 ARMFunctionInfo *AFI = MF.getInfo();
113 if (!AFI->isThumbFunction() || CSI.empty())
114 return false;
115
116 bool isVarArg = AFI->getVarArgsRegSaveSize() > 0;
117 MachineInstr *PopMI = new MachineInstr(TII.get(ARM::tPOP));
118 MBB.insert(MI, PopMI);
119 for (unsigned i = CSI.size(); i != 0; --i) {
120 unsigned Reg = CSI[i-1].getReg();
121 if (Reg == ARM::LR) {
122 // Special epilogue for vararg functions. See emitEpilogue
123 if (isVarArg)
124 continue;
125 Reg = ARM::PC;
126 PopMI->setInstrDescriptor(TII.get(ARM::tPOP_RET));
127 MBB.erase(MI);
128 }
129 PopMI->addOperand(MachineOperand::CreateReg(Reg, true));
130 }
131 return true;
13288 }
13389
13490 static inline
3636 static unsigned getRegisterNumbering(unsigned RegEnum);
3737
3838 /// Code Generation virtual methods...
39 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
40 MachineBasicBlock::iterator MI,
41 const std::vector &CSI) const;
42
43 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
44 MachineBasicBlock::iterator MI,
45 const std::vector &CSI) const;
46
4739 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
4840 unsigned DestReg, const MachineInstr *Orig) const;
4941
2828 IA64RegisterInfo(const TargetInstrInfo &tii);
2929
3030 /// Code Generation virtual methods...
31 void copyRegToReg(MachineBasicBlock &MBB,
32 MachineBasicBlock::iterator MI,
33 unsigned DestReg, unsigned SrcReg,
34 const TargetRegisterClass *DestRC,
35 const TargetRegisterClass *SrcRC) const;
36
3731 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
3832 unsigned DestReg, const MachineInstr *Orig) const;
3933
1414 #include "X86.h"
1515 #include "X86GenInstrInfo.inc"
1616 #include "X86InstrBuilder.h"
17 #include "X86MachineFunctionInfo.h"
1718 #include "X86Subtarget.h"
1819 #include "X86TargetMachine.h"
1920 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
2022 #include "llvm/CodeGen/MachineInstrBuilder.h"
2123 #include "llvm/CodeGen/MachineRegisterInfo.h"
2224 #include "llvm/CodeGen/LiveVariables.h"
961963 NewMIs.push_back(MIB);
962964 }
963965
966 bool X86InstrInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
967 MachineBasicBlock::iterator MI,
968 const std::vector &CSI) const {
969 if (CSI.empty())
970 return false;
971
972 bool is64Bit = TM.getSubtarget().is64Bit();
973 unsigned SlotSize = is64Bit ? 8 : 4;
974
975 MachineFunction &MF = *MBB.getParent();
976 X86MachineFunctionInfo *X86FI = MF.getInfo();
977 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
978
979 unsigned Opc = is64Bit ? X86::PUSH64r : X86::PUSH32r;
980 for (unsigned i = CSI.size(); i != 0; --i) {
981 unsigned Reg = CSI[i-1].getReg();
982 // Add the callee-saved register as live-in. It's killed at the spill.
983 MBB.addLiveIn(Reg);
984 BuildMI(MBB, MI, get(Opc)).addReg(Reg);
985 }
986 return true;
987 }
988
989 bool X86InstrInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
990 MachineBasicBlock::iterator MI,
991 const std::vector &CSI) const {
992 if (CSI.empty())
993 return false;
994
995 bool is64Bit = TM.getSubtarget().is64Bit();
996
997 unsigned Opc = is64Bit ? X86::POP64r : X86::POP32r;
998 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
999 unsigned Reg = CSI[i].getReg();
1000 BuildMI(MBB, MI, get(Opc), Reg);
1001 }
1002 return true;
1003 }
1004
9641005 bool X86InstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
9651006 if (MBB.empty()) return false;
9661007
295295 SmallVectorImpl &Addr,
296296 const TargetRegisterClass *RC,
297297 SmallVectorImpl &NewMIs) const;
298
299 virtual bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
300 MachineBasicBlock::iterator MI,
301 const std::vector &CSI) const;
302
303 virtual bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
304 MachineBasicBlock::iterator MI,
305 const std::vector &CSI) const;
306
298307 virtual bool BlockHasNoFallThrough(MachineBasicBlock &MBB) const;
299308 virtual bool ReverseBranchCondition(std::vector &Cond) const;
300309
740740 }
741741 }
742742
743 bool X86RegisterInfo::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
744 MachineBasicBlock::iterator MI,
745 const std::vector &CSI) const {
746 if (CSI.empty())
747 return false;
748
749 MachineFunction &MF = *MBB.getParent();
750 X86MachineFunctionInfo *X86FI = MF.getInfo();
751 X86FI->setCalleeSavedFrameSize(CSI.size() * SlotSize);
752 unsigned Opc = Is64Bit ? X86::PUSH64r : X86::PUSH32r;
753 for (unsigned i = CSI.size(); i != 0; --i) {
754 unsigned Reg = CSI[i-1].getReg();
755 // Add the callee-saved register as live-in. It's killed at the spill.
756 MBB.addLiveIn(Reg);
757 BuildMI(MBB, MI, TII.get(Opc)).addReg(Reg);
758 }
759 return true;
760 }
761
762 bool X86RegisterInfo::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
763 MachineBasicBlock::iterator MI,
764 const std::vector &CSI) const {
765 if (CSI.empty())
766 return false;
767
768 unsigned Opc = Is64Bit ? X86::POP64r : X86::POP32r;
769 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
770 unsigned Reg = CSI[i].getReg();
771 BuildMI(MBB, MI, TII.get(Opc), Reg);
772 }
773 return true;
774 }
775
776743 static const MachineInstrBuilder &X86InstrAddOperand(MachineInstrBuilder &MIB,
777744 MachineOperand &MO) {
778745 if (MO.isRegister())
9191 int getDwarfRegNum(unsigned RegNum, bool isEH) const;
9292
9393 /// Code Generation virtual methods...
94 ///
95 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MI,
97 const std::vector &CSI) const;
98
99 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
100 MachineBasicBlock::iterator MI,
101 const std::vector &CSI) const;
102
94 ///
10395 const TargetRegisterClass *
10496 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
10597