llvm.org GIT mirror llvm / d925fa7
AMDGPU/SI: Fix inst-select-load-smrd.mir on some builds Summary: For some reason instructions are being inserted in the wrong order with some builds. I'm not sure why this is happening. Reviewers: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D29325 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@293639 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 22 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
8383
8484 DebugLoc DL = I.getDebugLoc();
8585
86 MachineOperand Lo1(getSubOperand64(I.getOperand(1), AMDGPU::sub0));
87 MachineOperand Lo2(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
88
8689 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADD_U32), DstLo)
87 .add(getSubOperand64(I.getOperand(1), AMDGPU::sub0))
88 .add(getSubOperand64(I.getOperand(2), AMDGPU::sub0));
90 .add(Lo1)
91 .add(Lo2);
92
93 MachineOperand Hi1(getSubOperand64(I.getOperand(1), AMDGPU::sub1));
94 MachineOperand Hi2(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
8995
9096 BuildMI(*BB, &I, DL, TII.get(AMDGPU::S_ADDC_U32), DstHi)
91 .add(getSubOperand64(I.getOperand(1), AMDGPU::sub1))
92 .add(getSubOperand64(I.getOperand(2), AMDGPU::sub1));
97 .add(Hi1)
98 .add(Hi2);
9399
94100 BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), I.getOperand(0).getReg())
95101 .addReg(DstLo)
5151 # SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 4294967292
5252 # SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 3
5353 # SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
54 # SIVI: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
55 # SIVI: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
54 # SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
55 # SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
5656 # SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
57 # SIVI: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
58 # SIVI: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
57 # SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
58 # SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
5959 # SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
6060 # SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
6161 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
6565 # GCN: [[K_LO:%[0-9]+]] = S_MOV_B32 0
6666 # GCN: [[K_HI:%[0-9]+]] = S_MOV_B32 4
6767 # GCN: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
68 # GCN: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
69 # GCN: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
68 # GCN-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
69 # GCN-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
7070 # GCN: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
71 # GCN: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
72 # GCN: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
71 # GCN-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
72 # GCN-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
7373 # GCN: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
7474 # GCN: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
7575 # GCN: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
8686 # SIVI: [[K_LO:%[0-9]+]] = S_MOV_B32 0
8787 # SIVI: [[K_HI:%[0-9]+]] = S_MOV_B32 1
8888 # SIVI: [[K:%[0-9]+]] = REG_SEQUENCE [[K_LO]], 1, [[K_HI]], 2
89 # SIVI: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
90 # SIVI: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
89 # SIVI-DAG: [[K_SUB0:%[0-9]+]] = COPY [[K]].sub0
90 # SIVI-DAG: [[PTR_LO:%[0-9]+]] = COPY [[PTR]].sub0
9191 # SIVI: [[ADD_PTR_LO:%[0-9]+]] = S_ADD_U32 [[PTR_LO]], [[K_SUB0]]
92 # SIVI: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
93 # SIVI: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
92 # SIVI-DAG: [[K_SUB1:%[0-9]+]] = COPY [[K]].sub1
93 # SIVI-DAG: [[PTR_HI:%[0-9]+]] = COPY [[PTR]].sub1
9494 # SIVI: [[ADD_PTR_HI:%[0-9]+]] = S_ADDC_U32 [[PTR_HI]], [[K_SUB1]]
9595 # SIVI: [[ADD_PTR:%[0-9]+]] = REG_SEQUENCE [[ADD_PTR_LO]], 1, [[ADD_PTR_HI]], 2
9696 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0