llvm.org GIT mirror llvm / d907744
Revert "[APInt] Fix a few places that use APInt::getRawData to operate within the normal API." This reverts commit r301105, 4, 3 and 1, as a follow up of the previous revert, which broke even more bots. For reference: Revert "[APInt] Use operator<<= where possible. NFC" Revert "[APInt] Use operator<<= instead of shl where possible. NFC" Revert "[APInt] Use ashInPlace where possible." PR32754. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@301111 91177308-0d34-0410-b5e6-96231b3b80d8 Renato Golin 3 years ago
14 changed file(s) with 38 addition(s) and 46 deletion(s). Raw diff Collapse all Expand all
875875 return *this;
876876 }
877877
878 /// \brief Left-shift assignment function.
879 ///
880 /// Shifts *this left by shiftAmt and assigns the result to *this.
881 ///
882 /// \returns *this after shifting left by ShiftAmt
883 APInt &operator<<=(const APInt &ShiftAmt);
884
885878 /// @}
886879 /// \name Binary Operators
887880 /// @{
963956 /// \brief Left-shift function.
964957 ///
965958 /// Left-shift this APInt by shiftAmt.
966 APInt shl(const APInt &ShiftAmt) const {
967 APInt R(*this);
968 R <<= ShiftAmt;
969 return R;
970 }
959 APInt shl(const APInt &shiftAmt) const;
971960
972961 /// \brief Rotate left by rotateAmt.
973962 APInt rotl(const APInt &rotateAmt) const;
19481948 return true;
19491949 StringRef V = S.substr(2);
19501950 APInt A(V.size()*4, V, 16);
1951 Result = A.zextOrTrunc(A.getActiveBits());
1951 Result = APInt(A.getActiveBits(),
1952 ArrayRef(A.getRawData(), A.getNumWords()));
19521953 return false;
19531954 }
19541955
53425342 APInt Mask = APInt::getHighBitsSet(OpSizeInBits, OpSizeInBits - c1);
53435343 SDValue Shift;
53445344 if (c2 > c1) {
5345 Mask <<= c2 - c1;
5345 Mask = Mask.shl(c2 - c1);
53465346 SDLoc DL(N);
53475347 Shift = DAG.getNode(ISD::SHL, DL, VT, N0.getOperand(0),
53485348 DAG.getConstant(c2 - c1, DL, N1.getValueType()));
25882588 DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(I - J, dl, SHVT));
25892589
25902590 APInt Shift(Sz, 1);
2591 Shift <<= J;
2591 Shift = Shift.shl(J);
25922592 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(Shift, dl, VT));
25932593 Tmp = DAG.getNode(ISD::OR, dl, VT, Tmp, Tmp2);
25942594 }
157157 // and the low 64 bits here.
158158 if (DAG.getDataLayout().isBigEndian() &&
159159 CN->getValueType(0).getSimpleVT() == llvm::MVT::ppcf128) {
160 APInt Val = CN->getValueAPF().bitcastToAPInt().rotl(64);
160 uint64_t words[2] = { CN->getValueAPF().bitcastToAPInt().getRawData()[1],
161 CN->getValueAPF().bitcastToAPInt().getRawData()[0] };
162 APInt Val(128, words);
161163 return DAG.getConstant(Val, SDLoc(CN),
162164 TLI.getTypeToTransformTo(*DAG.getContext(),
163165 CN->getValueType(0)));
10571059 APInt C = cast(N)->getValueAPF().bitcastToAPInt();
10581060 SDLoc dl(N);
10591061 Lo = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1060 C.extractBits(64, 64)),
1062 APInt(64, C.getRawData()[1])),
10611063 dl, NVT);
10621064 Hi = DAG.getConstantFP(APFloat(DAG.EVTToAPFloatSemantics(NVT),
1063 C.extractBits(64, 0)),
1065 APInt(64, C.getRawData()[0])),
10641066 dl, NVT);
10651067 }
10661068
23222322 if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
23232323 computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, DemandedElts,
23242324 Depth + 1);
2325 KnownZero <<= *ShAmt;
2326 KnownOne <<= *ShAmt;
2325 KnownZero = KnownZero << *ShAmt;
2326 KnownOne = KnownOne << *ShAmt;
23272327 // Low bits are known zero.
23282328 KnownZero.setLowBits(ShAmt->getZExtValue());
23292329 }
41594159 auto SignExtendInReg = [&](APInt Val, llvm::EVT ConstantVT) {
41604160 unsigned FromBits = EVT.getScalarSizeInBits();
41614161 Val <<= Val.getBitWidth() - FromBits;
4162 Val.ashrInPlace(Val.getBitWidth() - FromBits);
4162 Val = Val.ashr(Val.getBitWidth() - FromBits);
41634163 return getConstant(Val, DL, ConstantVT);
41644164 };
41654165
17131713 bestWidth = width;
17141714 break;
17151715 }
1716 newMask <<= width;
1716 newMask = newMask << width;
17171717 }
17181718 }
17191719 }
29802980 Flags.setExact(true);
29812981 Op1 = DAG.getNode(ISD::SRA, dl, Op1.getValueType(), Op1, Amt, &Flags);
29822982 Created.push_back(Op1.getNode());
2983 d.ashrInPlace(ShAmt);
2983 d = d.ashr(ShAmt);
29842984 }
29852985
29862986 // Calculate the multiplicative inverse, using Newton's method.
15641564 Tmp = Tmp.zext(SrcBitSize);
15651565 Tmp = TempSrc.AggregateVal[SrcElt++].IntVal;
15661566 Tmp = Tmp.zext(DstBitSize);
1567 Tmp <<= ShiftAmt;
1567 Tmp = Tmp.shl(ShiftAmt);
15681568 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
15691569 Elt.IntVal |= Tmp;
15701570 }
843843
844844 // Otherwise, we have to shift the mantissa bits up to the right location
845845 APInt Tmp(width, mantissa);
846 Tmp <<= (unsigned)exp - 52;
846 Tmp = Tmp.shl((unsigned)exp - 52);
847847 return isNeg ? -Tmp : Tmp;
848848 }
849849
11271127
11281128 /// Left-shift this APInt by shiftAmt.
11291129 /// @brief Left-shift function.
1130 APInt &APInt::operator<<=(const APInt &shiftAmt) {
1130 APInt APInt::shl(const APInt &shiftAmt) const {
11311131 // It's undefined behavior in C to shift by BitWidth or greater.
1132 *this <<= (unsigned)shiftAmt.getLimitedValue(BitWidth);
1133 return *this;
1132 return shl((unsigned)shiftAmt.getLimitedValue(BitWidth));
11341133 }
11351134
11361135 void APInt::shlSlowCase(unsigned ShiftAmt) {
18511851 OpUsefulBits = 1;
18521852
18531853 if (MSB >= Imm) {
1854 OpUsefulBits <<= MSB - Imm + 1;
1854 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
18551855 --OpUsefulBits;
18561856 // The interesting part will be in the lower part of the result
18571857 getUsefulBits(Op, OpUsefulBits, Depth + 1);
18581858 // The interesting part was starting at Imm in the argument
1859 OpUsefulBits <<= Imm;
1859 OpUsefulBits = OpUsefulBits.shl(Imm);
18601860 } else {
1861 OpUsefulBits <<= MSB + 1;
1861 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
18621862 --OpUsefulBits;
18631863 // The interesting part will be shifted in the result
1864 OpUsefulBits <<= OpUsefulBits.getBitWidth() - Imm;
1864 OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
18651865 getUsefulBits(Op, OpUsefulBits, Depth + 1);
18661866 // The interesting part was at zero in the argument
18671867 OpUsefulBits.lshrInPlace(OpUsefulBits.getBitWidth() - Imm);
18911891 if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSL) {
18921892 // Shift Left
18931893 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
1894 Mask <<= ShiftAmt;
1894 Mask = Mask.shl(ShiftAmt);
18951895 getUsefulBits(Op, Mask, Depth + 1);
18961896 Mask.lshrInPlace(ShiftAmt);
18971897 } else if (AArch64_AM::getShiftType(ShiftTypeAndValue) == AArch64_AM::LSR) {
19011901 uint64_t ShiftAmt = AArch64_AM::getShiftValue(ShiftTypeAndValue);
19021902 Mask.lshrInPlace(ShiftAmt);
19031903 getUsefulBits(Op, Mask, Depth + 1);
1904 Mask <<= ShiftAmt;
1904 Mask = Mask.shl(ShiftAmt);
19051905 } else
19061906 return;
19071907
19291929 uint64_t Width = MSB - Imm + 1;
19301930 uint64_t LSB = Imm;
19311931
1932 OpUsefulBits <<= Width;
1932 OpUsefulBits = OpUsefulBits.shl(Width);
19331933 --OpUsefulBits;
19341934
19351935 if (Op.getOperand(1) == Orig) {
19361936 // Copy the low bits from the result to bits starting from LSB.
19371937 Mask = ResultUsefulBits & OpUsefulBits;
1938 Mask <<= LSB;
1938 Mask = Mask.shl(LSB);
19391939 }
19401940
19411941 if (Op.getOperand(0) == Orig)
19461946 uint64_t Width = MSB + 1;
19471947 uint64_t LSB = UsefulBits.getBitWidth() - Imm;
19481948
1949 OpUsefulBits <<= Width;
1949 OpUsefulBits = OpUsefulBits.shl(Width);
19501950 --OpUsefulBits;
1951 OpUsefulBits <<= LSB;
1951 OpUsefulBits = OpUsefulBits.shl(LSB);
19521952
19531953 if (Op.getOperand(1) == Orig) {
19541954 // Copy the bits from the result to the zero bits.
123123 // FP immediates are used only when setting GPRs, so they may be dealt
124124 // with like regular immediates from this point on.
125125 auto Expr = HexagonMCExpr::create(
126 MCConstantExpr::create(Val.bitcastToAPInt().getZExtValue(),
126 MCConstantExpr::create(*Val.bitcastToAPInt().getRawData(),
127127 AP.OutContext),
128128 AP.OutContext);
129129 HexagonMCInstrInfo::setMustExtend(*Expr, MustExtend);
2671626716 DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth + 1);
2671726717 unsigned ShAmt = ShiftImm->getZExtValue();
2671826718 if (Opc == X86ISD::VSHLI) {
26719 KnownZero <<= ShAmt;
26720 KnownOne <<= ShAmt;
26719 KnownZero = KnownZero << ShAmt;
26720 KnownOne = KnownOne << ShAmt;
2672126721 // Low bits are known zero.
2672226722 KnownZero.setLowBits(ShAmt);
2672326723 } else {
3105331053 N0.getOperand(1).getOpcode() == ISD::Constant) {
3105431054 SDValue N00 = N0.getOperand(0);
3105531055 APInt Mask = cast(N0.getOperand(1))->getAPIntValue();
31056 Mask <<= N1C->getAPIntValue();
31056 const APInt &ShAmt = N1C->getAPIntValue();
31057 Mask = Mask.shl(ShAmt);
3105731058 bool MaskOK = false;
3105831059 // We can handle cases concerning bit-widening nodes containing setcc_c if
3105931060 // we carefully interrogate the mask to make sure we are semantics
3126331264 unsigned ShiftImm = ShiftVal.getZExtValue();
3126431265 for (APInt &Elt : EltBits) {
3126531266 if (X86ISD::VSHLI == Opcode)
31266 Elt <<= ShiftImm;
31267 Elt = Elt.shl(ShiftImm);
3126731268 else if (X86ISD::VSRAI == Opcode)
31268 Elt.ashrInPlace(ShiftImm);
31269 Elt = Elt.ashr(ShiftImm);
3126931270 else
3127031271 Elt.lshrInPlace(ShiftImm);
3127131272 }
377377 for (unsigned i = 0; i != NumSubElts; ++i) {
378378 unsigned SubEltIdx = (NumSubElts - 1) - i;
379379 auto SubElt = cast(CDV->getElementAsConstant(SubEltIdx));
380 Count <<= BitWidth;
380 Count = Count.shl(BitWidth);
381381 Count |= SubElt->getValue().zextOrTrunc(64);
382382 }
383383 }
15611561 for (unsigned Lane = 0; Lane != NumLanes; ++Lane) {
15621562 APInt LaneElts = OpUndefElts.lshr(InnerVWidthPerLane * Lane);
15631563 LaneElts = LaneElts.getLoBits(InnerVWidthPerLane);
1564 LaneElts <<= InnerVWidthPerLane * (2 * Lane + OpNum);
1564 LaneElts = LaneElts.shl(InnerVWidthPerLane * (2 * Lane + OpNum));
15651565 UndefElts |= LaneElts;
15661566 }
15671567 }